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Unit 5
Microprocessor
Prepared by:Shubhangi Gaikar
Registers Involved In Each Instruction
Cycle:
• Memory address registers(MAR) : It is connected to the
address lines of the system bus. It specifies the address in
memory for a read or write operation.
• Memory Buffer Register(MBR) : It is connected to the data
lines of the system bus. It contains the value to be stored in
memory or the last value read from the memory.
• Program Counter(PC) : Holds the address of the next
instruction to be fetched.
• Instruction Register(IR) : Holds the last instruction fetched.
Instruction Cycle of Microprocessor
1.Fetch: In the fetch cycle, the CPU retrieves the instruction from
memory. The instruction is typically stored at the address specified
by the program counter (PC). The PC is then incremented to point to
the next instruction in memory.
2.Decode: In the decode cycle, the CPU interprets the instruction and
determines what operation needs to be performed. This involves
identifying the opcode and any operands that are needed to execute
the instruction.
3.Execute: In the execute cycle, the CPU performs the operation
specified by the instruction. This may involve reading or writing data
from or to memory, performing arithmetic or logic operations on
data, or manipulating the control flow of the program.
Fetch and Decode
Evolution of Microprocessor
Multicore processors
• A multicore processor is an integrated circuit that has two or
more processor cores attached for enhanced performance and
reduced power consumption. These processors also enable
more efficient simultaneous processing of multiple tasks, such
as with parallel processing and multithreading. A dual core
setup is similar to having multiple, separate processors installed
on a computer. However, because the two processors are
plugged into the same socket, the connection between them is
faster.
25 4/6/2024
Multi-core architectures
• Replicate multiple processor cores on a single die.
Core 1 Core 2 Core 3 Core 4
Multi-core CPU chip
26 4/6/2024
Multi-core CPU chip
• The cores fit on a single processor socket
• Also called CMP (Chip Multi-Processor)
c
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1
c
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r
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2
c
o
r
e
3
c
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4
27 4/6/2024
The cores run in parallel
c
o
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1
c
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2
c
o
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3
c
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4
thread 1 thread 2 thread 3 thread 4
28 4/6/2024
Within each core, threads are time-sliced (just
like on a uniprocessor)
c
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1
c
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c
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3
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several
threads
several
threads
several
threads
several
threads
29 4/6/2024
Interaction with OS
• OS perceives each core as a separate processor
• OS scheduler maps threads/processes
to different cores
• Most major OS support multi-core today
30 4/6/2024
Why multi-core ?
• Difficult to make single-core
clock frequencies even higher
• Many new applications are
multithreaded
• General trend in computer
architecture (shift towards
more parallelism)
31 4/6/2024
Instruction-level parallelism
• Parallelism at the machine-instruction level
• The processor can re-order, pipeline instructions, split them into
microinstructions, do aggressive branch prediction, etc.
• Instruction-level parallelism enabled rapid increases in processor
speeds over the last 15 years
32 4/6/2024
Thread-level parallelism (TLP)
• This is parallelism on a more coarser scale
• Server can serve each client in a separate thread (Web
server, database server)
• A computer game can do AI, graphics, and physics in
three separate threads
• Single-core superscalar processors cannot fully exploit
TLP
• Multi-core architectures are the next step in processor
evolution: explicitly exploiting TLP
33 4/6/2024
Multiprocessor memory types
• Shared memory:
In this model, there is one (large) common shared memory for all
processors
• Distributed memory:
In this model, each processor has its own (small) local memory, and
its content is not replicated anywhere else
34 4/6/2024
Multi-core processor is a special kind of a
multiprocessor:
All processors are on the same chip
• Multi-core processors are MIMD:
Different cores execute different threads (Multiple
Instructions), operating on different parts of memory
(Multiple Data).
• Multi-core is a shared memory multiprocessor:
All cores share the same memory
35
4/6/2024
What applications benefit
from multi-core?
• Database servers
• Web servers (Web commerce)
• Telecommuncation markets:
6WINDGate (datapath and control
plane)
• Multimedia applications
• Scientific applications, CAD/CAM
• In general, applications with
Thread-level parallelism
(as opposed to instruction-level
parallelism)
Each can
run on its
own core
36 4/6/2024
More examples
• Editing a photo while recording a TV show through a digital video
recorder
• Downloading software while running an anti-virus program
• “Anything that can be threaded today will map efficiently to multi-
core”
• BUT: some applications difficult to
parallelize
37 4/6/2024
Simultaneous multithreading (SMT)
• Permits multiple independent threads to execute
SIMULTANEOUSLY on the SAME core
• Weaving together multiple “threads”
on the same core
• Example: if one thread is waiting for a floating point
operation to complete, another thread can use the
integer units

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fundamentals of digital communication Unit 5_microprocessor.pdf

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  • 6. Registers Involved In Each Instruction Cycle: • Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies the address in memory for a read or write operation. • Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the value to be stored in memory or the last value read from the memory. • Program Counter(PC) : Holds the address of the next instruction to be fetched. • Instruction Register(IR) : Holds the last instruction fetched.
  • 7. Instruction Cycle of Microprocessor 1.Fetch: In the fetch cycle, the CPU retrieves the instruction from memory. The instruction is typically stored at the address specified by the program counter (PC). The PC is then incremented to point to the next instruction in memory. 2.Decode: In the decode cycle, the CPU interprets the instruction and determines what operation needs to be performed. This involves identifying the opcode and any operands that are needed to execute the instruction. 3.Execute: In the execute cycle, the CPU performs the operation specified by the instruction. This may involve reading or writing data from or to memory, performing arithmetic or logic operations on data, or manipulating the control flow of the program.
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  • 22. Multicore processors • A multicore processor is an integrated circuit that has two or more processor cores attached for enhanced performance and reduced power consumption. These processors also enable more efficient simultaneous processing of multiple tasks, such as with parallel processing and multithreading. A dual core setup is similar to having multiple, separate processors installed on a computer. However, because the two processors are plugged into the same socket, the connection between them is faster.
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  • 25. 25 4/6/2024 Multi-core architectures • Replicate multiple processor cores on a single die. Core 1 Core 2 Core 3 Core 4 Multi-core CPU chip
  • 26. 26 4/6/2024 Multi-core CPU chip • The cores fit on a single processor socket • Also called CMP (Chip Multi-Processor) c o r e 1 c o r e 2 c o r e 3 c o r e 4
  • 27. 27 4/6/2024 The cores run in parallel c o r e 1 c o r e 2 c o r e 3 c o r e 4 thread 1 thread 2 thread 3 thread 4
  • 28. 28 4/6/2024 Within each core, threads are time-sliced (just like on a uniprocessor) c o r e 1 c o r e 2 c o r e 3 c o r e 4 several threads several threads several threads several threads
  • 29. 29 4/6/2024 Interaction with OS • OS perceives each core as a separate processor • OS scheduler maps threads/processes to different cores • Most major OS support multi-core today
  • 30. 30 4/6/2024 Why multi-core ? • Difficult to make single-core clock frequencies even higher • Many new applications are multithreaded • General trend in computer architecture (shift towards more parallelism)
  • 31. 31 4/6/2024 Instruction-level parallelism • Parallelism at the machine-instruction level • The processor can re-order, pipeline instructions, split them into microinstructions, do aggressive branch prediction, etc. • Instruction-level parallelism enabled rapid increases in processor speeds over the last 15 years
  • 32. 32 4/6/2024 Thread-level parallelism (TLP) • This is parallelism on a more coarser scale • Server can serve each client in a separate thread (Web server, database server) • A computer game can do AI, graphics, and physics in three separate threads • Single-core superscalar processors cannot fully exploit TLP • Multi-core architectures are the next step in processor evolution: explicitly exploiting TLP
  • 33. 33 4/6/2024 Multiprocessor memory types • Shared memory: In this model, there is one (large) common shared memory for all processors • Distributed memory: In this model, each processor has its own (small) local memory, and its content is not replicated anywhere else
  • 34. 34 4/6/2024 Multi-core processor is a special kind of a multiprocessor: All processors are on the same chip • Multi-core processors are MIMD: Different cores execute different threads (Multiple Instructions), operating on different parts of memory (Multiple Data). • Multi-core is a shared memory multiprocessor: All cores share the same memory
  • 35. 35 4/6/2024 What applications benefit from multi-core? • Database servers • Web servers (Web commerce) • Telecommuncation markets: 6WINDGate (datapath and control plane) • Multimedia applications • Scientific applications, CAD/CAM • In general, applications with Thread-level parallelism (as opposed to instruction-level parallelism) Each can run on its own core
  • 36. 36 4/6/2024 More examples • Editing a photo while recording a TV show through a digital video recorder • Downloading software while running an anti-virus program • “Anything that can be threaded today will map efficiently to multi- core” • BUT: some applications difficult to parallelize
  • 37. 37 4/6/2024 Simultaneous multithreading (SMT) • Permits multiple independent threads to execute SIMULTANEOUSLY on the SAME core • Weaving together multiple “threads” on the same core • Example: if one thread is waiting for a floating point operation to complete, another thread can use the integer units