International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
This document discusses the advantages of a 5T SRAM cell compared to a traditional 6T SRAM cell. It summarizes the design and operation of a 5T SRAM cell, which removes one transistor compared to a 6T cell. This reduces power consumption by eliminating the need to charge and discharge one of the bit lines during read and write operations. The document then describes the layout design of a 64-bit 5T SRAM using a 90nm technology node. It compares the performance of this 64-bit 5T SRAM to a 64-bit 6T SRAM in terms of power consumption, layout area, number of transistors, and leakage current.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IRJET- Low Voltage High Speed 8T SRAM Cell for Ultra-Low Power ApplicationsIRJET Journal
The document discusses an 8-transistor (8T) SRAM cell designed for low-power applications. The 8T SRAM cell aims to improve read and write operations at sub-threshold voltages down to 0.1V. It uses single-ended read and write operations enabled by additional access transistors. The 8T cell is proposed to reduce power consumption and delay compared to standard 6T and conventional 8T SRAM cells. Key aspects of the 8T cell include improved readability using a read assist technique and reduced dynamic power usage through two extra pass transistors.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
10T Dual-voltage Low Power SRAM Project ReportJie Song
This document describes a proposed 10T low power SRAM bit cell. It compares the proposed 10T cell to a conventional 6T cell. The 10T cell has higher read and write stability at low voltages and lower power consumption. Simulation results show the 10T cell has faster write time, lower write power, and similar read power and static power compared to the 6T cell. The document also describes the layout and peripheral circuits used to implement the 10T SRAM, including the clock generator, sense amplifier, and decoding circuits. Post-layout simulation results meeting timing requirements are presented.
Torque Profiles of Asymmetrically Wound Six-Phase Induction Motor (AWSP-IM) u...IOSR Journals
This document analyzes the torque profiles of an asymmetrically wound six-phase induction motor under various phase loss conditions through MATLAB/SIMULINK simulations. It examines scenarios where one, two, or three phases are lost, including losses of adjacent phases and non-adjacent phases. The analysis finds that phase losses increase torque ripple compared to normal six-phase operation. Losing adjacent phases causes more torque ripple than non-adjacent phases. Some phase loss scenarios produced results close to normal three-phase induction motor operation. The six-phase motor exhibits better performance than a three-phase motor under phase loss without control techniques.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
This document discusses the advantages of a 5T SRAM cell compared to a traditional 6T SRAM cell. It summarizes the design and operation of a 5T SRAM cell, which removes one transistor compared to a 6T cell. This reduces power consumption by eliminating the need to charge and discharge one of the bit lines during read and write operations. The document then describes the layout design of a 64-bit 5T SRAM using a 90nm technology node. It compares the performance of this 64-bit 5T SRAM to a 64-bit 6T SRAM in terms of power consumption, layout area, number of transistors, and leakage current.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IRJET- Low Voltage High Speed 8T SRAM Cell for Ultra-Low Power ApplicationsIRJET Journal
The document discusses an 8-transistor (8T) SRAM cell designed for low-power applications. The 8T SRAM cell aims to improve read and write operations at sub-threshold voltages down to 0.1V. It uses single-ended read and write operations enabled by additional access transistors. The 8T cell is proposed to reduce power consumption and delay compared to standard 6T and conventional 8T SRAM cells. Key aspects of the 8T cell include improved readability using a read assist technique and reduced dynamic power usage through two extra pass transistors.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
10T Dual-voltage Low Power SRAM Project ReportJie Song
This document describes a proposed 10T low power SRAM bit cell. It compares the proposed 10T cell to a conventional 6T cell. The 10T cell has higher read and write stability at low voltages and lower power consumption. Simulation results show the 10T cell has faster write time, lower write power, and similar read power and static power compared to the 6T cell. The document also describes the layout and peripheral circuits used to implement the 10T SRAM, including the clock generator, sense amplifier, and decoding circuits. Post-layout simulation results meeting timing requirements are presented.
Torque Profiles of Asymmetrically Wound Six-Phase Induction Motor (AWSP-IM) u...IOSR Journals
This document analyzes the torque profiles of an asymmetrically wound six-phase induction motor under various phase loss conditions through MATLAB/SIMULINK simulations. It examines scenarios where one, two, or three phases are lost, including losses of adjacent phases and non-adjacent phases. The analysis finds that phase losses increase torque ripple compared to normal six-phase operation. Losing adjacent phases causes more torque ripple than non-adjacent phases. Some phase loss scenarios produced results close to normal three-phase induction motor operation. The six-phase motor exhibits better performance than a three-phase motor under phase loss without control techniques.
Numerical Modelling of Wind Patterns around a Solar Parabolic Trough CollectorIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Voice over IP (VOIP) Security Research- A ResearchIJMER
This document summarizes research on Voice over IP (VoIP) security. It begins with an overview of SIP (Session Initiation Protocol), a commonly used VoIP standard, and a taxonomy of VoIP security threats. It then surveys existing research on VoIP security classified according to the threat categories. The research covers threats like eavesdropping, denial of service attacks, toll fraud, and spam over IP telephony (SPIT). Approaches studied include encryption, authentication, reputation systems, audio fingerprinting, and Turing tests to detect automated SPIT callers. The goal is to identify gaps and guide future work on analyzing VoIP attackers and improving the security and resilience of VoIP systems.
An Enhance PSO Based Approach for Solving Economical Ordered Quantity (EOQ) P...IJMER
The Meta-heuristic approaches can provide a sufficiently good solution to an
optimization problem, especially with incomplete or imperfect information and with lower
computational complexity especially for numerical solutions. This paper presents an enhanced PSO
(Particle Swarm Optimization) technique for solving the same problem. Through the PSO performs well
but it may require some more iteration to converge or sometimes many repetitions for the complex
problems. To overcome these problems an enhanced PSO is presented which utilizes the PSO with
double chaotic maps to perform irregular velocity updates which forces the particles to search greater
space for best global solution. Finally the comparison between both algorithms is performed for the
EOQ problem considering deteriorating items, shortages and partially backlogging. The simulation
results shows that the proposed enhanced PSO converges quickly and found much closer solution then
PSO.
Driver Fatigue Monitoring System Using Eye ClosureIJMER
Now-a-days so many road accidents occur due to driver distraction while he is driving.
Those accidents are broadly depends upon wide range of driver state such as drowsy state, alcoholic
state, depressed state etc. Even driver distraction and conversation with passengers during driving
can lead in major problems. To address the problem we propose a Driver fatigue Monitoring and
warning system based on eye-tracking, which is consider as active safety system. This system is useful
and helpful for drivers to be alert while driving. Eye tracking is one of the major technologies for
future driver system since human eyes contains much information. Sleepiness reduces reaction time of
safe driving. The driver distraction is measured by the person eye closure rate for certain period while
driving. It is implemented by comparing the image extracted from video and the video that is currently
performing. The percentage of eyes is compared from both the frames, if the driver is suspected to be
sleeping then a warning alarm is given to alert the driver.
Interstellar Communication Theories and its PossibilitiesIJMER
This paper reviews and discusses the research dimensions in four dimensional time travel and
time dependencies of future and past on the basis of present. The paper investigates the theories that
support time travel in any manner and explore possibilities based on them for interstellar communication
This document discusses websockets and their use for real-time communication. It begins with a definition of websockets as providing full-duplex communication channels over a single TCP connection. It then notes some key aspects of websockets like sending UTF-8 text or binary data, built-in heartbeating support, and browser support issues. The document highlights benefits of websockets like two-way communication and real-time data transfer without firewall interference but also notes compatibility concerns. It describes the websocket lifecycle and then outlines a project using websockets with Nginx, Node.js, and CoffeeScript for high-performance real-time applications across browsers.
The document describes various photos that were rejected for use in ancillary materials like front covers and billboards. The photos were rejected for reasons such as subjects having the wrong facial expressions, poor focus, visible equipment, hair obstructing faces, shadows obscuring faces, subjects too far apart or not looking at the camera. Explaining why each photo did not meet professional standards for the intended use.
Experimental Investigation of Silica Fume and Steel Slag in ConcreteIJMER
This paper gives a review on replacements in concrete made out of various
industrial by-products like silica fume and steel slag in concrete Through my study a combined
replacement of steel slag and silica fume in (40, 50, 60, and 70) % and (10, 15, 20, and 25) %
and conduct a detailed experimental study on Compressive strength, split tensile strength,
flexural strength at age of (7, 28, 56 and 90) days and durability study on acid attack was also
determinedand investigates the potential use and optimum usage of steel slag and silica fume in
the production of concrete
The document discusses the simulation and development of a stepper motor to control the position of a shuttle disc in a badminton playing robot. It includes:
1) A description of the system components including the stepper motor, drive circuit, batteries, and shuttle disc load.
2) A MATLAB simulation of the stepper motor model to analyze performance at no load and rated load conditions.
3) Hardware implementation of the system to rotate the shuttle disc using a stepper motor and microcontroller drive. Testing showed accurate rotation within 0.02 degrees of the target position even with shuttles loaded.
The document discusses deconstructing a scene from the television show Hollyoaks to better understand the storylines of the show. Deconstructing the scene allowed the person to analyze how the scene contributed to ongoing plots and character development in a more detailed manner than just watching.
This document summarizes a research paper about using a Z-Source Inverter (ZSI) based STATCOM to enhance power quality in a thirty bus power system. It first provides background on power quality issues and how Flexible AC Transmission Systems (FACTS) devices like STATCOMs can help address them. It then describes the components and operation of a conventional STATCOM and introduces the ZSI as an alternative inverter topology. The research presented in the paper models and simulates a thirty bus system both with and without a ZSI-based STATCOM to study improvements in voltage regulation and reactive power compensation.
This document discusses various techniques for sentiment analysis of application reviews, including both statistical and natural language processing approaches. It describes how sentiment analysis can be used to analyze textual reviews and classify them as positive or negative. Several key techniques are discussed, such as using machine learning classifiers like Naive Bayes, extracting n-grams and sentiment-oriented words, and developing rule-based models using techniques like identifying parts of speech. The document also discusses using these techniques to perform sentiment analysis at both the document and aspect levels.
The document summarizes the design of an HDLC controller with CRC generation using VHDL. It discusses:
1. HDLC is a standard protocol that organizes data into frames for point-to-point transmission with error detection. It includes address, control and CRC fields.
2. The design of the HDLC controller includes transmitter and receiver sections. The transmitter adds flag sequences and CRC to frames. The receiver detects flags, removes stuffing and checks the CRC.
3. Simulation results show the controller can generate and check CRC to detect errors for an example transmission of an 8-bit data byte and 8-bit address.
Enhancement in viscosity of diesel by adding vegetable oilIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Theoretical and graphical analysis of abrasivewater jetturningIJMER
This document presents a theoretical and graphical analysis of abrasive water jet turning. It begins with an abstract that describes using finite element analysis to simulate the impact of abrasive particles on stainless steel in abrasive water jet machining. The influences of impact angle and particle velocity were observed. The results of the FEA simulation agreed well with experimental validation. The objective of the present work is to develop a mathematical model considering the variation in jet impact angle and kerf profile to predict the final diameter achieved in abrasive water jet turning of ductile and brittle materials. Various distributions are evaluated to represent the kerf shape, with a sine function found to better represent the observed kerf geometry than exponential and cosine functions.
This document discusses methods for reducing coupling between antennas located near each other. It focuses on using periodic structures, such as corrugated metal surfaces, to provide electromagnetic shielding between antennas. Periodic structures can give the surface an inductive or capacitive impedance that attenuates electromagnetic fields and reduces coupling. Structures with quarter-wavelength deep slots can reflect plane waves with no phase reversal, further reducing coupling. While useful, periodic structures work best at wavelengths much smaller than the period. More research is still needed to develop new designs and models to improve electromagnetic compatibility between antennas.
El documento describe el Sistema Acústico USG TABLAROCA, que es ideal para hoteles, oficinas, hospitales y otros espacios. Se presentan diferentes configuraciones del sistema, incluyendo muros divisorios simples y dobles, así como plafones corridos simples y dobles. Se proporcionan detalles sobre los materiales utilizados y las pruebas de resistencia al sonido y al fuego realizadas.
Experimental Investigation of Performance & Emission Characteristics of Diese...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
The Three Phases of the Anti-Christ PowerRobert Taylor
This document outlines keys to unlocking prophecies in the Bible. It discusses various symbols found in prophecies and their meanings, such as beasts representing ruling powers. It analyzes prophecies about a beast with seven heads and ten horns in Revelation 12-13 and 17. This beast represents the papacy, which ruled as a head/empire for 1260 years before being wounded but healing. Biblical knowledge of the antichrist power and its mark are said to be the last message before Jesus' return. Intellectual biblical knowledge is presented as the greatest reformer of Christianity.
Maintenance Model of Hostel Buildings for Effective Performance and AestheticsIJMER
1. The document analyzes defects found in hostel buildings at The Polytechnic, Ibadan in Nigeria. Questionnaires were administered to evaluate and categorize defects.
2. Analysis of the questionnaires found that electrical systems, bathroom fixtures, door locks, and fire safety equipment like extinguishers and detectors were the most urgent defects requiring maintenance.
3. Defects were evaluated based on their mean scores and ranked. The most urgent defects across various areas of the buildings included faulty electrical sockets, damaged bathroom fixtures, and faulty door locks.
4. Attention to aesthetics and maintenance management is important for building management. Resources should be directed to the more urgent defects first while less urgent ones are addressed later.
Design of Low Power High Density SRAM Bit CellIRJET Journal
The document describes the design of a low power, high density 4T SRAM bit cell. It begins by introducing the motivation to minimize power and area in memory designs for portable devices. It then describes the conventional 6T SRAM cell and compares it to the proposed 4T cell. Simulation results show the 4T cell reduces power consumption by approximately 40% and area by 35% compared to the 6T cell. In conclusion, the 4T cell is shown to achieve both reduced power and area making it suitable for high density, low power memory applications.
IRJET- Deisgn of Low Power 16x16 Sram with Adiabatic LogicIRJET Journal
This document describes the design of a low power 16x16 SRAM array using adiabatic logic on a 180nm CMOS technology. It begins with an introduction to SRAM and discusses how large SRAM arrays are widely used in applications like cache memory and consume a significant chip area. It then provides background on adiabatic logic and its advantages for low power design. The document outlines the architecture of the designed 16x16 SRAM array, including the key components like the SRAM cell, sense amplifier, and row/column decoders. It presents the schematics of these components and discusses their implementation. Simulation results showing the successful read and write operations are provided. The designed SRAM array achieves low power
Numerical Modelling of Wind Patterns around a Solar Parabolic Trough CollectorIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Voice over IP (VOIP) Security Research- A ResearchIJMER
This document summarizes research on Voice over IP (VoIP) security. It begins with an overview of SIP (Session Initiation Protocol), a commonly used VoIP standard, and a taxonomy of VoIP security threats. It then surveys existing research on VoIP security classified according to the threat categories. The research covers threats like eavesdropping, denial of service attacks, toll fraud, and spam over IP telephony (SPIT). Approaches studied include encryption, authentication, reputation systems, audio fingerprinting, and Turing tests to detect automated SPIT callers. The goal is to identify gaps and guide future work on analyzing VoIP attackers and improving the security and resilience of VoIP systems.
An Enhance PSO Based Approach for Solving Economical Ordered Quantity (EOQ) P...IJMER
The Meta-heuristic approaches can provide a sufficiently good solution to an
optimization problem, especially with incomplete or imperfect information and with lower
computational complexity especially for numerical solutions. This paper presents an enhanced PSO
(Particle Swarm Optimization) technique for solving the same problem. Through the PSO performs well
but it may require some more iteration to converge or sometimes many repetitions for the complex
problems. To overcome these problems an enhanced PSO is presented which utilizes the PSO with
double chaotic maps to perform irregular velocity updates which forces the particles to search greater
space for best global solution. Finally the comparison between both algorithms is performed for the
EOQ problem considering deteriorating items, shortages and partially backlogging. The simulation
results shows that the proposed enhanced PSO converges quickly and found much closer solution then
PSO.
Driver Fatigue Monitoring System Using Eye ClosureIJMER
Now-a-days so many road accidents occur due to driver distraction while he is driving.
Those accidents are broadly depends upon wide range of driver state such as drowsy state, alcoholic
state, depressed state etc. Even driver distraction and conversation with passengers during driving
can lead in major problems. To address the problem we propose a Driver fatigue Monitoring and
warning system based on eye-tracking, which is consider as active safety system. This system is useful
and helpful for drivers to be alert while driving. Eye tracking is one of the major technologies for
future driver system since human eyes contains much information. Sleepiness reduces reaction time of
safe driving. The driver distraction is measured by the person eye closure rate for certain period while
driving. It is implemented by comparing the image extracted from video and the video that is currently
performing. The percentage of eyes is compared from both the frames, if the driver is suspected to be
sleeping then a warning alarm is given to alert the driver.
Interstellar Communication Theories and its PossibilitiesIJMER
This paper reviews and discusses the research dimensions in four dimensional time travel and
time dependencies of future and past on the basis of present. The paper investigates the theories that
support time travel in any manner and explore possibilities based on them for interstellar communication
This document discusses websockets and their use for real-time communication. It begins with a definition of websockets as providing full-duplex communication channels over a single TCP connection. It then notes some key aspects of websockets like sending UTF-8 text or binary data, built-in heartbeating support, and browser support issues. The document highlights benefits of websockets like two-way communication and real-time data transfer without firewall interference but also notes compatibility concerns. It describes the websocket lifecycle and then outlines a project using websockets with Nginx, Node.js, and CoffeeScript for high-performance real-time applications across browsers.
The document describes various photos that were rejected for use in ancillary materials like front covers and billboards. The photos were rejected for reasons such as subjects having the wrong facial expressions, poor focus, visible equipment, hair obstructing faces, shadows obscuring faces, subjects too far apart or not looking at the camera. Explaining why each photo did not meet professional standards for the intended use.
Experimental Investigation of Silica Fume and Steel Slag in ConcreteIJMER
This paper gives a review on replacements in concrete made out of various
industrial by-products like silica fume and steel slag in concrete Through my study a combined
replacement of steel slag and silica fume in (40, 50, 60, and 70) % and (10, 15, 20, and 25) %
and conduct a detailed experimental study on Compressive strength, split tensile strength,
flexural strength at age of (7, 28, 56 and 90) days and durability study on acid attack was also
determinedand investigates the potential use and optimum usage of steel slag and silica fume in
the production of concrete
The document discusses the simulation and development of a stepper motor to control the position of a shuttle disc in a badminton playing robot. It includes:
1) A description of the system components including the stepper motor, drive circuit, batteries, and shuttle disc load.
2) A MATLAB simulation of the stepper motor model to analyze performance at no load and rated load conditions.
3) Hardware implementation of the system to rotate the shuttle disc using a stepper motor and microcontroller drive. Testing showed accurate rotation within 0.02 degrees of the target position even with shuttles loaded.
The document discusses deconstructing a scene from the television show Hollyoaks to better understand the storylines of the show. Deconstructing the scene allowed the person to analyze how the scene contributed to ongoing plots and character development in a more detailed manner than just watching.
This document summarizes a research paper about using a Z-Source Inverter (ZSI) based STATCOM to enhance power quality in a thirty bus power system. It first provides background on power quality issues and how Flexible AC Transmission Systems (FACTS) devices like STATCOMs can help address them. It then describes the components and operation of a conventional STATCOM and introduces the ZSI as an alternative inverter topology. The research presented in the paper models and simulates a thirty bus system both with and without a ZSI-based STATCOM to study improvements in voltage regulation and reactive power compensation.
This document discusses various techniques for sentiment analysis of application reviews, including both statistical and natural language processing approaches. It describes how sentiment analysis can be used to analyze textual reviews and classify them as positive or negative. Several key techniques are discussed, such as using machine learning classifiers like Naive Bayes, extracting n-grams and sentiment-oriented words, and developing rule-based models using techniques like identifying parts of speech. The document also discusses using these techniques to perform sentiment analysis at both the document and aspect levels.
The document summarizes the design of an HDLC controller with CRC generation using VHDL. It discusses:
1. HDLC is a standard protocol that organizes data into frames for point-to-point transmission with error detection. It includes address, control and CRC fields.
2. The design of the HDLC controller includes transmitter and receiver sections. The transmitter adds flag sequences and CRC to frames. The receiver detects flags, removes stuffing and checks the CRC.
3. Simulation results show the controller can generate and check CRC to detect errors for an example transmission of an 8-bit data byte and 8-bit address.
Enhancement in viscosity of diesel by adding vegetable oilIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Theoretical and graphical analysis of abrasivewater jetturningIJMER
This document presents a theoretical and graphical analysis of abrasive water jet turning. It begins with an abstract that describes using finite element analysis to simulate the impact of abrasive particles on stainless steel in abrasive water jet machining. The influences of impact angle and particle velocity were observed. The results of the FEA simulation agreed well with experimental validation. The objective of the present work is to develop a mathematical model considering the variation in jet impact angle and kerf profile to predict the final diameter achieved in abrasive water jet turning of ductile and brittle materials. Various distributions are evaluated to represent the kerf shape, with a sine function found to better represent the observed kerf geometry than exponential and cosine functions.
This document discusses methods for reducing coupling between antennas located near each other. It focuses on using periodic structures, such as corrugated metal surfaces, to provide electromagnetic shielding between antennas. Periodic structures can give the surface an inductive or capacitive impedance that attenuates electromagnetic fields and reduces coupling. Structures with quarter-wavelength deep slots can reflect plane waves with no phase reversal, further reducing coupling. While useful, periodic structures work best at wavelengths much smaller than the period. More research is still needed to develop new designs and models to improve electromagnetic compatibility between antennas.
El documento describe el Sistema Acústico USG TABLAROCA, que es ideal para hoteles, oficinas, hospitales y otros espacios. Se presentan diferentes configuraciones del sistema, incluyendo muros divisorios simples y dobles, así como plafones corridos simples y dobles. Se proporcionan detalles sobre los materiales utilizados y las pruebas de resistencia al sonido y al fuego realizadas.
Experimental Investigation of Performance & Emission Characteristics of Diese...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
The Three Phases of the Anti-Christ PowerRobert Taylor
This document outlines keys to unlocking prophecies in the Bible. It discusses various symbols found in prophecies and their meanings, such as beasts representing ruling powers. It analyzes prophecies about a beast with seven heads and ten horns in Revelation 12-13 and 17. This beast represents the papacy, which ruled as a head/empire for 1260 years before being wounded but healing. Biblical knowledge of the antichrist power and its mark are said to be the last message before Jesus' return. Intellectual biblical knowledge is presented as the greatest reformer of Christianity.
Maintenance Model of Hostel Buildings for Effective Performance and AestheticsIJMER
1. The document analyzes defects found in hostel buildings at The Polytechnic, Ibadan in Nigeria. Questionnaires were administered to evaluate and categorize defects.
2. Analysis of the questionnaires found that electrical systems, bathroom fixtures, door locks, and fire safety equipment like extinguishers and detectors were the most urgent defects requiring maintenance.
3. Defects were evaluated based on their mean scores and ranked. The most urgent defects across various areas of the buildings included faulty electrical sockets, damaged bathroom fixtures, and faulty door locks.
4. Attention to aesthetics and maintenance management is important for building management. Resources should be directed to the more urgent defects first while less urgent ones are addressed later.
Design of Low Power High Density SRAM Bit CellIRJET Journal
The document describes the design of a low power, high density 4T SRAM bit cell. It begins by introducing the motivation to minimize power and area in memory designs for portable devices. It then describes the conventional 6T SRAM cell and compares it to the proposed 4T cell. Simulation results show the 4T cell reduces power consumption by approximately 40% and area by 35% compared to the 6T cell. In conclusion, the 4T cell is shown to achieve both reduced power and area making it suitable for high density, low power memory applications.
IRJET- Deisgn of Low Power 16x16 Sram with Adiabatic LogicIRJET Journal
This document describes the design of a low power 16x16 SRAM array using adiabatic logic on a 180nm CMOS technology. It begins with an introduction to SRAM and discusses how large SRAM arrays are widely used in applications like cache memory and consume a significant chip area. It then provides background on adiabatic logic and its advantages for low power design. The document outlines the architecture of the designed 16x16 SRAM array, including the key components like the SRAM cell, sense amplifier, and row/column decoders. It presents the schematics of these components and discusses their implementation. Simulation results showing the successful read and write operations are provided. The designed SRAM array achieves low power
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...IRJET Journal
This document presents a performance analysis and comparison of NOR CAM cell designs implemented using CMOS-LP, CMOS-HP, and FinFET 16nm technologies. It describes the functionality of NOR CAM cells and different circuit implementations, including ones using XNOR transistor logic, XNOR transmission gate logic, and a novel XNOR switch stack logic. Simulation results show that the FinFET implementation has 15-19% lower power dissipation for BCAM cells and 19-25% lower power for TCAM cells compared to the CMOS-LP and CMOS-HP implementations. The FinFET implementation also has shorter delay times.
Study and Analysis of Low Power SRAM Memory Array at nano-scaled TechnologyIRJET Journal
This document summarizes a study analyzing the design of low-power SRAM memory arrays at nano-scaled CMOS technology. The study adapts a multi-threshold CMOS design to create a novel low-power 6T SRAM cell that can reduce power usage and access time by using transistors with different threshold voltages. Simulation results show that leakage power can be significantly reduced in the idle state, lowering overall power consumption. Various SRAM cell designs are reviewed and a 1KB SRAM memory array is implemented using the proposed low-power 6T SRAM cell to validate the approach.
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
The document summarizes research on reducing power consumption in 4T SRAM cells through a stacking technique. It describes the conventional 4T SRAM cell and its operations. A proposed design is presented using a stacking transistor controlled by a signal to reduce leakage current. Simulations using Tanner EDA show the proposed cell has lower maximum, minimum, and average power compared to the conventional cell during write operations. The stacking technique is effective for lowering power consumption in SRAM cells.
IRJET- Comparative Analysis of High Speed SRAM Cell for 90nm CMOS TechnologyIRJET Journal
This document presents a comparative analysis of 6T and 8T SRAM cells for 90nm CMOS technology. It begins with an abstract discussing the simulation of low power SRAM cells at different frequencies. The main body then provides background on SRAM cells, discusses related work analyzing 6T and 8T SRAM cell designs. It presents the architecture and operating principles of an 8T SRAM cell, including write and read modes. Simulation results show the 8T SRAM cell has lower dynamic power consumption than a 6T cell, with readings of 82 micro Watts for read and 120 micro Watts for write. Logic validation testing confirms the 8T cell correctly writes and reads input bit values.
The document discusses the advantages of a 5T SRAM compared to a conventional 6T SRAM. It summarizes the design and layout of a 64-bit 5T SRAM using a 90nm technology. Simulation results show that the 5T SRAM reduces power dissipation by 36.2-37.2% and leakage current by 35-36.6% compared to a 64-bit 6T SRAM, while also reducing the area by 30.2%. The document concludes that the 5T SRAM design provides improvements in power, leakage current and area over a conventional 6T SRAM.
This document describes the design and analysis of a 10T CMOS SRAM cell using 0.6 μm technology to reduce power consumption during write operations. It first discusses 6T SRAM cells and issues with scaling. It then presents the design of a conventional 6T SRAM cell in Microwind 2 using 0.6 μm technology files and describes its read/write operations. Next, it proposes a 10T SRAM cell with two tail transistors added to the pull down network and bit lines cross-coupled to these transistors. This is claimed to help control leakage current and efficiently charge/discharge bit lines during writes. Simulation results then show the proposed 10T cell reduces average write power consumption by 38.6% compared
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
IRJET- Design of Energy Efficient 8T SRAM Cell at 90nm TechnologyIRJET Journal
The document describes a study on designing an energy efficient 8-transistor (8T) static random access memory (SRAM) cell for use at 90nm technology. The proposed 8T SRAM cell enhances static noise margin for low power supply voltages, achieving higher write static noise margin than 6T and 8T SRAM cells at 300mV. It also has high read static noise margin similar to other cell designs while consuming less write power. Simulations of a 1-kb array of the 8T SRAM cells showed reduced read and write power/energy consumption compared to other cell designs. The 8T cell was designed and analyzed using CADENCE design tools at 90nm technology node to enable ultralow power applications.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IRJET- Modified Low Power Single Bit-Line Static Random-Access Memory Cell Ar...IRJET Journal
The document discusses a modified low power single bit-line static random access memory (SRAM) cell architecture. It begins by introducing the issues of power consumption in memory systems and discusses existing techniques to reduce power, including adiabatic logic. It then presents a previously proposed single bit-line SRAM cell with an adiabatically operated word line. The document goes on to propose a modification to this cell that eliminates one transistor, reducing power consumption from 0.498mW to 0.350mW without impacting stability or performance. Simulation results demonstrating the power reduction are shown and conclusions are drawn about the benefits of the modified low power cell.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An Innovative Design solution for minimizing Power Dissipation in SRAM CellIJERA Editor
Over the years, the development of the logic on the chip is increased. To sustain and drive the logic flow, various techniques and SRAM cell designs have been implemented. The basic element of memory design is 6T SRAM cell. But while dealing with this 6T SRAM cell there are some issues with the parametric analysis on the performance of the cell. This paper presents an innovative design idea of new 8T RAM cell with various parametric analysis. The proposed cell is compared with the standard cell in terms of different parameters such as area, speed and power consumption along with the loading effect with the increase in load capacitance on the cell. The structure is designed with CMOS 45 nm Technology with BSIM 4 MOS modelling using Microwind 3.5 software tool
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
This document summarizes an improved SRAM design implemented using Cadence. The focus was on developing a simplified design by reducing transistor count and replacing some conventional circuit designs. Key aspects of the SRAM design discussed include the 6T SRAM cell, transistor sizing considerations, precharge circuits, sense amplifiers, write amplifiers, decoders, control circuits including flip-flops and write select generators, and specifying input stimuli using digital vector files. The design aims to increase speed and reduce layout area of the SRAM.
A Study on Translucent Concrete Product and Its Properties by Using Optical F...IJMER
- Translucent concrete is a concrete based material with light-transferring properties,
obtained due to embedded light optical elements like Optical fibers used in concrete. Light is conducted
through the concrete from one end to the other. This results into a certain light pattern on the other
surface, depending on the fiber structure. Optical fibers transmit light so effectively that there is
virtually no loss of light conducted through the fibers. This paper deals with the modeling of such
translucent or transparent concrete blocks and panel and their usage and also the advantages it brings
in the field. The main purpose is to use sunlight as a light source to reduce the power consumption of
illumination and to use the optical fiber to sense the stress of structures and also use this concrete as an
architectural purpose of the building
Developing Cost Effective Automation for Cotton Seed DelintingIJMER
A low cost automation system for removal of lint from cottonseed is to be designed and
developed. The setup consists of stainless steel drum with stirrer in which cottonseeds having lint is mixed
with concentrated sulphuric acid. So lint will get burn. This lint free cottonseed treated with lime water to
neutralize acidic nature. After water washing this cottonseeds are used for agriculter purpose
Study & Testing Of Bio-Composite Material Based On Munja FibreIJMER
The incorporation of natural fibres such as munja fiber composites has gained
increasing applications both in many areas of Engineering and Technology. The aim of this study is to
evaluate mechanical properties such as flexural and tensile properties of reinforced epoxy composites.
This is mainly due to their applicable benefits as they are light weight and offer low cost compared to
synthetic fibre composites. Munja fibres recently have been a substitute material in many weight-critical
applications in areas such as aerospace, automotive and other high demanding industrial sectors. In
this study, natural munja fibre composites and munja/fibreglass hybrid composites were fabricated by a
combination of hand lay-up and cold-press methods. A new variety in munja fibre is the present work
the main aim of the work is to extract the neat fibre and is characterized for its flexural characteristics.
The composites are fabricated by reinforcing untreated and treated fibre and are tested for their
mechanical, properties strictly as per ASTM procedures.
Hybrid Engine (Stirling Engine + IC Engine + Electric Motor)IJMER
Hybrid engine is a combination of Stirling engine, IC engine and Electric motor. All these 3 are
connected together to a single shaft. The power source of the Stirling engine will be a Solar Panel. The aim of
this is to run the automobile using a Hybrid engine
Fabrication & Characterization of Bio Composite Materials Based On Sunnhemp F...IJMER
This document summarizes research on the fabrication and characterization of bio-composite materials using sunnhemp fibre. The document discusses how sunnhemp fibre was used to reinforce an epoxy matrix through hand lay-up methods. Various mechanical properties of the bio-composites were tested, including tensile, flexural, and impact properties. The results of the mechanical tests on the bio-composite specimens are presented. Potential applications of the sunnhemp fibre bio-composites are also suggested, such as in fall ceilings, partitions, packaging, automotive interiors, and toys.
Geochemistry and Genesis of Kammatturu Iron Ores of Devagiri Formation, Sandu...IJMER
The Greenstone belts of Karnataka are enriched in BIFs in Dharwar craton, where Iron
formations are confined to the basin shelf, clearly separated from the deeper-water iron formation that
accumulated at the basin margin and flanking the marine basin. Geochemical data procured in terms of
major, trace and REE are plotted in various diagrams to interpret the genesis of BIFs. Al2O3, Fe2O3 (T),
TiO2, CaO, and SiO2 abundances and ratios show a wide variation. Ni, Co, Zr, Sc, V, Rb, Sr, U, Th,
ΣREE, La, Ce and Eu anomalies and their binary relationships indicate that wherever the terrigenous
component has increased, the concentration of elements of felsic such as Zr and Hf has gone up. Elevated
concentrations of Ni, Co and Sc are contributed by chlorite and other components characteristic of basic
volcanic debris. The data suggest that these formations were generated by chemical and clastic
sedimentary processes on a shallow shelf. During transgression, chemical precipitation took place at the
sediment-water interface, whereas at the time of regression. Iron ore formed with sedimentary structures
and textures in Kammatturu area, in a setting where the water column was oxygenated.
Experimental Investigation on Characteristic Study of the Carbon Steel C45 in...IJMER
In this paper, the mechanical characteristics of C45 medium carbon steel are investigated
under various working conditions. The main characteristic to be studied on this paper is impact toughness
of the material with different configurations and the experiment were carried out on charpy impact testing
equipment. This study reveals the ability of the material to absorb energy up to failure for various
specimen configurations under different heat treated conditions and the corresponding results were
compared with the analysis outcome
Non linear analysis of Robot Gun Support Structure using Equivalent Dynamic A...IJMER
Robot guns are being increasingly employed in automotive manufacturing to replace
risky jobs and also to increase productivity. Using a single robot for a single operation proves to be
expensive. Hence for cost optimization, multiple guns are mounted on a single robot and multiple
operations are performed. Robot Gun structure is an efficient way in which multiple welds can be done
simultaneously. However mounting several weld guns on a single structure induces a variety of
dynamic loads, especially during movement of the robot arm as it maneuvers to reach the weld
locations. The primary idea employed in this paper, is to model those dynamic loads as equivalent G
force loads in FEA. This approach will be on the conservative side, and will be saving time and
subsequently cost efficient. The approach of the paper is towards creating a standard operating
procedure when it comes to analysis of such structures, with emphasis on deploying various technical
aspects of FEA such as Non Linear Geometry, Multipoint Constraint Contact Algorithm, Multizone
meshing .
Static Analysis of Go-Kart Chassis by Analytical and Solid Works SimulationIJMER
This paper aims to do modelling, simulation and performing the static analysis of a go
kart chassis consisting of Circular beams. Modelling, simulations and analysis are performed using 3-D
modelling software i.e. Solid Works and ANSYS according to the rulebook provided by Indian Society of
New Era Engineers (ISNEE) for National Go Kart Championship (NGKC-14).The maximum deflection is
determined by performing static analysis. Computed results are then compared to analytical calculation,
where it is found that the location of maximum deflection agrees well with theoretical approximation but
varies on magnitude aspect.
In récent year various vehicle introduced in market but due to limitation in
carbon émission and BS Séries limitd speed availability vehicle in the market and causing of
environnent pollution over few year There is need to decrease dependancy on fuel vehicle.
bicycle is to be modified for optional in the future To implement new technique using change in
pedal assembly and variable speed gearbox such as planetary gear optimise speed of vehicle
with variable speed ratio.To increase the efficiency of bicycle for confortable drive and to
reduce torque appli éd on bicycle. we introduced epicyclic gear box in which transmission done
throgh Chain Drive (i.e. Sprocket )to rear wheel with help of Epicyclical gear Box to give
number of différent Speed during driving.To reduce torque requirent in the cycle with change in
the pedal mechanism
Integration of Struts & Spring & Hibernate for Enterprise ApplicationsIJMER
This document discusses integrating the Spring, Struts, and Hibernate frameworks to develop enterprise applications. It provides an overview of each framework and their features. The Spring Framework is a lightweight, modular framework that allows for inversion of control and aspect-oriented programming. It can be used to develop any or all tiers of an application. The document proposes an architecture for an e-commerce website that integrates these three frameworks, with Spring handling the business layer, Struts the presentation layer, and Hibernate the data access layer. This modular approach allows for clear separation of concerns and reduces complexity in application development.
Microcontroller Based Automatic Sprinkler Irrigation SystemIJMER
Microcontroller based Automatic Sprinkler System is a new concept of using
intelligence power of embedded technology in the sprinkler irrigation work. Designed system replaces
the conventional manual work involved in sprinkler irrigation to automatic process. Using this system a
farmer is protected against adverse inhuman weather conditions, tedious work of changing over of
sprinkler water pipe lines & risk of accident due to high pressure in the water pipe line. Overall
sprinkler irrigation work is transformed in to a comfortableautomatic work. This system provides
flexibility & accuracy in respect of time set for the operation of a sprinkler water pipe lines. In present
work the author has designed and developed an automatic sprinkler irrigation system which is
controlled and monitored by a microcontroller interfaced with solenoid valves.
On some locally closed sets and spaces in Ideal Topological SpacesIJMER
This document introduces and studies the concept of δˆ s-locally closed sets in ideal topological spaces. Some key points:
- A subset A is δˆ s-locally closed if A can be written as the intersection of a δˆ s-open set and a δˆ s-closed set.
- Various properties of δˆ s-locally closed sets are introduced and characterized, including relationships to other concepts like generalized locally closed sets.
- It is shown that a subset A is δˆ s-locally closed if and only if A can be written as the intersection of a δˆ s-open set and the δˆ s-closure of A.
- Theore
Intrusion Detection and Forensics based on decision tree and Association rule...IJMER
This paper present an approach based on the combination of, two techniques using
decision tree and Association rule mining for Probe attack detection. This approach proves to be
better than the traditional approach of generating rules for fuzzy expert system by clustering methods.
Association rule mining for selecting the best attributes together and decision tree for identifying the
best parameters together to create the rules for fuzzy expert system. After that rules for fuzzy expert
system are generated using association rule mining and decision trees. Decision trees is generated for
dataset and to find the basic parameters for creating the membership functions of fuzzy inference
system. Membership functions are generated for the probe attack. Based on these rules we have
created the fuzzy inference system that is used as an input to neuro-fuzzy system. Fuzzy inference
system is loaded to neuro-fuzzy toolbox as an input and the final ANFIS structure is generated for
outcome of neuro-fuzzy approach. The experiments and evaluations of the proposed method were
done with NSL-KDD intrusion detection dataset. As the experimental results, the proposed approach
based on the combination of, two techniques using decision tree and Association rule mining
efficiently detected probe attacks. Experimental results shows better results for detecting intrusions as
compared to others existing methods
Natural Language Ambiguity and its Effect on Machine LearningIJMER
This document discusses natural language ambiguity and its effect on machine learning. It begins by introducing different types of ambiguity that exist in natural languages, including lexical, syntactic, semantic, discourse, and pragmatic ambiguities. It then examines how these ambiguities present challenges for computational linguistics and machine translation systems. Specifically, it notes that ambiguity is a major problem for computers in processing human language as they lack the world knowledge and context that humans use to resolve ambiguities. The document concludes by outlining the typical process of machine translation and how ambiguities can interfere with tasks like analysis, transfer, and generation of text in the target language.
Today in era of software industry there is no perfect software framework available for
analysis and software development. Currently there are enormous number of software development
process exists which can be implemented to stabilize the process of developing a software system. But no
perfect system is recognized till yet which can help software developers for opting of best software
development process. This paper present the framework of skillful system combined with Likert scale. With
the help of Likert scale we define a rule based model and delegate some mass score to every process and
develop one tool name as MuxSet which will help the software developers to select an appropriate
development process that may enhance the probability of system success.
Material Parameter and Effect of Thermal Load on Functionally Graded CylindersIJMER
The present study investigates the creep in a thick-walled composite cylinders made
up of aluminum/aluminum alloy matrix and reinforced with silicon carbide particles. The distribution
of SiCp is assumed to be either uniform or decreasing linearly from the inner to the outer radius of
the cylinder. The creep behavior of the cylinder has been described by threshold stress based creep
law with a stress exponent of 5. The composite cylinders are subjected to internal pressure which is
applied gradually and steady state condition of stress is assumed. The creep parameters required to
be used in creep law, are extracted by conducting regression analysis on the available experimental
results. The mathematical models have been developed to describe steady state creep in the composite
cylinder by using von-Mises criterion. Regression analysis is used to obtain the creep parameters
required in the study. The basic equilibrium equation of the cylinder and other constitutive equations
have been solved to obtain creep stresses in the cylinder. The effect of varying particle size, particle
content and temperature on the stresses in the composite cylinder has been analyzed. The study
revealed that the stress distributions in the cylinder do not vary significantly for various combinations
of particle size, particle content and operating temperature except for slight variation observed for
varying particle content. Functionally Graded Materials (FGMs) emerged and led to the development
of superior heat resistant materials.
Energy Audit is the systematic process for finding out the energy conservation
opportunities in industrial processes. The project carried out studies on various energy conservation
measures application in areas like lighting, motors, compressors, transformer, ventilation system etc.
In this investigation, studied the technical aspects of the various measures along with its cost benefit
analysis.
Investigation found that major areas of energy conservation are-
1. Energy efficient lighting schemes.
2. Use of electronic ballast instead of copper ballast.
3. Use of wind ventilators for ventilation.
4. Use of VFD for compressor.
5. Transparent roofing sheets to reduce energy consumption.
So Energy Audit is the only perfect & analyzed way of meeting the Industrial Energy Conservation.
An Implementation of I2C Slave Interface using Verilog HDLIJMER
This document describes the implementation of an I2C slave interface using Verilog HDL. It introduces the I2C protocol which uses only two bidirectional lines (SDA and SCL) for communication. The document discusses the I2C protocol specifications including start/stop conditions, addressing, read/write operations, and acknowledgements. It then provides details on designing an I2C slave module in Verilog that responds to commands from an I2C master and allows synchronization through clock stretching. The module is simulated in ModelSim and synthesized in Xilinx. Simulation waveforms demonstrate successful read and write operations to the slave device.
Discrete Model of Two Predators competing for One PreyIJMER
This paper investigates the dynamical behavior of a discrete model of one prey two
predator systems. The equilibrium points and their stability are analyzed. Time series plots are obtained
for different sets of parameter values. Also bifurcation diagrams are plotted to show dynamical behavior
of the system in selected range of growth parameter
Unlocking Productivity: Leveraging the Potential of Copilot in Microsoft 365, a presentation by Christoforos Vlachos, Senior Solutions Manager – Modern Workplace, Uni Systems
Cosa hanno in comune un mattoncino Lego e la backdoor XZ?Speck&Tech
ABSTRACT: A prima vista, un mattoncino Lego e la backdoor XZ potrebbero avere in comune il fatto di essere entrambi blocchi di costruzione, o dipendenze di progetti creativi e software. La realtà è che un mattoncino Lego e il caso della backdoor XZ hanno molto di più di tutto ciò in comune.
Partecipate alla presentazione per immergervi in una storia di interoperabilità, standard e formati aperti, per poi discutere del ruolo importante che i contributori hanno in una comunità open source sostenibile.
BIO: Sostenitrice del software libero e dei formati standard e aperti. È stata un membro attivo dei progetti Fedora e openSUSE e ha co-fondato l'Associazione LibreItalia dove è stata coinvolta in diversi eventi, migrazioni e formazione relativi a LibreOffice. In precedenza ha lavorato a migrazioni e corsi di formazione su LibreOffice per diverse amministrazioni pubbliche e privati. Da gennaio 2020 lavora in SUSE come Software Release Engineer per Uyuni e SUSE Manager e quando non segue la sua passione per i computer e per Geeko coltiva la sua curiosità per l'astronomia (da cui deriva il suo nickname deneb_alpha).
Dr. Sean Tan, Head of Data Science, Changi Airport Group
Discover how Changi Airport Group (CAG) leverages graph technologies and generative AI to revolutionize their search capabilities. This session delves into the unique search needs of CAG’s diverse passengers and customers, showcasing how graph data structures enhance the accuracy and relevance of AI-generated search results, mitigating the risk of “hallucinations” and improving the overall customer journey.
GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...Neo4j
Leonard Jayamohan, Partner & Generative AI Lead, Deloitte
This keynote will reveal how Deloitte leverages Neo4j’s graph power for groundbreaking digital twin solutions, achieving a staggering 100x performance boost. Discover the essential role knowledge graphs play in successful generative AI implementations. Plus, get an exclusive look at an innovative Neo4j + Generative AI solution Deloitte is developing in-house.
How to Get CNIC Information System with Paksim Ga.pptxdanishmna97
Pakdata Cf is a groundbreaking system designed to streamline and facilitate access to CNIC information. This innovative platform leverages advanced technology to provide users with efficient and secure access to their CNIC details.
Unlock the Future of Search with MongoDB Atlas_ Vector Search Unleashed.pdfMalak Abu Hammad
Discover how MongoDB Atlas and vector search technology can revolutionize your application's search capabilities. This comprehensive presentation covers:
* What is Vector Search?
* Importance and benefits of vector search
* Practical use cases across various industries
* Step-by-step implementation guide
* Live demos with code snippets
* Enhancing LLM capabilities with vector search
* Best practices and optimization strategies
Perfect for developers, AI enthusiasts, and tech leaders. Learn how to leverage MongoDB Atlas to deliver highly relevant, context-aware search results, transforming your data retrieval process. Stay ahead in tech innovation and maximize the potential of your applications.
#MongoDB #VectorSearch #AI #SemanticSearch #TechInnovation #DataScience #LLM #MachineLearning #SearchTechnology
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2024/06/building-and-scaling-ai-applications-with-the-nx-ai-manager-a-presentation-from-network-optix/
Robin van Emden, Senior Director of Data Science at Network Optix, presents the “Building and Scaling AI Applications with the Nx AI Manager,” tutorial at the May 2024 Embedded Vision Summit.
In this presentation, van Emden covers the basics of scaling edge AI solutions using the Nx tool kit. He emphasizes the process of developing AI models and deploying them globally. He also showcases the conversion of AI models and the creation of effective edge AI pipelines, with a focus on pre-processing, model conversion, selecting the appropriate inference engine for the target hardware and post-processing.
van Emden shows how Nx can simplify the developer’s life and facilitate a rapid transition from concept to production-ready applications.He provides valuable insights into developing scalable and efficient edge AI solutions, with a strong focus on practical implementation.
In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
Goodbye Windows 11: Make Way for Nitrux Linux 3.5.0!SOFTTECHHUB
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Optimized CAM Design
1. www.ijmer.com
International Journal of Modern Engineering Research (IJMER)
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645
ISSN: 2249-6645
Optimized CAM Design
S. Haroon Rasheed1, M. Anand Vijay Kamalnath2
Department of ECE, AVR & SVR E C T, Nandyal, India
Abstract:
Content-addressable memories (CAMs) are hardware search engines that are faster than algorithmic
approaches for searching applications. CAMs consist of conventional semiconductor memory (usually SRAM) with added
comparison circuitry that performs search operation to complete in a unique clock cycle. In case of sophisticated and high
end applications we need large sized CAM which utilizes large amount of power but this has to be avoided. This paper
proposes an idea for improving power, area and performance of the system of recently proposed high Performance HybridType CAM Designs. For this we replace the basic 9T CAM cell with a 4T CAM cell. The simulation results show the success
of the method.
Key words: Basic 9T CAM cell, 4T CAM cell, NOR-Type Array, NAND-Type Array, Hybrid CAM Design.
I.
INTRODUCTION
Content Addressable Memory is used to access the memory through the data rather than the address which is used
in the case of normal RAM‟s. The output of the CAM will be the location where the associated content is stored. In CAM
with parallel comparison feature the power consumption is lesser than the normal CAM. In case of CAM, the input data and
the stored data are being compared, if both matches then the match line are used to indicate it. Due to its low power and fast
matching capability it is mainly used in advanced applications like Strong ARM processors, ATM switches, etc.
In this paper we are designing a Hybrid Type CAM[7] design so that it should have low power and high
performance. Normally basic CAM cell consists of 9 transistors to write, read and match the data. It consists of both store
unit and match unit. The main drawback of this basic CAM cell is that it occupies more area, needs more power and has
large delay. So we need to explore modifications to it so that area, power and performance can be improved. So we are
designing 4 transistor CAM cell[8] such that these can be effectively used in many applications.
In the design CAM different techniques have been proposed to reduce the power consumption and improve the
performance of the CAM cell. A CAM cell design with XOR and XNOR blocks were designed [2], with different
combinations of pmos and nmos transistors, depending upon the type of application. But the main drawback of the proposed
design are usage of more number of transistors and more power consumption. A two stage CAM cell design is proposed [3],
to reduce power consumption where a control circuitry consisting of an inverter is used between the two stages. Performance
of this CAM cell design is degraded in this design and there exists the disadvantage of short circuit power dissipation. A
static pseudo nmos CAM has been designed[4] which requires an extra pmos transistor for every CAM cell which use in it,
so it is very bad idea to for each and every pmos for each stages. Other method has been designed which requires separate
cmos parallel CAM for searching the data[5] which requires lot of area to implement it and also extra precharge device[6] to
implement CAM. To overcome the disadvantages of the previous designs a Hybrid-Type CAM design[7] is proposed to
improve the power, area and performance of the CAM cell. This consists of both the NOR-type CAM design for the
high performance and NAND-type CAM design for Low-Power, as constraints.
II.
BASIC CONTENT ADDRESSABLE MEMORY
Basic CAM cell consists of both store unit for storing the data and compare unit for comparing the data. We store the data
using two cross-
Fig 1: Basic XOR CAM cell
coupled inverters and is implemented with 6T SRAM cell. The compare unit is designed using pass transistors. The fast pull
down transistor is used to discharge the data so that it indicates whether the data is matched. Depending on different
applications the compare unit can be designed with XOR type or XNOR type blocks. The main operation of CAM cell can
be described as: when the cross- coupled inverters store the data „1‟ and then the bit and nbit(bit bar/bitc) line has the data
„1‟ and „0‟ respectively. Now one of the two pull down transistors will be ON state and the other will be OFF state so that
there won‟t be any transistor path to discharge the match line and hence it remains in High-impedance state. Now if the bit
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2. International Journal of Modern Engineering Research (IJMER)
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645
ISSN: 2249-6645
and nbit line has the data „0‟ and „1‟ respectively, then in the compare unit one of the pull down transistor will be in ON state
so that the fast pull down transistor moves to ON state. This discharges the match line indicating that the data have been
matched.
Fig 2: Basic XNOR CAM cell
III.
MODIFIED CAM CELL (4T CELL)
This modified 4T CAM cell design consists of 4 nmos transistors and the cells are arranged such that the two
transistors (tc1 and tco) are used to store the data and the remaining two transistors (tw1 and tw0) are used to write the
data[8]. The gates of tc1(„a‟) and tco(„b‟) are used as storage capacitance elements so that it can be used to store the data as
shown in fig 3. When the transistors tw1 and tw0 are in ON state the data can be transferred to the nodes a and b and then
these can be read using transistors tc1 and tc0.
Fig 3:4T XOR CAM cell
Normally matching operation can be done using match line that is connected to the output of the XOR type
transistors which are arranged using transistors tc1 and tc0. If the match line output is at logic „1‟ that indicates that the „data
stored‟ and the „input data‟ are matched. If the match line output is at logic „0‟, it indicates that there is no match and then
the match line gets discharged. Basically in this operation, first the match line has to be charged to logic „1‟ by using
precharge transistor and then the matching operation can be done. Even in case of mismatch, the match line needs to be
discharged, which can be done by using read transistor that is arranged between match line and ground. Fig 4. Shows the 4T
XNOR CAMCell.
Fig 4: 4T XNOR CAM cell
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3. www.ijmer.com
International Journal of Modern Engineering Research (IJMER)
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645
ISSN: 2249-6645
IV.
NOR-TYPE CAM ARRAY
In NOR-type CAM cell design, XOR-type CAM cell is used for better performance of the system. Here the pulldown transistors are arranged in NOR fashion so that it can discharge very fast and hence the performance improves. In case
of pre-charge, the Match-line is precharged to HIGH.
Fig 5: NOR type CAM Array
In the Evaluation phase, if the input data is matched with the stored data then the match line remains HIGH and if
all the cells are mismatched then the Match-line will discharge through the pull-down transistors. Thus the NOR-type CAM
cell provides better performance. But the drawback in this design is increase in Drain-Capacitance due to more number of
transistors. This drawback, increases Power consumption. Hence, it is only useful in case of High performance.
V.
NAND-TYPE CAM ARRAY
Unlike the NOR-type CAM cell, NAND-type CAM cell is used to reduce the power consumption of the system. In
this the NAND-type CAM, cell is arranged using XNOR type and the transistors are arranged in NAND fashion.
Fig 6: NAND CAM Array
Since the drain capacitance is less, the power consumption of the system is also less. In searching the data, initially
the match line is precharged to HIGH, in the pre-charge phase and the match line discharges to ground in the evaluation
phase, only when all the CAM cells are matched with the stored data. In case of mismatch the match line remains HIGH as
in that of the pre-charge phase. Thus the power consumption of the system can be improved. But the drawback with this
design is the time taken to discharge the match line is more, as it has long pull-down path. Hence, this NAND-type design is
performance inefficient/slow.
VI.
HYBRID-TYPE CAM DESIGN
Hybrid-type CAM design consists of both NOR-type Array with XOR CAM cell for performance advantage and
NAND-type Array with XNOR CAM cell for power advantage. Mainly we divide the complete circuit into 3 parts namely,
SEG1, SEG2 and CONTROL circuitry. In the SEG 1, we design the circuit using XNOR type and then arrange the pulldown transistors using NAND-type. In the SEG 2, we design the circuit using XOR type and the pull-down transistors are
arranged in NOR type design as shown in fig.7.
Fig 7: HYBRID CAM Structure [Ref 7]
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645
ISSN: 2249-6645
SEARCH OPERATION OF CAM CELL
In case of searching a data, the input data is compared with that of stored data. The circuit operates in two different
phases namely Pre-charge phase and Evaluation Phase. In Pre-charge phase the Match-line is kept in HIGH state and in the
Evaluation Phase the state of Match-line depends upon the data matched.
1.
PRE-CHARGE PHASE
The control signal PRE is kept LOW so that the circuit starts to Pre-charge. Thus when the PRE signal is kept LOW
the match line that is connected to one of the pmos transistor P3 is made to be in HIGH state. In this circuit we have 3
discharge paths namely T1,T2 and T3 that are connected to three transistors N1, P5 and NOR block respectively. As both
the nodes M1 and M2 are HIGH, there are no discharge paths for the Match-line in this phase. As there is no chance of
discharging the data, the Match-line doesn‟t require much power. This design is very efficient in Power saving.
2. MATCH-EVALUATION PHASE
In this phase the control signal PRE is made HIGH to start the matching process of the design. The data to be
searched is given to the bit lines of the CAM cell. When we search the data we come across 4 different cases but the exact
matching occurs only when both the segments are matched. The voltages of each node are shown in Table.1. The detailed
explanation of this matching process is given below.
Case1: In this case, SEG1 is mismatched and SEG2 is mismatched or matched. As the SEG1 is mismatched there
exists no discharge path because there may be at least one transistor that is OFF. So the node voltage M1 remains HIGH and
hence, there won‟t be any discharge path. Thus in this case the matching process doesn‟t depend on the SEG2. As there is no
discharge path the Match-line still remains in the HIGH state.
Case2: In this case, SEG1 is matched and SEG2 is mismatched. As the SEG1 is matched all the transistors that are
connected in the NAND fashion are in ON state, so that there exists a discharge path through the path T1. And thus, the node
M1 remains LOW and the two pull-down transistor P5 gets ON and so, there exists a path T2 to discharge. Now as the SEG
2 is mismatched there exists at least one path to discharge through N3 so that the node M2 remains LOW. Hence in this case,
there won‟t be any path to discharge the match-line.
Table 1: Node Voltages of each node of HYBRID CAM Cell.
Case3: In this case, both the segments are matched. Thus, as the SEG1 is matched, the node M1 gets LOW value as
there exists a discharge path. Now in case of SEG2, as it is matched all the transistors are turned OFF and the path T3 to
ground is disconnected. Now the node M2 is at HIGH state making the transistor N4 to turn ON. Now there exists a path for
Match-line to discharge the data, through the paths T1 or T2. As the path T2 is the fastest path to discharge the data, the
Match-line discharges through the transistor P5. Thus it indicates that the data have been matched properly. In this design as
we have two pull-down paths to discharge the match-line. It discharges through path T2 as path T1 has transistors connected
which takes long time to discharge. Thus, this design provides better performance.
VII.
EXPERIMENTAL RESULTS
0.18um technology is used to implement the design. The below Figure 8 shows all the three cases of both SEG 1 and SEG 2
that have been used to search the data .
Table 2: Comparison between 9T and 4T
Thus, 9T CAM cell is compared with 4T CAM cell and the power of the CAM cell have been reduced by 3 times as
shown in Table 2.
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5. International Journal of Modern Engineering Research (IJMER)
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Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645
ISSN: 2249-6645
The NOR type and NAND CAM Arrays are also compared on the basis of power and performance as shown in
Tables 3 and 4.
Fig 8. Simulation results of HYBRID CAM
Table 3: NOR Type CAM Array
Table 4: NAND Type CAM Array
Thus, by combining NAND type CAM Array for power efficiency and NOR type CAM Array for performance
efficiency, the HYBRID DYNAMIC CAM design have been designed and it is observed that the design has low power
consumption and increased performance. The total power consumption of HYBRID CAM design is shown in Table 5.
Table 5: HYBRID CAM Design
Thus by observing the results we can say that by replacing 9T CAM cell with 4T CAM cell the power consumption
of the system has been improved and also its performance is also improved drastically. The above Figure 8 shows the
simulation results of HYBRID CAM cell, done using MENTOR GRAPHICS and all the three different cases of CAM cell
for matching the data is shown.
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6. www.ijmer.com
International Journal of Modern Engineering Research (IJMER)
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645
ISSN: 2249-6645
Fig 9: 4T CAM Cell layout in 0.18 um standard CMOS Technology.
VIII.
CONCLUSION
Thus, a HYBRID CAM Structure has been designed for Low Power and High Performance using NOR and NAND
type CAM Array and area of the complete system has been reduced by replacing 9T basic CAM cell with 4T CAM cell with
a fast pull down path to accelerate the search operation.
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