This document discusses various memory management techniques used in operating systems, including memory protection using base and limit registers, address binding at compile, load, and execution times, logical vs physical address spaces, memory allocation using contiguous and multiple partition schemes, segmentation using segment tables, and paging using page tables. Paging allows for non-contiguous allocation of physical memory through the use of pages and frames, address translation via a page table with page and offset, and protection bits. It aims to reduce fragmentation and support sharing of common code through reentrant code.

1. Operating System
Main Memory

2. Memory Management
Memory Accessing
- Registers
- Cache
- Main Memory
Stall
Hardware Address Protection
Base and Limit Registers

3. Address Binding
Input Queue
- Single-tasking Procedure
Binding
- Mapping of symbolic into logical Address
Steps of Binding
- Compile Time
- Load Time
- Execution Time

4. Logical vs Physical Address Space
Logical Address
- Logical Address Space
Physical Address
- Physical Address Space
Memory Management Unit (MMU)
Loading when called.
Better memory utilization.
Useful when large amount of code needs to
be handled.
Dynamic relocation using a
relocation register
Mapping of virtual into Physical Address
- Relocation Registers
- MS-DOS on Intel 80x86 used 4 relocation registers

5. Dynamic Linking
Static linking
Stub Program
Libraries
- shared libraries

6. Swapping
A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
Standard Swapping
Standard swapping involves moving processes between main memory
and Baking store.
• Backing store
• Roll out, roll in
• transfer time
• ready queue

7. Schematic View of Swapping

8. Context Switch Time including Swapping
• If next processes to be put on CPU is not in memory, need to swap out
a process and swap in target process
• Context switch time can then be very high
• 100MB process swapping to hard disk with transfer rate of 50MB/sec
• Swapping is constrained by other factors as well.
Pending I/O
Double buffering
Standard swapping not used in modern operating systems

9. Swapping on Mobile Systems
• Not typically supported
• Flash memory based
• Small amount of space
• Limited number of write cycles
• Poor throughput between flash memory and CPU on
mobile platform
• Instead use other methods to free memory if low
iOS asks
Read-only data
Failure to free
application state

10. Contiguous Memory Allocation
The main memory must accommodate
both the operating system and the
various user processes.
Main memory usually into two partitions.
- Resident operating system.
- User processes.
- single contiguous section.

11. • Relocation registers used to protect user processes
-Base register
-Limit register
-MMU maps
-transient
Memory Protection

12. Memory Allocation
Multiple-partition allocation
• Degree of multiprogramming limited by number of
partitions
• Variable-partition
• Hole
• process arrival
• Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

13. Dynamic Storage-Allocation Problem
• which concerns how to satisfy a request of size n from a
list of free holes.
• First-fit
• Best-fit
• Worst-fit

14. Fragmentation
• External Fragmentation
• Internal Fragmentation
Reduce external fragmentation by compaction
• Shuffle
• Compaction
• I/O problem

15. Segmentation
Memory segmentation is the division of a computer's
primary memory into segments or sections.
A program is a collection of segments.
A segment is a logical unit such as.
- main program
- procedure
- local variables
- global variables

16. User’s View of a Program Logical View of Segmentation
1
3
2
4
1
4
2
3
user space physical memory space

17. Segmentation Architecture
Logical address consists of a two tuple
<segment-number, offset>
Segment table.
- Base
- Limit
Segment-table base register (STBR)
Segment-table length register (STLR)
Protection
With each entry in segment table associate:
validation bit = 0  illegal segment
read/write/execute privileges
Protection bits
segments length

18. Segmentation Hardware

19. Paging
• Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
• Frames
• Pages
• Set up a page table to translate logical to physical addresses
• Backing store likewise split into pages
• Still have Internal fragmentation

20. Address Translation Scheme
Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
• Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit
page number page offset
p d
m -n n
• For given logical address space 2m and page size 2n

21. Paging Model of Logical and Physical Memory

22. Paging Hardware
• Each operating system has its own methods for storing page
tables.
• Some allocate a page table for each process.
• When the dispatcher is told to start a process, it must reload the user
registers and define the correct hardware page-table values from the
stored user page table.
• The hardware implementation of the page table can be
done in several ways.
In the simplest case
The page table is implemented as a set of
dedicated registers.

23. • Page-table base register (PTBR) points to the
page table.
Page-table Base Register (PTBR)
• The standard solution to this problem is to
use a special, small, fastlookup hardware
cache called a translation look-aside buffer
(TLB).
• The percentage of times that the page number of
interest is found in the TLB is called the hit ratio.

24. Protection
Memory protection in a paged environment is accomplished by protection bits
associated with each frame.
• One bit can define a page to be read–write or read-
only.
Valid–Invalid Bit
• One additional bit is generally attached
to each entry in the page table: a
valid–invalid bit.

25. Shared Pages
• An advantage of paging is the possibility of
sharing common code.
• This consideration is particularly important in a
time-sharing environment.
• If the text editor consists of 150 KB of code and 50 KB of data space,
we need 8,000 KB to support the 40 users.
• If the code is reentrant code (or pure code),

26. Sharing Of code in Paging environment