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Operating Systems 1 (9/12) - Memory Management Concepts
The document discusses memory management concepts in operating systems including: - Memory is a critical resource that must be managed by the operating system to allow multiple processes to efficiently share the physical memory. - The operating system implements virtual memory which maps process logical addresses to physical addresses to isolate processes. - A memory management unit (MMU) hardware performs this address translation transparently. - Memory is organized in a hierarchy from fast expensive cache/RAM to slower cheaper disk storage. - The operating system uses paging, swapping and memory partitioning to manage this hierarchy and allocate memory to processes.
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Operating Systems 1 (9/12) - Memory Management Concepts
- 1. Memory Management -Concepts Beuth Hochschule Summer Term 2014 ! Pictures (C) W. Stallings, if not stated otherwise
- 2. Operating Systems IPT / FF 14 Memory Management • Beside compute time, memory is the most important operating system resource • von Neumann model: Memory as linear set of bytes with constant access time • Memory utilization approaches • Without operating system, one control flow • Every loaded program must communicate with the hardware by itself • With operating system, one control flow • Memory used by operating system, device drivers and the program itself • With operating system and multi-tasking • Better processor utilization on locking I/O operations • Multiple programs use the same memory 2
- 3. Operating Systems IPT / FF 14 Memory Management - Address Space • CPU fetches instructions from memory according to the program counter value • Instructions may cause additional loading from and storing to memory locations • Address space: Set of unique location identifiers (addresses) • Memory address regions that are available to the program at run-time • All systems today work with a contiguous / linear address space per process • In a concurrent system, address spaces must be isolated from each other -> mapping of address spaces to physical memory • Mapping approach is predefined by the hardware / operating system combination • Not every mapping model works on all hardware • Most systems today implement a virtual address space per process 3
- 4. Operating Systems IPT / FF 14 Linear Address Space 4 (fromIBMdeveloperWorks) Lineare Adreßräume (2) Memory Address Space 1 Address Space 2 Address Space 3 Address Space 3 Address Space 1 Address Space 2
- 5. Operating Systems IPT / FF 14 Addressing Schemes • Physical / absolute address • Actual location of data in physical memory • If some data is available at address a, it is accessed at this location • Relative address • Location in relation to some known address • Logical address • Memory reference independent from current physical location of data • Access to data at physical location a is performed by using the logical address a‘ • It exists a mapping f with f(a') = a • f can be implemented in software or hardware -> MMU 5
- 6. Operating Systems IPT / FF 14 Logical Address Space 6 Logischer Adressbereich 000C0000 − 000C7FFF 000A0000 − 000BFFFF 000E0000 − 000EFFFF 000F0000 − 000FFFFF 00000000 − 0009FFFF 000C8000 − 000DFFFF 00100000 − 02FFFFFF FFFE0000 − FFFEFFFF FFFF0000 − FFFFFFFF 03000000 − FFFDFFFF physikalischer Adreßraumlogischer Adreßraum 00000000 − 02F9FFFF Lineare Adreßräume (2) Memory Address Space 1 Address Space 2 Address Space 3 Address Space 3 Address Space 1 Address Space 2
- 7. Operating Systems IPT / FF 14 Memory Management Unit (MMU) • Hardware device that maps logical to physical addresses • The MMU is part of the processor • Re-programming the MMU is a privileged operation, can only be performed in privileged (kernel) mode • The MMU typically implements one or more mapping approaches • The user program deals with logical addresses only • Never sees the real physical addresses • Transparent translation with each instruction executed 7
- 8. Operating Systems IPT / FF 148 Addressing Schemes Logical Address Space Core MMU Instruction fetch Logical address Physical Address Space Physical address Mapping information
- 9. Operating Systems IPT / FF 14 Memory Hierarchy • If operating system manages the memory, it must consider all levels of memory • Memory hierarchy • Differences in capacity, costs and access time • Bigger capacity for lower costs and speed • Principal of locality • Static RAM (SRAM) • Fast, expensive, keeps stored value once it is written • Used only for register files and caches • Dynamic RAM (DRAM) • Capacitor per Bit, demands re-fresh every 10-100ms 9 FusionDrive intro from Apple keynote 2012 Fast Expensive Small Slow Cheap Large non-volatile volatile
- 10. Operating Systems IPT / FF 14 Memory Hierarchy 10 http://tjliu.myweb.hinet.net/ • The operating system has to manage the memory hierarchy • Programs should have comparable performance on different memory architectures • In some systems, parts of the cache invalidation are a software task (e.g. TLB)
- 11. Operating Systems IPT / FF 14 Memory Hierarchy • Available main and secondary memory is a shared resource among all processes • Can be allocated and released by operating system and application • Programmers are not aware of other processes in the same system • Main memory is expensive, volatile and fast, good for short-term usage • Secondary memory is cheaper, typically not volatile and slower, good for long-term • Flow between levels in the memory hierarchy is necessary for performance • Traditionally solved by overlaying and swapping • Reoccurring task for software developers - delegation to operating system • In multiprogramming, this becomes a must 11
- 12. Operating Systems IPT / FF 14 Swapping • In a multiprogramming environment • Blocked (and ready) processes can be temporarily swapped out of main to secondary memory • Allows for execution of other processes • With physical addresses • Processes will be swapped in into same memory space that they occupied previously • With logical addresses • Processes can be swapped in at arbitrary physical addresses • Demands relocation support 12 Opera&ng) system) User) )space) Process) P1) Process) P2) Swap) out) Swap) in) Main)memory) Backing)store)
- 13. Operating Systems IPT / FF 14 Memory Management - Protection and Sharing • With relocation capabilities and concurrency, the operating system must implement protection mechanisms against accidental or intentional unwanted process interference • Protection mechanism must work at run-time for each memory reference • Program location in memory is unpredictable • Dynamic address calculation in program code is possible for attackers • Mechanism therefore must be supported by hardware • Software solution would need to screen all (!) memory referencing • Sharing • Allow controlled sharing of memory regions, if protection is satisfied • Both features can be implemented with a relocation mechanism 13
- 14. Operating Systems IPT / FF 14 Memory Management - Partitioning • With relocation and isolation, the operating system can manage memory partitions • Reserve memory partitions on request • Recycle unused / no longer used memory partitions, implicitly or explicitly • Swap out the content of temporarily unused memory partitions • Memory management must keep state per memory partition • Different partitioning approaches have different properties • Traditional approach was one partition per process 14 Lineare Adreßräume (2) Memory Address Space 1 Address Space 2 Address Space 3 Address Space 3 Address Space 1 Address Space 2
- 15. • Partitioning approachescan be evaluated by their • Fragmentation behavior, performance, overhead • Hypothetical example: Fixed partition size, bit mask for partition state • Small block size -> large bit mask -> small fragmentation Large block size -> small bit mask -> large fragmentation • External Fragmentation • Total memory space exists to satisfy a request, but it is not contiguous • Internal Fragmentation • Allocated memory may be slightly larger than requested memory • Size difference is memory internal to a partition, but not being used Operating Systems I PT / FF 14 Memory Management - Partitioning 15
- 16. Operating Systems IPT / FF 14 Memory Partitioning - Dynamic Partitioning • Variable length of partitions, as needed by new processes • Used in the IBM OS/MVT system • Leads to external fragmentation 16 Only P4 is ready - swap out takes place
- 17. Operating Systems IPT / FF 14 Memory Partitioning - Dynamic Partitioning • External fragmentation can be overcome by compaction • Operating system is shifting partitions so that free memory becomes one block • Time investment vs. performance gain • Demands relocation support • Placement algorithms for unequal fixed and dynamic partitioning • Best-fit: Chose the partition that is closest in size • First-fit: Pick first partition that is large enough • Next-fit: Start check from the last chosen partition and pick next match 17 Example: 16MB allocation
- 18. Operating Systems IPT / FF 14 Memory Partitioning - Placement • Best-fit: Use smallest free partition match • Sort free partitions by increasing size, choose first match • Leaves mostly unusable fragments, compaction must be done more frequently • Overhead for sorting and searching, tendency for small fragments at list start • Typically worst performer • Worst-fit: Use largest free partition match • Sort free partitions by decreasing size, choose first match • Leave fragments with large size to reduce internal fragmentation • Tendency for small fragments at list end and large fragments at list start • Results in small search overhead, but higher fragmentation; sorting overhead 18
- 19. Operating Systems IPT / FF 14 Memory Partitioning - Placement • First-fit: • Maintain list of free partitions ordered by addresses • Tendency for small fragments at list start and large fragments at list end • In comparison to best-fit, it can work much faster with less external fragmentation • Next-fit: • Tendency to fragment the large free block at the end of memory • Leads to more equal distribution of fragments 19
- 20. Operating Systems IPT / FF 14 Compaction • Combine adjacent free memory regions to a larger region • Removes external fragmentation • Can be performed ... • ... with each memory de-allocation • ... when the system in inactive • ... if an allocation request fails • ... if a process terminates • Compaction demands support for relocation 20 Kompaktifizierung (1) . . . muß spätestens ausgelöst werden, w Anforderung nicht mehr erfüllbar ist job 1 job 2 OS 0 300 500 600 2100 job 3 job 4 800 1200 job 1 job 2 OS 0 300 500 600 2100 1200 job 4 job 3 1000 job 1 job 4 job 3 job 2 OS 0 300 500 600 1000 1200 1500 2100 1900 job 1 job 4 job 2 OS 0 300 500 600 1500 2100 1900 job 3 600 Worte bewegt 400 Worte bewegtAusgangspunkt 200 Worte bewegt
- 21. Operating Systems IPT / FF 14 Compaction • Very resource-consuming activity, avoid whenever possible • Time for mandatory compaction can be delayed • Placement strategies and memory de-allocation approaches • Example: Linux • First part of the algorithm looks for movable regions from memory start • Second part of the algorithm looks for free regions from memory end back • Uses existing mechanisms for memory migration (NUMA systems) • Also very interesting research topic for heap management and garbage collection 21
- 22. Operating Systems IPT / FF 14 Memory Management - Segmentation • Each process has several data sections being mapped to its address space • Application program code (procedures, modules, classes) and library program code • Differences in purpose, developer, reliability and quality • Stack(s) • (X86) ESP register points to highest element in the stack, one per process • (X86) PUSH / POP assembler instructions • (X86) CALL leaves return address on the stack, RET returns to current address on the stack • Parameter hand-over in method calls, local variables • Heap(s) • Memory dynamically allocated and free‘d during runtime by the program code 22
- 23. Operating Systems IPT / FF 14 Process Data Sections 23 Interne Organisation Address Space Code Data Stack Data Code Data Data Code Code Data Code Code Code Heap Adreßräume in Unix-Deriva Expansion Area Code End of Data (break) Top of Stack Stack Start of Address Space End of Address Space Initialised Data BSS (zeroed) Unix BSS = „Block Started By Symbol“ -> non-initialized static and global variables (C) J. Nolte, BTU
- 24. • Segmentation: • Splitprocess address space into segments • Variable length up to a given maximum • Like dynamic partitioning, but • Partitions don‘t need to be contiguous - no internal fragmentation • External fragmentation is reduced with multiple partitions per process • Large segments can be used for process isolation (like in the partitioning idea) • Mid-size segments can be used for separating application code, libraries and stack • Small segments can be used for object and record management • Each logical memory address is a tuple of segment number and segment-relative address (offset) • Translated to base / limit values by the MMU Operating Systems I PT / FF 14 Partitioning by Segmentation 24
- 25. Operating Systems IPT / FF 14 Memory Protection - Bounds / Limit • Every process has different limit, either base/limit pair or bounds pair • Processor has only one valid configuration at a time • Operating system manages limits as part of the processor context per process 25 Schranken (4) unused user 2 user 1 base hardware prototype base base base operating system software prototypes limit limit limit limit (C) J. Nolte, BTU
- 26. Operating Systems IPT / FF 14 Segmentation Granularity 26 Grobe Segmentierung (3) Expansion Area Code Stack Initialised Data BSS (zeroed) Code Initialised Data BSS (zeroed) Stack Logical Physical base/limit base/limit base/limit • One base/limit pair per segment • Configuration of base/limit registers: • Implicitly through activities (code /data fetch) • Explicitly through the operating system • Segmentation on module level can help to implement shared memory • Code or data sharing • Shared libraries get their own segment, mapped to different processes • Also good for inter-process communication • Separated or combined utilization of a segment for code and data of program modules Moduln (1) Data Data Data Code Data Code Code Module 0 Module 2 Module 3 Module 1 Module 0..3 Module 0..3 Separated Combined Code Code Moduln (1) Data Data Data Code Data Code Code Module 0 Module 2 Module 3 Module 1 Module 0..3 Module 0..3 Separated Combined Code Code (C) J. Nolte, BTU
- 27. Operating Systems IPT / FF 14 Segmentation Granularity 27 Mittelgranulare Segmentierung (1) Code 0Module 0 Module 2 Module 1 Code 1 Code 2 Data 2 Data 0 Data 1 Data 1 Code 1 Data 0 Data 2 Code 2 logical physical base/limit base/limit base/limit base/limit base/limit base/limit Code 0 (C) J. Nolte, BTU
- 28. Operating Systems IPT / FF 14 Segment Tables • With multiple base/limit pairs per process, a segment table must be maintained • Table is in main memory, but must be evaluated by the MMU 28
- 29. Operating Systems IPT / FF 14 Memory Management - Paging • Segmentation / partitioning always have a fragmentation problem • Fixed-size partitions lead to internal fragmentation • Variable-sized partitions lead to external fragmentation • Solution: Paging • Partition memory into small equal fixed-size chunks - (page) frames • Partition process address space into chunks of the same size - pages • No external fragmentation, only small internal fragmentation in the last page • One page table per process • Maps each process page to a frame - entries for all pages needed • Used by processor MMU do translate logical to physical addresses 29
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- 31. Operating Systems IPT / FF 14 Memory Management - Paging 31
- 32. Operating Systems IPT / FF 14 Memory Management - Paging • Page frame size depends on processor • 512 Byte (DEC VAX, IBM AS/400), 4K or 4MB (Intel X86) • 4K (IBM 370, PowerPC), 4K up to 16MB (MIPS) • 4KB up to 4MB (UltraSPARC), 512x48Bit (Atlas) • Non-default size only possible with multi-level paging (later) • Each logical address is represented by a tuple (page number, offset) • Page number is an index into the page table • Page Table Entry (PTE) contains physical start address of the frame • Change of process -> change of logical address space -> change of active page table • Start of the active page table in physical memory is stored in a MMU register 32
- 33. Operating Systems IPT / FF 14 Page Table Sizes 33 Address Space Page Size Number of Pages Page Table Size per Process 2 2 2 2 2 2 2 2 2 2 2 256 GB 2 2 2 256 MB 2 2 2 16.7 PB 2 2 2 16 TB
- 34. Operating Systems IPT / FF 14 Address Translation • Adding a page frame (physical address range) to a logical address space • Add the frame number to a free position in the page table • Adding logical address space range to another logical address space • Compute frame number from page number • Add to target page table • Determining the physical address for a logical address • Determine page number, lookup in the page table for the frame start address • Add offset • Determining the logical address for a physical address • Determine page number from frame start address, add offset 34
- 35. • Mapping ofpages to frames can change constantly during run-time • Each memory access demands another one for the page table information • Necessary to cache page table lookup results for performance optimization • Translation Lookaside Buffer (TLB) • Page number + complete PTE per entry • Hardware can check TLB entries in parallel for page number match Operating Systems I PT / FF 14 Paging - Page Tables 35
- 36. Operating Systems IPT / FF 14 Protection and Sharing • Logical addressing with paging allows sharing of address space regions • Shared code - multiple program instances, libraries, operating system code • Shared data - concurrent applications, inter-process communication • Protection based on paging mechanisms • Individual rights per page maintained in the page table (read, write, execute) • On violation, the MMU triggers a processor exception (trap) • Address space often has unused holes (e.g. between stack and heap) • If neither process nor operating system allocated this region, it is marked as invalid in the page table • On access, the processor traps 36
- 37. Operating Systems IPT / FF 14 Th NX Bit • The Never eXecute bit marks a page as not executable • Very good protection against stack or heap-based overflow attacks • Well-known for decades in non-X86 processor architectures • AMD decided to add it to the AMD64 instruction set, Intel adopted it since P4 • Demands operating system support for new page table structure • Support in all recent Windows and Linux versions 37
- 38. Operating Systems IPT / FF 14 X86 Page Table Entry (PTE) 38 •! M01+%$0J6+9%0.+%0..0/%-I%M01+%:0J6+%K"$.#+9%SM:K9T% •! 406#8%M:K9%>0F+%$L-%g+689)%% –! M01+%U.0,+%?5,J+.%SMU?T% –! U6019%8+9@.#J#"1%9$0$+%0"8%=.-$+@;-"%-I%$>+%=01+% 29 Page frame number VU P Cw Gi L D A Cd Wt O W Res (writable on MP Systems) Res Res Global Res (large page if PDE) Dirty Accessed Cache disabled Write through Owner Write (writable on MP Systems) valid Reserved bits are used only when PTE is not valid 31 12 0 M:K%'$0$59%0"8%M.-$+@;-"%Z#$9%% SR"$+6%P^_%-"6/T% 30
- 39. Operating Systems IPT / FF 14 Virtual Memory • Common concepts in segmentation and paging • All memory references are translated to physical addresses at run-time • Address spaces are transparently broken up into non-contiguous pieces • Combination allows to not have all parts of an address space in main memory • Commonly described as virtual memory concept • Size of virtual memory is limited by address space size and secondary storage • More processes can be maintained in main memory • Process address space occupation may exceed the available physical memory • First reported for Atlas computer (1962) 39
- 40. Operating Systems IPT / FF 14 Virtual Memory with Paging • Frames can be dynamically mapped into address spaces • Example: Dynamic heap extension, creation of shared regions • Demands page table modification for the address space owner • Frames can be mapped into multiple different logical address spaces • Page-in / page-out: Taking a frame out of the logical address space • Mark the address space region as invalid in the page table • Move the (page) data to somewhere else, release the frame • On access, the trap handler of the operating system is called • Triggers the page swap-in to allow the access (same frame ?) • This is often simply called swapping, even though it is page swapping 40
- 41. Operating Systems IPT / FF 14 Page Swapping 41 /B:
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