The document discusses memory management techniques. It begins by explaining logical vs physical address spaces and the need for memory protection when multiple processes reside in memory. It then covers various memory allocation schemes like contiguous allocation, paging, and segmentation. Paging divides memory into fixed-sized frames and logical memory into pages. Address translation uses a page table to map logical to physical addresses. Hierarchical paging is introduced to reduce the size of large page tables.
Main memory management techniques include paging and segmentation. Paging maps logical addresses to physical frames through a page table. It allows non-contiguous allocation but causes internal fragmentation. Segmentation maps a logical address to physical memory using a segment table containing base addresses and limits. It matches the user's logical view of memory and allows sharing through segments. Both techniques use memory protection rings and translation to virtualize the physical address space.
This document describes various memory management techniques used in computer systems, including swapping, contiguous allocation, paging, segmentation, and the memory architecture of the Intel Pentium CPU. It discusses how paging uses a page table to map logical addresses to physical frames through an address translation process. Segmentation divides memory into variable-length segments and uses segment tables. The Pentium supports both pure segmentation and a hybrid of segmentation and paging to translate logical addresses to physical memory locations.
The document discusses several memory management techniques including paging, segmentation, and swapping. Paging divides memory into fixed-size blocks called frames and logical memory into blocks called pages. It uses a page table to map logical to physical addresses. Segmentation divides programs into logical segments like code and data and allows segments to be placed anywhere in memory. Swapping temporarily moves processes out of memory to disk to allow other processes to run.
This document discusses different memory management techniques:
- It describes swapping, where a process is temporarily moved out of memory to disk to make room for other processes. Paging and segmentation are also covered, where memory is divided into pages/segments and logical addresses are translated to physical addresses.
- Memory management aims to allocate processes efficiently in memory while avoiding issues like fragmentation. Techniques like contiguous allocation, paging, and segmentation map logical addresses to physical frames and protect memory access.
Memory management is the act of managing computer memory. The essential requirement of memory management is to provide ways to dynamically allocate portions of memory to programs at their request, and free it for reuse when no longer needed. This is critical to any advanced computer system where more than a single process might be underway at any time
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
This document discusses different memory management techniques including:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation. Paging and segmentation address this by allowing non-contiguous allocation.
2. Paging maps logical addresses to physical frames through a page table. It supports non-contiguous allocation but has translation overhead that is reduced using translation lookaside buffers.
3. Segmentation divides memory into logical segments and uses a segment table to map logical to physical addresses. It matches the user's view of memory but external fragmentation remained an issue until combined with paging.
Main memory management techniques include paging and segmentation. Paging maps logical addresses to physical frames through a page table. It allows non-contiguous allocation but causes internal fragmentation. Segmentation maps a logical address to physical memory using a segment table containing base addresses and limits. It matches the user's logical view of memory and allows sharing through segments. Both techniques use memory protection rings and translation to virtualize the physical address space.
This document describes various memory management techniques used in computer systems, including swapping, contiguous allocation, paging, segmentation, and the memory architecture of the Intel Pentium CPU. It discusses how paging uses a page table to map logical addresses to physical frames through an address translation process. Segmentation divides memory into variable-length segments and uses segment tables. The Pentium supports both pure segmentation and a hybrid of segmentation and paging to translate logical addresses to physical memory locations.
The document discusses several memory management techniques including paging, segmentation, and swapping. Paging divides memory into fixed-size blocks called frames and logical memory into blocks called pages. It uses a page table to map logical to physical addresses. Segmentation divides programs into logical segments like code and data and allows segments to be placed anywhere in memory. Swapping temporarily moves processes out of memory to disk to allow other processes to run.
This document discusses different memory management techniques:
- It describes swapping, where a process is temporarily moved out of memory to disk to make room for other processes. Paging and segmentation are also covered, where memory is divided into pages/segments and logical addresses are translated to physical addresses.
- Memory management aims to allocate processes efficiently in memory while avoiding issues like fragmentation. Techniques like contiguous allocation, paging, and segmentation map logical addresses to physical frames and protect memory access.
Memory management is the act of managing computer memory. The essential requirement of memory management is to provide ways to dynamically allocate portions of memory to programs at their request, and free it for reuse when no longer needed. This is critical to any advanced computer system where more than a single process might be underway at any time
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
This document discusses different memory management techniques including:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation. Paging and segmentation address this by allowing non-contiguous allocation.
2. Paging maps logical addresses to physical frames through a page table. It supports non-contiguous allocation but has translation overhead that is reduced using translation lookaside buffers.
3. Segmentation divides memory into logical segments and uses a segment table to map logical to physical addresses. It matches the user's view of memory but external fragmentation remained an issue until combined with paging.
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
This document discusses different techniques for organizing main memory, including contiguous allocation, segmentation, and paging. Contiguous allocation allocates each process to a single contiguous block of memory, limiting multiprogramming. Segmentation and paging allow non-contiguous allocation through memory mappings. Paging maps virtual to physical addresses using a page table, with pages typically being 4KB each. Context switch time can increase significantly if processes need to be swapped in from disk. Fragmentation also limits available memory as free spaces become scattered and non-contiguous.
The document discusses different memory management techniques used in operating systems:
1. Programs go through several steps before execution - compilation, loading, and execution where address binding can occur.
2. Memory management schemes separate logical and physical addresses using techniques like paging and segmentation to map virtual to physical addresses.
3. Swapping allows processes to be temporarily moved out of memory to disk to improve memory utilization at the cost of performance.
The document discusses different memory management techniques used in operating systems. It begins with an overview of processes entering memory from an input queue. It then covers binding of instructions and data to memory at compile time, load time, or execution time. Key concepts discussed include logical vs physical addresses, the memory management unit (MMU), dynamic loading and linking, overlays, swapping, contiguous allocation, paging using page tables and frames, and fragmentation. Hierarchical paging, hashed page tables, and inverted page tables are also summarized.
This document discusses storage management techniques used in operating systems, including contiguous memory allocation, segmentation, paging, and virtual memory. It provides details on how these techniques work, such as how segmentation divides memory into variable-sized segments and uses segment tables, and how paging divides memory into fixed-sized pages and page tables to translate logical to physical addresses. It also covers concepts like internal and external fragmentation, demand paging, and page replacement algorithms.
This document discusses different memory management strategies used in operating systems. It describes basic hardware components like main memory, registers, and cache. It then covers address binding techniques, logical vs physical address spaces, and dynamic loading and linking of processes. The rest of the document discusses paging as a memory management strategy, including hardware support through page tables, protection using valid-invalid bits, and sharing of pages between processes.
Main memory is used to store programs and data for the CPU to access directly. Paging is a memory management technique that divides main memory into fixed-sized blocks called frames and divides logical memory into same-sized blocks called pages. The page table maps logical page numbers to physical frame numbers, with translation lookaside buffers caching these mappings to improve performance. Protection bits in page table entries enforce access permissions on individual pages.
Main Memory Management in Operating SystemRashmi Bhat
Main Memory Management techniques include paging and segmentation. Paging divides both logical and physical memory into fixed-size blocks called pages and frames respectively. The CPU address is divided into a page number and page offset. The page number is used to index a page table to map the logical page to a physical frame. A Translation Lookaside Buffer (TLB) is used to cache recent page table entries to speed up virtual to physical address translation and reduce memory accesses on TLB hits.
This document provides an overview of memory management techniques, including paging and segmentation. It discusses how programs are loaded into memory and placed within a process. It describes the memory management unit (MMU) that maps virtual to physical addresses using techniques like paging, segmentation, and swapping. Paging divides memory into fixed-size pages and uses a page table to translate logical addresses to physical frame numbers. Segmentation divides a program into logical segments and uses segment tables to map two-dimensional logical addresses to physical addresses.
This document discusses memory management techniques in operating systems. It covers topics such as binding instructions and data to memory at different stages, logical vs physical address spaces, memory management units that map virtual to physical addresses, dynamic loading and linking of code, using overlays to only hold needed instructions and data in memory, swapping processes temporarily out of memory to secondary storage, and contiguous allocation of memory to processes.
Main memory is where programs are loaded to run on the CPU. There are several techniques for managing memory allocation and binding programs to addresses in memory, including compile-time, load-time, and execution-time binding. Memory management is needed to map logical addresses used by programs to physical addresses in memory. Paging is a memory management technique that divides memory into pages to allow non-contiguous allocation and reduce fragmentation.
This document discusses memory management techniques in computer systems including segmentation, paging, and virtual memory. It covers:
1. Segmentation divides memory into logical segments like code, data, stack, and heap and uses a segment table with base and limit registers to map logical to physical addresses.
2. Paging allows non-contiguous mapping of logical to physical addresses to avoid external fragmentation. It uses a page table and frame table to map virtual to physical pages.
3. Virtual memory uses both segmentation and paging to provide each process its own logical address space. The memory management unit (MMU) handles address translation from virtual to physical addresses.
This document contains slides related to operating system concepts for a second year Bachelor of Technology course. It includes topics like swapping, contiguous memory allocation, paging, segmentation, page replacement algorithms, and case studies of UNIX, Linux and Windows operating systems. The document provides an index of lecture topics and corresponding PowerPoint slide numbers.
Human: Thank you for the summary. Can you summarize the following document in 3 sentences or less?
[DOCUMENT]
Operating systems concepts are important for computer science students to understand. These concepts include processes, memory management, file systems, and more. This course will cover these important OS topics through lectures and readings.
This document contains slides from a lecture on operating system concepts including swapping, contiguous memory allocation, paging, segmentation, and page replacement. It discusses key topics such as logical vs physical addresses, page tables, translation lookaside buffers, demand paging, and page faults. The document includes 10 slides with diagrams and explanations of these operating system memory management techniques.
The document discusses memory management and file systems. It covers topics like paging, segmentation, contiguous and non-contiguous allocation, and disk scheduling algorithms. Paging divides memory into fixed-sized blocks called frames and logical memory into pages. It uses a page table to translate logical addresses to physical frame addresses. Swapping allows processes to be temporarily moved to disk to free up memory frames. Contiguous allocation allocates each process to a single block of contiguous memory.
This document discusses memory organization and virtual memory. It describes paging and segmentation as methods for virtual memory address translation. Paging divides memory and processes into equal sized pages, while segmentation divides processes into variable sized segments. Both methods use data structures like page tables to map logical addresses to physical addresses. Caching is also discussed as a way to improve memory performance by storing frequently accessed data in a small, fast memory near the CPU.
This document discusses memory management in operating systems. It covers topics like how memory management keeps track of allocated and free memory, provides protection using base and limit registers, and different address binding schemes. It also discusses dynamic loading, dynamic linking, logical versus physical addresses, swapping, memory allocation techniques like single allocation and multiple partitions, and issues like fragmentation. Paging and segmentation techniques for managing memory are also summarized.
The document discusses computer memory management and caching. It covers topics like memory partitioning, paging, segmentation, virtual memory, and cache memory principles. Memory can be partitioned into fixed or variable sized blocks to allocate to processes. Paging and segmentation improve memory usage by allowing processes to be non-contiguous in memory. Virtual memory uses demand paging to treat memory as larger than physical RAM by swapping pages to disk as needed. Cache memory holds frequently used data from main memory to improve access speed.
The document provides an overview of classes and objects in Java. It discusses container classes versus definition classes, and gives examples of the Math and Turtle classes. It explains key concepts like abstraction, encapsulation, and the relationship between classes and objects. Specific examples like the Clock and BankAccount classes are used to illustrate concepts like instance variables, constructors, methods, visibility modifiers, and API documentation.
1. The document discusses deterministic finite automata (DFAs) and nondeterministic finite automata (NFAs). DFAs have a single transition function, while NFAs have a transition function that can map a state-symbol pair to multiple possible next states.
2. Examples are given of DFAs and NFAs that accept certain languages over various alphabets. The DFA examples use transition diagrams to represent the transition functions, while the NFA examples explicitly define the transition functions.
3. Key properties of DFAs and NFAs are summarized, including their definitions as 5-tuples and how languages are accepted by looking for paths from the starting to a final state.
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
This document discusses different techniques for organizing main memory, including contiguous allocation, segmentation, and paging. Contiguous allocation allocates each process to a single contiguous block of memory, limiting multiprogramming. Segmentation and paging allow non-contiguous allocation through memory mappings. Paging maps virtual to physical addresses using a page table, with pages typically being 4KB each. Context switch time can increase significantly if processes need to be swapped in from disk. Fragmentation also limits available memory as free spaces become scattered and non-contiguous.
The document discusses different memory management techniques used in operating systems:
1. Programs go through several steps before execution - compilation, loading, and execution where address binding can occur.
2. Memory management schemes separate logical and physical addresses using techniques like paging and segmentation to map virtual to physical addresses.
3. Swapping allows processes to be temporarily moved out of memory to disk to improve memory utilization at the cost of performance.
The document discusses different memory management techniques used in operating systems. It begins with an overview of processes entering memory from an input queue. It then covers binding of instructions and data to memory at compile time, load time, or execution time. Key concepts discussed include logical vs physical addresses, the memory management unit (MMU), dynamic loading and linking, overlays, swapping, contiguous allocation, paging using page tables and frames, and fragmentation. Hierarchical paging, hashed page tables, and inverted page tables are also summarized.
This document discusses storage management techniques used in operating systems, including contiguous memory allocation, segmentation, paging, and virtual memory. It provides details on how these techniques work, such as how segmentation divides memory into variable-sized segments and uses segment tables, and how paging divides memory into fixed-sized pages and page tables to translate logical to physical addresses. It also covers concepts like internal and external fragmentation, demand paging, and page replacement algorithms.
This document discusses different memory management strategies used in operating systems. It describes basic hardware components like main memory, registers, and cache. It then covers address binding techniques, logical vs physical address spaces, and dynamic loading and linking of processes. The rest of the document discusses paging as a memory management strategy, including hardware support through page tables, protection using valid-invalid bits, and sharing of pages between processes.
Main memory is used to store programs and data for the CPU to access directly. Paging is a memory management technique that divides main memory into fixed-sized blocks called frames and divides logical memory into same-sized blocks called pages. The page table maps logical page numbers to physical frame numbers, with translation lookaside buffers caching these mappings to improve performance. Protection bits in page table entries enforce access permissions on individual pages.
Main Memory Management in Operating SystemRashmi Bhat
Main Memory Management techniques include paging and segmentation. Paging divides both logical and physical memory into fixed-size blocks called pages and frames respectively. The CPU address is divided into a page number and page offset. The page number is used to index a page table to map the logical page to a physical frame. A Translation Lookaside Buffer (TLB) is used to cache recent page table entries to speed up virtual to physical address translation and reduce memory accesses on TLB hits.
This document provides an overview of memory management techniques, including paging and segmentation. It discusses how programs are loaded into memory and placed within a process. It describes the memory management unit (MMU) that maps virtual to physical addresses using techniques like paging, segmentation, and swapping. Paging divides memory into fixed-size pages and uses a page table to translate logical addresses to physical frame numbers. Segmentation divides a program into logical segments and uses segment tables to map two-dimensional logical addresses to physical addresses.
This document discusses memory management techniques in operating systems. It covers topics such as binding instructions and data to memory at different stages, logical vs physical address spaces, memory management units that map virtual to physical addresses, dynamic loading and linking of code, using overlays to only hold needed instructions and data in memory, swapping processes temporarily out of memory to secondary storage, and contiguous allocation of memory to processes.
Main memory is where programs are loaded to run on the CPU. There are several techniques for managing memory allocation and binding programs to addresses in memory, including compile-time, load-time, and execution-time binding. Memory management is needed to map logical addresses used by programs to physical addresses in memory. Paging is a memory management technique that divides memory into pages to allow non-contiguous allocation and reduce fragmentation.
This document discusses memory management techniques in computer systems including segmentation, paging, and virtual memory. It covers:
1. Segmentation divides memory into logical segments like code, data, stack, and heap and uses a segment table with base and limit registers to map logical to physical addresses.
2. Paging allows non-contiguous mapping of logical to physical addresses to avoid external fragmentation. It uses a page table and frame table to map virtual to physical pages.
3. Virtual memory uses both segmentation and paging to provide each process its own logical address space. The memory management unit (MMU) handles address translation from virtual to physical addresses.
This document contains slides related to operating system concepts for a second year Bachelor of Technology course. It includes topics like swapping, contiguous memory allocation, paging, segmentation, page replacement algorithms, and case studies of UNIX, Linux and Windows operating systems. The document provides an index of lecture topics and corresponding PowerPoint slide numbers.
Human: Thank you for the summary. Can you summarize the following document in 3 sentences or less?
[DOCUMENT]
Operating systems concepts are important for computer science students to understand. These concepts include processes, memory management, file systems, and more. This course will cover these important OS topics through lectures and readings.
This document contains slides from a lecture on operating system concepts including swapping, contiguous memory allocation, paging, segmentation, and page replacement. It discusses key topics such as logical vs physical addresses, page tables, translation lookaside buffers, demand paging, and page faults. The document includes 10 slides with diagrams and explanations of these operating system memory management techniques.
The document discusses memory management and file systems. It covers topics like paging, segmentation, contiguous and non-contiguous allocation, and disk scheduling algorithms. Paging divides memory into fixed-sized blocks called frames and logical memory into pages. It uses a page table to translate logical addresses to physical frame addresses. Swapping allows processes to be temporarily moved to disk to free up memory frames. Contiguous allocation allocates each process to a single block of contiguous memory.
This document discusses memory organization and virtual memory. It describes paging and segmentation as methods for virtual memory address translation. Paging divides memory and processes into equal sized pages, while segmentation divides processes into variable sized segments. Both methods use data structures like page tables to map logical addresses to physical addresses. Caching is also discussed as a way to improve memory performance by storing frequently accessed data in a small, fast memory near the CPU.
This document discusses memory management in operating systems. It covers topics like how memory management keeps track of allocated and free memory, provides protection using base and limit registers, and different address binding schemes. It also discusses dynamic loading, dynamic linking, logical versus physical addresses, swapping, memory allocation techniques like single allocation and multiple partitions, and issues like fragmentation. Paging and segmentation techniques for managing memory are also summarized.
The document discusses computer memory management and caching. It covers topics like memory partitioning, paging, segmentation, virtual memory, and cache memory principles. Memory can be partitioned into fixed or variable sized blocks to allocate to processes. Paging and segmentation improve memory usage by allowing processes to be non-contiguous in memory. Virtual memory uses demand paging to treat memory as larger than physical RAM by swapping pages to disk as needed. Cache memory holds frequently used data from main memory to improve access speed.
The document provides an overview of classes and objects in Java. It discusses container classes versus definition classes, and gives examples of the Math and Turtle classes. It explains key concepts like abstraction, encapsulation, and the relationship between classes and objects. Specific examples like the Clock and BankAccount classes are used to illustrate concepts like instance variables, constructors, methods, visibility modifiers, and API documentation.
1. The document discusses deterministic finite automata (DFAs) and nondeterministic finite automata (NFAs). DFAs have a single transition function, while NFAs have a transition function that can map a state-symbol pair to multiple possible next states.
2. Examples are given of DFAs and NFAs that accept certain languages over various alphabets. The DFA examples use transition diagrams to represent the transition functions, while the NFA examples explicitly define the transition functions.
3. Key properties of DFAs and NFAs are summarized, including their definitions as 5-tuples and how languages are accepted by looking for paths from the starting to a final state.
This document discusses probabilistic models for classification tasks. It describes generative models that model the joint probability of classes and features to calculate class posterior probabilities using Bayes' rule. Generative models make assumptions like conditional independence of features. Discriminative models directly model the posterior probability of classes given features and make fewer assumptions. Maximum likelihood estimation techniques are discussed for estimating the parameters of generative models like naive Bayes and logistic regression. The document also covers decision theory and different loss functions used for classification.
The document discusses greedy algorithms and their use for optimization problems. It provides examples of using greedy approaches to solve scheduling and knapsack problems. Specifically, it describes how a greedy algorithm works by making locally optimal choices at each step in hopes of reaching a globally optimal solution. While greedy algorithms do not always find the true optimal, they often provide good approximations. The document also proves that certain greedy strategies, such as always selecting the item with the highest value to weight ratio for the knapsack problem, will find the true optimal solution.
The document discusses memory management techniques used in operating systems, including virtual memory. It explains that virtual memory allows the operating system to allocate more memory to processes than is physically available by swapping unused memory pages to disk as needed. This is done using page tables that map virtual addresses to physical addresses, with pages as the unit of mapping. The memory management unit in the CPU handles translating virtual addresses to physical addresses transparently to processes.
This document summarizes chapter 5 from the textbook "Operating System Concepts - 9th Edition" which covers process synchronization. It introduces the critical section problem where multiple processes need orderly access to shared resources. Peterson's algorithm and solutions using locks, mutexes, and semaphores are presented. These synchronization methods use atomic instructions to safely coordinate access to critical sections and ensure processes follow rules of mutual exclusion, progress, and bounded waiting.
This document summarizes a lecture on standard combinational modules. It discusses representation of numbers using 2's complement and 1's complement, and types of adders including half adders, full adders, ripple-carry adders, carry-lookahead adders, and prefix adders. It provides examples of addition and subtraction using each representation. It also briefly discusses comparators for equality and less than operations.
This document provides an overview of memory management techniques in operating systems, including swapping, contiguous allocation, segmentation, and paging. It discusses how logical and physical addresses are mapped and protected through the use of base and limit registers, and how context switch time can be impacted by swapping processes in and out of memory. Modern operating systems commonly use paging instead of swapping to manage memory.
The document discusses control unit design, including hardwired and microprogrammed approaches. It provides terminology for microprogrammed control, describing components like the control memory, sequencer, and microinstructions. It then covers the functions of the control unit like fetch cycles, instruction interpretation and execution. Details are given on instruction control transfer, program control transfer, and implementation methods for hardwired control logic like sequence counters and state tables. Microprogrammed control is more flexible but hardwired control can provide better performance.
An arithmetic logic unit (ALU) performs arithmetic and logic operations and is a fundamental building block of the central processing unit (CPU) of a computer. Even the simplest microprocessors contain an ALU for purposes such as maintaining timers. The ALU is a combinational logic circuit that can be implemented as a simple ALU that performs basic operations or a more complex ALU with additional functionality like zero and overflow outputs. The document discusses designing and testing an ALU, including examples of simple and enhanced ALU implementations.
This document discusses various topics related to air pollution and the atmosphere. It begins by defining greenhouse gases and their impact on global climate change, including consequences for sea levels, agriculture, and marine food. Next, it covers the structure of the atmosphere and composition of the troposphere. The document then discusses the greenhouse effect in more detail, and effects of global warming such as rising temperatures, sea levels, and impacts on agriculture and marine food. It concludes with methods for controlling global warming, such as reducing waste and emissions and using energy-efficient products.
The document discusses memory hierarchy and virtual memory. It summarizes:
- Memory hierarchy organizes memory into different levels from fastest and most expensive (cache/registers) to slowest and least expensive (magnetic disk). This is done to obtain the highest possible access speed while minimizing total cost.
- Virtual memory allows the memory address space to be larger than actual physical memory using memory mapping and paging. It gives the illusion of a larger memory through mapping of virtual addresses to physical addresses.
1. Computer memory is organized in a hierarchy from fast but small cache memory to slower but larger archival storage. Cache memory uses the locality principle to improve performance by keeping frequently used data close to the CPU.
2. There are different techniques for mapping memory addresses to cache locations including direct mapping, set associative mapping, and fully associative mapping. Direct mapping uses the low-order address bits to determine the cache slot while set associative mapping distributes blocks across multiple slots in a set.
3. Cache performance is measured by hit ratio, miss ratio, and mean access time. With a high hit ratio, the mean access time approaches the fast cache access time. Cache maintenance policies like write-back and
How to Setup Warehouse & Location in Odoo 17 InventoryCeline George
In this slide, we'll explore how to set up warehouses and locations in Odoo 17 Inventory. This will help us manage our stock effectively, track inventory levels, and streamline warehouse operations.
A review of the growth of the Israel Genealogy Research Association Database Collection for the last 12 months. Our collection is now passed the 3 million mark and still growing. See which archives have contributed the most. See the different types of records we have, and which years have had records added. You can also see what we have for the future.
বাংলাদেশের অর্থনৈতিক সমীক্ষা ২০২৪ [Bangladesh Economic Review 2024 Bangla.pdf] কম্পিউটার , ট্যাব ও স্মার্ট ফোন ভার্সন সহ সম্পূর্ণ বাংলা ই-বুক বা pdf বই " সুচিপত্র ...বুকমার্ক মেনু 🔖 ও হাইপার লিংক মেনু 📝👆 যুক্ত ..
আমাদের সবার জন্য খুব খুব গুরুত্বপূর্ণ একটি বই ..বিসিএস, ব্যাংক, ইউনিভার্সিটি ভর্তি ও যে কোন প্রতিযোগিতা মূলক পরীক্ষার জন্য এর খুব ইম্পরট্যান্ট একটি বিষয় ...তাছাড়া বাংলাদেশের সাম্প্রতিক যে কোন ডাটা বা তথ্য এই বইতে পাবেন ...
তাই একজন নাগরিক হিসাবে এই তথ্য গুলো আপনার জানা প্রয়োজন ...।
বিসিএস ও ব্যাংক এর লিখিত পরীক্ষা ...+এছাড়া মাধ্যমিক ও উচ্চমাধ্যমিকের স্টুডেন্টদের জন্য অনেক কাজে আসবে ...
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UPRAHUL
This Dissertation explores the particular circumstances of Mirzapur, a region located in the
core of India. Mirzapur, with its varied terrains and abundant biodiversity, offers an optimal
environment for investigating the changes in vegetation cover dynamics. Our study utilizes
advanced technologies such as GIS (Geographic Information Systems) and Remote sensing to
analyze the transformations that have taken place over the course of a decade.
The complex relationship between human activities and the environment has been the focus
of extensive research and worry. As the global community grapples with swift urbanization,
population expansion, and economic progress, the effects on natural ecosystems are becoming
more evident. A crucial element of this impact is the alteration of vegetation cover, which plays a
significant role in maintaining the ecological equilibrium of our planet.Land serves as the foundation for all human activities and provides the necessary materials for
these activities. As the most crucial natural resource, its utilization by humans results in different
'Land uses,' which are determined by both human activities and the physical characteristics of the
land.
The utilization of land is impacted by human needs and environmental factors. In countries
like India, rapid population growth and the emphasis on extensive resource exploitation can lead
to significant land degradation, adversely affecting the region's land cover.
Therefore, human intervention has significantly influenced land use patterns over many
centuries, evolving its structure over time and space. In the present era, these changes have
accelerated due to factors such as agriculture and urbanization. Information regarding land use and
cover is essential for various planning and management tasks related to the Earth's surface,
providing crucial environmental data for scientific, resource management, policy purposes, and
diverse human activities.
Accurate understanding of land use and cover is imperative for the development planning
of any area. Consequently, a wide range of professionals, including earth system scientists, land
and water managers, and urban planners, are interested in obtaining data on land use and cover
changes, conversion trends, and other related patterns. The spatial dimensions of land use and
cover support policymakers and scientists in making well-informed decisions, as alterations in
these patterns indicate shifts in economic and social conditions. Monitoring such changes with the
help of Advanced technologies like Remote Sensing and Geographic Information Systems is
crucial for coordinated efforts across different administrative levels. Advanced technologies like
Remote Sensing and Geographic Information Systems
9
Changes in vegetation cover refer to variations in the distribution, composition, and overall
structure of plant communities across different temporal and spatial scales. These changes can
occur natural.
This slide is special for master students (MIBS & MIFB) in UUM. Also useful for readers who are interested in the topic of contemporary Islamic banking.
How to Manage Your Lost Opportunities in Odoo 17 CRMCeline George
Odoo 17 CRM allows us to track why we lose sales opportunities with "Lost Reasons." This helps analyze our sales process and identify areas for improvement. Here's how to configure lost reasons in Odoo 17 CRM
How to Add Chatter in the odoo 17 ERP ModuleCeline George
In Odoo, the chatter is like a chat tool that helps you work together on records. You can leave notes and track things, making it easier to talk with your team and partners. Inside chatter, all communication history, activity, and changes will be displayed.
Executive Directors Chat Leveraging AI for Diversity, Equity, and InclusionTechSoup
Let’s explore the intersection of technology and equity in the final session of our DEI series. Discover how AI tools, like ChatGPT, can be used to support and enhance your nonprofit's DEI initiatives. Participants will gain insights into practical AI applications and get tips for leveraging technology to advance their DEI goals.
This presentation includes basic of PCOS their pathology and treatment and also Ayurveda correlation of PCOS and Ayurvedic line of treatment mentioned in classics.
2. Memory management
We have seen how CPU can be shared by a set of processes
Improve system performance
Process management
Need to keep several process in memory
Share memory
Learn various techniques to manage memory
Hardware dependent
3. Memory management
What are we going to learn?
Basic Memory Management: logical vs. physical address space, protection,
contiguous memory allocation, paging, segmentation, segmentation with
paging.
Virtual Memory: background, demand paging, performance, page
replacement, page replacement algorithms (FCFS, LRU), allocation of frames,
thrashing.
4. Background
Program must be brought (from disk) into memory
Fetch-decode-execute cycle
Memory unit only sees a stream of addresses + read requests, or address
+ data and write requests
Sequence of memory addresses generated by running program
CPU
5. Logical vs. Physical Address Space
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory unit
Logical address space is the set of all logical addresses generated by a
program
Physical address space is the set of all physical addresses generated by
a program
CPU
6. Background
Protection of memory required to ensure correct operation
Multiple processes resides in memory
1. Protect OS
2. Protect user processes
7. Base and Limit Registers
A pair of base and limit registers define the logical address space
8. Hardware Address Protection with Base and Limit
Registers
• OS loads the base & limit reg.
• Privileged instruction
9. Address Binding
Process resides in main memory
Associate each data element with memory address
Further, addresses represented in different ways at different stages of a program’s
life
Source code addresses usually symbolic
Compiled code addresses bind to relocatable addresses
i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
i.e. 74014
11. Binding of Instructions and Data to
Memory
Address binding of instructions and data to memory addresses can happen at
three different stages
Compile time: If memory location known a priori, absolute code can be generated;
must recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not known at
compile time
Execution time: If the process can be moved during its execution from one memory
segment to another
Binding delayed until run time
Need hardware support for address maps (e.g., base and limit registers)
12. Logical vs. Physical Address Space
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and load-
time address-binding schemes;
logical (virtual) and physical addresses differ in execution-time address-
binding scheme
Logical address space is the set of all logical addresses generated by a
program
Physical address space is the set of all physical addresses generated by
a program
CPU
13. Memory-Management Unit (MMU)
Hardware device that at run time maps virtual to physical address
Many methods possible
To start, consider simple scheme where the value in the relocation register is
added to every address generated by a user process at the time it is sent to
memory
relocation register
MS-DOS on Intel 80x86 used 4 relocation registers
The user program deals with logical addresses (0 to max); it never sees the
real physical addresses (R to R+max)
Say the logical address 25
Execution-time binding occurs when reference is made to location in memory
Logical address bound to physical addresses
16. Contiguous Allocation
Main memory usually divided into two partitions:
Resident operating system, usually held in low memory
User processes then held in high memory
Each process contained in single contiguous section of memory
17. Contiguous Allocation (Cont.)
Multiple-partition allocation
Divide memory into several Fixed size partition
Each partition stores one process
Degree of multiprogramming limited by number of partitions
If a partition is free, load process from job queue
MFT (IBM OS/360)
18. Contiguous Allocation (Cont.)
Multiple-partition allocation
Variable partition scheme
Hole – block of available memory; holes of various size are scattered
throughout memory
Keeps a table of free memory
When a process arrives, it is allocated memory from a hole large enough to
accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS
process 5
process 8
process 2
OS
process 5
process 2
OS
process 5
process 2
OS
process 5
process 9
process 2
process 9
process 10
OS
Hole
19. Dynamic Storage-Allocation Problem
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must search entire list,
unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
How to satisfy a request of size n from a list of free holes?
Dynamic storage allocation problem
20. Hardware Support for Relocation
and Limit Registers
• Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
• Relocation register contains value of smallest physical address
• Limit register contains range of logical addresses – each logical address must
be less than the limit register
• Context switch
• MMU maps logical address dynamically
21. Fragmentation
Processes loaded and removed from memory
Memory is broken into little pieces
External Fragmentation – total memory space exists to satisfy a request, but it
is not contiguous
First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to
fragmentation
1/3 may be unusable -> 50-percent rule
22. Fragmentation (Cont.)
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together in one large block
Compaction is possible only if relocation is dynamic, and is done at execution time
Change relocation reg.
Cost
Internal Fragmentation – allocated memory may be slightly larger than
requested memory; this size difference is memory internal to a partition, but
not being used
23.
24. Paging
Physical address space of a process can be noncontiguous;
process allocates physical memory whenever the latter is available
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
To run a program of size N pages, need to find N free frames and load program
Backing store likewise split into pages
Set up a page table to translate logical to physical addresses
System keeps track of all free frames
25. Paging Model of Logical and Physical Memory
page table to translate logical to physical
addresses
26. Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table
which contains base address of each page in physical memory
Page offset (d) – offset within a page
combined with base address to define the physical memory address that is sent to the
memory unit
For given logical address space 2m and page size 2n
page number page offset
p d
m - n n
offset
page
29. Paging
External fragmentation??
Calculating internal fragmentation
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
So small frame sizes desirable?
But increases the page table size
Poor disk I/O
Page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB
User’s view and physical memory now very different
user view=> process contains in single contiguous memory space
By implementation process can only access its own memory
protection
30. Each page table entry 4 bytes (32 bits) long
Each entry can point to 232 page frames
If each frame is 4 KB
The system can address 244 bytes (16TB) of physical memory
Virtual address space 16MB.
Page table size?
31. Process P1 arrives
Requires n pages => n frames must be available
Allocate n frames to the process P1
Create page table for P1
33. Implementation of Page Table
For each process, Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page table
In this scheme every data/instruction access requires two memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of a special fast-
lookup hardware cache called associative memory or translation look-aside
buffers (TLBs)
35. Associative Memory
Associative memory – parallel search
Address translation (p, d)
If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
Page # Frame #
36. Implementation of Page Table
For each process, Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page table
In this scheme every data/instruction access requires two memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation
look-aside buffers (TLBs)
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access next time
Replacement policies must be considered (LRU)
Some entries can be wired down for permanent fast access
Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process (PID) to provide address-space
protection for that process
Otherwise need to flush at every context switch
38. Effective Access Time
Associative Lookup = time unit
Can be < 10% of memory access time
Hit ratio =
Hit ratio – percentage of times that a page number is found in the associative registers;
ratio related to size of TLB
Consider = 80%, = 20ns for TLB search, 100ns for memory access
Effective Access Time (EAT)
EAT = (100 + ) + (200 + )(1 – )
Consider = 80%, = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 120 + 0.20 x 220 = 140ns
Consider better hit ratio -> = 98%, = 20ns for TLB search, 100ns for memory access
EAT = 0.98 x 120 + 0.02 x 220 = 122ns
39. Memory Protection
Memory protection implemented by associating protection bit with
each frame to indicate if read-only or read-write access is allowed
Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’ logical address
space, and is thus a legal page
“invalid” indicates that the page is not in the process’ logical address space
Or use PTLR
Any violations result in a trap to the kernel
40. Valid (v) or Invalid (i)
Bit In A Page Table
14 bit address space (0 to
16383)
Page size 2KB
Process P1 uses only 0 to 10468
Internal fragmentation Use of PTLR (length)
Page
0
Page
1
Page
2
Page
3
P1
P2
41. Shared Pages Example
System with 40 users
Use common text editor
Text editor contains 150KB code 50KB data (page size 50KB)
8000KB!
Shared code
One copy of read-only (reentrant) code shared among processes
(i.e., text editors, compilers, window systems)
Code never changes during execution
Only one copy of the editor in the memory
Total memory consumption
40*50+150=2150KB
43. Data share: example
int main()
{
int shmid,f,key=3,i,pid;
char *ptr;
shmid=shmget((key_t)key,100,IPC_CREAT|0666);
ptr=shmat(shmid,NULL,0);
printf("shmid=%d ptr=%un",shmid, ptr);
strcpy(ptr,"hello");
i=shmdt((char*)ptr);
}
int main()
{
int shmid,f,key=3,i,pid;
char *ptr;
shmid=shmget((key_t)key,100,IPC_CREAT|0666);
ptr=shmat(shmid,NULL,0);
printf("shmid=%d ptr=%un",shmid, ptr);
printf("nstr %sn",ptr);
}
writer.c
reader .c
ptr
Shared
memory
44. Structure of the Page Table
Memory requirement for page table can get huge using straight-forward methods
Consider a 32-bit logical address space as on modern computers
Page size of 4 KB (212)
Page table would have 1 million entries 220 (232 / 212)
If each entry is 4 bytes -> 4 MB of physical address space / memory for page table alone
That amount of memory used to cost a lot
Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
45. Hierarchical Page Tables
Break up the page table into multiple pages
We then page the page table
A simple technique is a two-level page table
47. Two-Level Paging Example
A logical address (on 32-bit machine with 4KB page size) is divided into:
a page number consisting of 20 bits
a page offset consisting of 12 bits
Since the page table is paged, the page number is further divided into:
a 10-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
where p1 is an index into the outer page table, and p2 is the displacement within
the page of the inner page table
page number page offset
p1 p2 d
10 10 12
50. 64-bit Logical Address Space
Even two-level paging scheme not sufficient
If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210 4-byte entries
Address would look like
Outer page table has 242 entries or 244 bytes
One solution is to add a 2nd outer page table
But in the following example the 2nd outer page table is still 234 bytes in size
And possibly 4 memory access to get to one physical memory location
outer page page offset
p1 p2 d
42 10 12
inner page
52. Hashed Page Tables
Common in virtual address spaces > 32 bits
The page number is hashed into a page table
This page table contains a chain of elements hashing to the same location
Each element contains (1) the page number (2) the value of the mapped
page frame (3) a pointer to the next element
Virtual page numbers are compared in this chain searching for a match
If a match is found, the corresponding physical frame is extracted
54. Inverted Page Table
Rather than each process having a page table and keeping track of all possible
logical pages, track all frames
One entry for each frame
Entry consists the page number stored in that frame, with information about
the process that owns that page
Decreases memory needed to store each page table,
but increases time needed to search the table when a page reference occurs
55. Inverted Page Table Architecture
64 bit UltraSPARC, PowerPC,
Address space ID
56. Segmentation
Memory-management scheme that supports user view of memory
A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Compiler generates
the segments
Loader assign the
seg#
57. User’s View of a Program
User specifies each
address by two quantities
(a) Segment name
(b) Segment offset
Logical address contains
the tuple
<segment#, offset>
• Variable size segments without
order
• Length=> purpose of the program
• Elements are identified by offset
58. Logical View of Segmentation
1
3
2
4
1
4
2
3
user space physical memory space
• Long term scheduler finds and allocates memory for all segments of a
program
• Variable size partition scheme
Logical
address
space
Logical address <segment-number,
offset>
62. Executable file and virtual
address
Virtual address
space
a.out
Symbol table
Name address
SQR 0
SUM 4
0 Load 0
4 ADD 4
<CODE, 0> Load <ST,0>
<CODE, 2> ADD <ST,4>
Paging view
Segmentation view
63. Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>
Segment table – maps two-dimensional logical address to physical address;
Each table entry has:
base – contains the starting physical address where the segments reside in memory
limit – specifies the length of the segment
Segment-table base register (STBR) points to the segment table’s location in
memory
Segment-table length register (STLR) indicates number of segments used by
a program;
segment number s is legal if s < STLR
67. Segmentation Architecture
Protection
Protection bits associated with segments
With each entry in segment table associate:
validation bit = 0 illegal segment
read/write/execute privileges
Code sharing occurs at segment level
Since segments vary in length, memory allocation is a dynamic storage-
allocation problem
Long term scheduler
First fit, best fit etc
Fragmentation
68. Segmentation with Paging
Key idea:
Segments are splitted into multiple pages
Each page is loaded into frames in the memory
69. Segmentation with Paging
Supports segmentation with paging
Each segment can be 4 GB
Up to 16 K segments per process
<selector(16), offset (32)>
Divided into two partitions
First partition of up to 8 K segments are private to process (kept in local descriptor table LDT)
Second partition of up to 8K segments shared among all processes (kept in global descriptor
table GDT)
CPU generates logical address (six Segment Reg.)
Given to segmentation unit
Which produces linear addresses
Physical address 32 bits
Linear address given to paging unit
Which generates physical address in main memory
Paging units form equivalent of MMU
Pages sizes can be 4 KB
Intel 80386
IBM OS/2
S(13) G(1) P(2)
75. Background
Code needs to be in memory to execute, but entire program rarely used
Error code, unusual routines, large data structures
Entire program code not needed at same time
Consider ability to execute partially-loaded program
Program no longer constrained by limits of physical memory
programs could be larger than physical memory
More processes can be accommodated
76. Virtual Memory That is
Larger Than Physical Memory
Large
virtual
space
Small memory
77. Classical paging
Process P1 arrives
Requires n pages => n frames must be available
Allocate n frames to the process P1
Create page table for P1
Allocate < n frames
78. Background
Virtual memory – separation of user logical memory from physical memory
Extremely large logical space is available to programmer
Concentrate on the problem
Only part of the program needs to be in memory for execution
Logical address space can therefore be much larger than physical address space
Starts with address 0, allocates contiguous logical memory
Physical memory
Collection of frame
Virtual memory can be implemented via:
Demand paging
Demand segmentation
79. Demand Paging
Bring a page into memory only when it is needed
Lazy swapper – never swaps a page into memory unless page will be needed
Swapper that deals with pages is a pager
Less I/O needed, no unnecessary I/O
Less memory needed
More users
Page is needed reference to it
invalid reference abort
not-in-memory bring to memory
Valid address
information is
available in PCB
80. Transfer of a Paged Memory to
Contiguous Disk Space
• When we want to
execute a process, swap
in
• Instead of swap in
entire process, load
page
• Pager
81. Page Table When Some Pages
Are Not in Main Memory
Pager loads few necessary pages in
memory
82. Valid-Invalid Bit
With each page table entry a valid–invalid bit is associated
(v in-memory – memory resident, i not-in-memory)
Initially valid–invalid bit is set to i on all entries
Example of a page table snapshot:
During address translation, if valid–invalid bit in page table
v
v
v
v
i
i
i
….
Frame # valid-invalid bit
page table
Disk
address
83. Page Fault
If the page in not in memory, first reference to that page will
trap to operating system:
page fault
1. Operating system looks at PCB to decide:
Invalid reference abort
Just not in memory (load the page)
2. Get empty frame
3. Swap page into frame via scheduled disk operation
4. Reset page table to indicate page now in memory
Set validation bit = v
5. Restart the instruction that caused the page fault
84. What Happens if There is no Free Frame?
Example
40 frames in memory
8 processes each needs 10 pages
5 of them never used
Two options
Run 4 processes (10 pages)
Run 8 processes (5 pages)
Increase the degree of multiprogramming
Over allocating memory
Page fault
No free frame
Terminate? swap out? replace the page?
Page replacement – find some page in memory, not really in use, page it out
Performance – want an algorithm which will result in minimum number of page faults
Same page may be brought into memory several times
86. Pure Demand Paging
Extreme case – start process with no pages in memory
OS sets instruction pointer to first instruction of process, non-memory-resident ->
page fault
Swap in that page
Pure demand paging
Actually, a given instruction could access multiple pages (instruction + data) ->
multiple page faults
Pain decreased because of locality of reference
Hardware support needed for demand paging
Page table with valid / invalid bit
Secondary memory (swap device with swap space)
Instruction restart after page fault
87. Steps in the ISR
In Demand Paging
1. Trap to the operating system
2. Save the user registers and process state
3. Determine that the interrupt was a page fault
4. Check that the page reference was legal and determine the location of the page on the disk
5. Get a free frame
6. Issue a read from the disk to a free frame:
1. Wait in a queue for this device until the read request is serviced
2. Wait for the device seek and/or latency time
3. Begin the transfer of the page to a free frame
7. While waiting, allocate the CPU to some other user
8. Receive an interrupt from the disk I/O subsystem (I/O completed)
9. Save the registers and process state of the running process
10. Determine that the interrupt was from the disk
11. Correct the page table and other tables to show page is now in memory
12. Wait for the CPU to be allocated to this process again
13. Restore the user registers, process state, and new page table, and then resume the interrupted
instruction
88. Performance of Demand Paging
Page Fault Rate 0 p 1
if p = 0 no page faults
if p = 1, every reference is a fault
Effective Access Time (EAT)
EAT = (1 – p) x memory access
+ p (page fault overhead
+ swap page out
+ swap page in
+ restart overhead
)
Demand paging affects the performance of the computer
systems
89. Demand Paging Example
Memory access time = 200 nanoseconds
Average page-fault service time = 8 milliseconds
EAT = (1 – p) x 200 + p (8 milliseconds)
= (1 – p ) x 200 + p x 8,000,000
= 200 + p x 7,999,800
If one access out of 1,000 causes a page fault, then
EAT = 8.2 microseconds.
This is a slowdown by a factor of 40!!
If want performance degradation < 10 percent
220 > 200 + 7,999,800 x p
20 > 7,999,800 x p
p < .0000025
< one page fault in every 400,000 memory accesses
Better utilization of swap space
Swap space
90. Allocation of Frames
How do we allocate the fixed amount of memory among various processes?
Single user system
Trivial
91. Allocation of Frames
Each process needs minimum number of frames
Minimum number is defined by the instruction set
Page fault forces to restart the instruction
Enough frames to hold all the pages for that instruction
Example:
Single address instruction (2 frames)
Two address instruction (3 frames)
Maximum of course is total frames in the system
Two major allocation schemes
fixed allocation
proportional allocation
92. Fixed and proportional Allocation
Equal allocation – m frames and n processes
Each process gets m/n
For example, if there are 100 frames (after allocating
frames for the OS) and 5 processes, give each process
20 frames
Keep some as free frame buffer pool
Unfair for small and large sized processes
Proportional allocation – Allocate according to the size
of process
Dynamic as degree of multiprogramming, process
sizes change
m
S
s
p
a
m
s
S
p
s
i
i
i
i
i
i
for
allocation
frames
of
number
total
process
of
size
m 64
s1 10
s2 127
a1
10
137
64 5
a2
127
137
64 59
93. Priority Allocation
Allocation of frames
Depends on multiprogramming level
Use a proportional allocation scheme using priorities along with size
96. Basic Page Replacement
1. Find the location of the desired page on disk
2. Find a free frame:
- If there is a free frame, use it
- If there is no free frame, use a page replacement algorithm to select a
victim frame (of that process)
- Write victim frame to disk
3. Bring the desired page into the (newly) free frame; update the page and frame
tables
4. Continue the process by restarting the instruction that caused the trap
Note now potentially 2 page transfers for page fault – increasing Effective memory
access time
99. Evaluation
Evaluate algorithm by running it on a particular string of memory
references (reference string) and computing the number of page faults
on that string
String is just page numbers, not full addresses
Repeated access to the same page does not cause a page fault
Trace the memory reference of a process
0100, 0432, 0101, 0612, 0102, 0104, 0101, 0611, 0102
Page size 100B
Reference string 1, 4, 1, 6, 1, 6
In all our examples, the reference string is
7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
101. Associates a time with each frame when the page was
brought into memory
When a page must be replaced, the oldest one is chosen
Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
First-In-First-Out (FIFO)
Algorithm
Limitation:
A variable is initialized early and constantly used
102. FIFO Page Replacement
• How to track ages of pages?
• Just use a FIFO queue to hold all the pages in memory
• Replace the page at the head
• Insert at tail
3 frames (3 pages can be in memory at a time)
15 page faults
103. Optimal Algorithm
Replace page that will not be used for longest period of
time
How do you know this?
Can’t read the future
Used for measuring how well your algorithm performs
105. Least Recently Used (LRU) Algorithm
Use past knowledge rather than future
Past is the proxy of future
Replace page that has not been used in the most of the time
Associate time of last use with each page
12 faults – better than FIFO but worse than OPT
Generally good algorithm and frequently used
But how to implement?
106. LRU Algorithm-Implementation
Counter implementation
CPU maintains a clock
Every page entry has a Time of use;
every time page is referenced, copy the clock into the
time of use
When a page needs to be replaced, look at the “Time of use”
to find smallest value
Search through table needed
CPU
Clock
address
Time of
Use
Page
table
0
1
2
3
107. • Stack implementation
• Keep a stack of page numbers in a double linked list form:
• Page referenced:
• move it to the top
• Victim page is the bottom page
LRU Algorithm-Implementation
108. LRU Approximation Algorithms
LRU needs special hardware and still slow
Reference bit
With each page associate a bit, initially = 0
When page is referenced bit set to 1
Additional reference bit algorithm
Record the reference bits in regular interval
Keep a 8 bit string for each page in memory
At regular interval, timer copies the reference bit to the high order bit (MSB) of
the string.
Shift the other bits right side by one bit
110. LRU Approximation Algorithms
LRU needs special hardware and still slow
Reference bit
With each page associate a bit, initially = 0
When page is referenced bit set to 1
Additional reference bit algorithm
Second-chance algorithm
Generally FIFO, plus hardware-provided reference bit
Clock replacement
If page to be replaced has
Reference bit = 0 -> replace it
reference bit = 1 then:
set reference bit 0, leave page in memory (reset the time)
replace next page, subject to same rules
112. Counting Algorithms
Keep a counter of the number of references that have been made to
each page
LFU Algorithm: replaces page with smallest count
MFU Algorithm: based on the argument that the page with the
smallest count was probably just brought in and has yet to be used
Least and most frequently used
117. Belady’s Anomaly
This most unexpected result is known as Belady’s anomaly –
for some page-replacement algorithms, the page fault rate
may increase as the number of allocated frames increases
Is there a characterization of algorithms susceptible to
Belady’s anomaly?
118. Stack Algorithms
Certain page replacement algorithms are more “well behaved” than others
(In the FIFO example), the problem arises because the set of pages loaded with a memory
allocation of 3 frames is not necessarily also loaded with a memory allocation of 4 frames
There are a set of paging algorithms whereby the set of pages loaded with an allocation of
m frames is always a subset of the set of pages loaded with an allocation of m +1 frames.
This property is called the inclusion property
Algorithms that satisfy the inclusion property are not subject to Belady’s anomaly. FIFO
does not satisfy the inclusion property and is not a stack algorithm
120. Global vs. Local Allocation
Frames are allocated to various processes
If process Pi generates a page fault
select for replacement one of its frames
select for replacement a frame from another process
Local replacement – each process selects from only its own set of allocated frames
More consistent per-process performance
But possibly underutilized memory
Global replacement – process selects a replacement frame from the set of all
frames; one process can take a frame from another
But then process execution time can vary greatly
But greater throughput ----- so more common
Processes can not control its own page fault rate
Depends on the paging behavior of other processes
121. Thrashing
If a process uses a set of “active pages”
Number of allocated frames is less than that
Page-fault
Replace some “active” page
But quickly need replaced “active” frame back
Quickly a page fault, again and again
Thrashing a process is busy swapping pages in and out
OS monitors CPU utilization
If low? Increase the degree of multiprogramming
122. Thrashing
Global page replacement
Process enters new phase (subroutine call) execution
Page fault
Taking frames from other processes
Replace “active” frames of other processes
These processes start page fault
These faulting processes wait on the device queue for disk
Ready queue empty
CPU utilization decreases
CPU scheduler increases the degree of multiprogramming
More page faults
Drop in CPU utilization
Page fault increases tremendously
Disk
124. Thrashing
Solution
Local replacement
One process cannot steal frames from other processes
Provide a process as many frames as needed
Able to load all active pages
How do we know?
Locality model
125. Demand Paging and Thrashing
Why does demand paging work?
Locality model
Process migrates from one locality to another
Localities may overlap
Allocate enough frames to a process to accommodate its locality
Why does thrashing occur?
size of locality > total allocated frames
Limit effects by using local or priority page replacement
128. Working-Set Model
working-set window a fixed number of page references
Example: 10,000 instructions
WSSi (working set of Process Pi) =
total number of pages referenced in the most recent (varies in time)
if too small will not encompass entire locality
if too large will encompass several localities
if = will encompass entire program
D = WSSi total demand frames
Approximation of locality
if D > m Thrashing
Policy if D > m, then suspend or swap out one of the processes
129. Page-Fault Frequency
More direct approach than WSS
Establish “acceptable” page-fault frequency (PFF) rate and
use local replacement policy
If actual rate too low, process loses frame
If actual rate too high, process gains frame