This document summarizes a research paper on implementing low power divider techniques using radix-8 division. It describes the design of a radix-8 divider that aims to reduce energy dissipation without penalizing latency. The algorithm and implementation of the divider are explained. Several low power techniques are then applied, including switching off inactive blocks, retiming the recurrence, reducing transitions in multiplexers, changing the redundant representation, partitioning the selection function, and modifying the conversion and rounding process. Applying these techniques can reduce energy dissipation by up to 70% compared to a standard implementation. The performance of the radix-8 divider is also compared to a radix-4 divider and one using overlapped radix-2 stages.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
Low Power Adaptive FIR Filter Based on Distributed ArithmeticIJERA Editor
This paper aims at implementation of a low power adaptive FIR filter based on distributed arithmetic (DA) with
low power, high throughput, and low area. Least Mean Square (LMS) Algorithm is used to update the weight
and decrease the mean square error between the current filter output and the desired response. The pipelined
Distributed Arithmetic table reduces switching activity and hence it reduces power. The power consumption is
reduced by keeping bit-clock used in carry-save accumulation much faster than clock of rest of the operations.
We have implemented it in Quartus II and found that there is a reduction in the total power and the core dynamic
power by 31.31% and 100.24% respectively when compared with the architecture without DA table
ICPP'18 paper :
"Parallelizing Pruning-based Graph Structural Clustering"
For details (codes/experimental results), see
https://github.com/GraphProcessor/ppSCAN
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of Compensator for Roll Control of Towing Air-Craftspaperpublications3
Abstract: It is a difficult task to make proper adjustment of towing vehicles, keeping the motion secured and predetermined. In older days the control was manual. Now-a-days automatic feedback control systems are used. The specifications are very stringent due to imposition of govt. and industrial rules. There are constraints on steady state accuracy, transient performance and stability margins. The requirements are contradictory. If the steady state accuracy is realized, the transient requirements and the stability margins cannot be maintained. It is difficult to fulfil the requirements by modifying the feedback or adding feed-forward. It is expedient to add a compensator in the forward or feedback path. In this paper, the design of a towing aircraft has been taken up. Its block diagram and transfer function are given. The gain has been fixed up to keep the steady state error within prescribed limits. The transient performance has been shaped and stability ensured by adding a lag compensator of chosen parameters.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
Low Power Adaptive FIR Filter Based on Distributed ArithmeticIJERA Editor
This paper aims at implementation of a low power adaptive FIR filter based on distributed arithmetic (DA) with
low power, high throughput, and low area. Least Mean Square (LMS) Algorithm is used to update the weight
and decrease the mean square error between the current filter output and the desired response. The pipelined
Distributed Arithmetic table reduces switching activity and hence it reduces power. The power consumption is
reduced by keeping bit-clock used in carry-save accumulation much faster than clock of rest of the operations.
We have implemented it in Quartus II and found that there is a reduction in the total power and the core dynamic
power by 31.31% and 100.24% respectively when compared with the architecture without DA table
ICPP'18 paper :
"Parallelizing Pruning-based Graph Structural Clustering"
For details (codes/experimental results), see
https://github.com/GraphProcessor/ppSCAN
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of Compensator for Roll Control of Towing Air-Craftspaperpublications3
Abstract: It is a difficult task to make proper adjustment of towing vehicles, keeping the motion secured and predetermined. In older days the control was manual. Now-a-days automatic feedback control systems are used. The specifications are very stringent due to imposition of govt. and industrial rules. There are constraints on steady state accuracy, transient performance and stability margins. The requirements are contradictory. If the steady state accuracy is realized, the transient requirements and the stability margins cannot be maintained. It is difficult to fulfil the requirements by modifying the feedback or adding feed-forward. It is expedient to add a compensator in the forward or feedback path. In this paper, the design of a towing aircraft has been taken up. Its block diagram and transfer function are given. The gain has been fixed up to keep the steady state error within prescribed limits. The transient performance has been shaped and stability ensured by adding a lag compensator of chosen parameters.
On selection of periodic kernels parameters in time series predictioncsandit
In the paper the analysis of the periodic kernels parameters is described. Periodic kernels can
be used for the prediction task, performed as the typical regression problem. On the basis of the
Periodic Kernel Estimator (PerKE) the prediction of real time series is performed. As periodic
kernels require the setting of their parameters it is necessary to analyse their influence on the
prediction quality. This paper describes an easy methodology of finding values of parameters of
periodic kernels. It is based on grid search. Two different error measures are taken into
consideration as the prediction qualities but lead to comparable results. The methodology was
tested on benchmark and real datasets and proved to give satisfactory results.
Advanced Stability Analysis of Control Systems with Variable Parametersjournal ijrtem
The purpose of the current research is to advance further the D-Partitioning method and
emphasize on its practical application. It has the objective to clarify it in a user friendly manner in order to
simplify its implementation. By applying the basic initial ideas of the method, the main line of the research is the
development of a generalized stability analysis tool and demonstrating its application. With the aid of this tool,
proper parameter values can be chosen for a desirable performance and stability of a system. The analysis tool
can be practically used when one, two or more system’s parameters are varied independently or simultaneously.
Basically this tool defines regions of stability in the space of the system’s parameters.
Tomography is important for network design and routing optimization. Prior approaches require either
precise time synchronization or complex cooperation. Furthermore, active tomography consumes explicit
probing resulting in limited scalability. To address the first issue we propose a novel Delay Correlation
Estimation methodology named DCE with no need of synchronization and special cooperation. For the
second issue we develop a passive realization mechanism merely using regular data flow without explicit
bandwidth consumption. Extensive simulations in OMNeT++ are made to evaluate its accuracy where we
show that DCE measurement is highly identical with the true value. Also from test result we find that
mechanism of passive realization is able to achieve both regular data transmission and purpose of
tomography with excellent robustness versus different background traffic and package size.
Performance Assessment of Polyphase Sequences Using Cyclic Algorithmrahulmonikasharma
Polyphase Sequences (known as P1, P2, Px, Frank) exist for a square integer length with good auto correlation properties are helpful in the several applications. Unlike the Barker and Binary Sequences which exist for certain length and exhibits a maximum of two digit merit factor. The Integrated Sidelobe level (ISL) is often used to define excellence of the autocorrelation properties of given Polyphase sequence. In this paper, we present the application of Cyclic Algorithm named CA which minimizes the ISL (Integrated Sidelobe Level) related metric which in turn improve the Merit factor to a greater extent is main thing in applications like RADAR, SONAR and communications. To illustrate the performance of the P1, P2, Px, Frank sequences when cyclic Algorithm is applied. we presented a number of examples for integer lengths. CA(Px) sequence exhibits the good Merit Factor among all the Polyphase sequences that are considered.
Numerical Simulation of Gaseous Microflows by Lattice Boltzmann MethodIDES Editor
This work is concerned with application of the
Lattice Boltzmznn Method (LBM) to compute flows in microgeometries.
The choice of using LBM for microflow simulation
is a good one owing to the fact that it is based on the Boltzmann
equation which is valid for the whole range of the Knudsen
number. In this work LBM is applied to simulate the pressure
driven microchannel flows and micro lid-driven cavity flows.
First, the microchannel flow is studied in some details with
the effects of varying the Knudsen number, pressure ratio
and Tangential Momemtum Accomodation Coefficient
(TMAC). The pressure distribution and other parameters are
compared with available experimental and analytical data
with good agreement. After having thus established the
credibility of the code and the method including boundary
conditions, LBM is then used to investigate the micro liddriven
cavity flow. The computations are carried out mainly
for the slip regime and the threshold of the transition regime.
A modular abstraction is presented to implement model predictive control (MPC) on a three phase two level voltage source inverter to control its output current. Traditional ways of coded implementation do not provide insights into the complex nature of MPC; hence a more intuitive, logical and flexible approach for hardware implementation is conceptualized in the form of signal flow graphs (SFGs) for estimation, prediction and optimization. Simulation results show good performance of the approach and easier code generation for real time implementation. RL load is assumed for the inverter and the importance of choosing load inductance and sampling time ratio is emphasized for better control performance.
Controller Design and Load Frequency Control for Single Area Power System wit...IJERA Editor
The performance of power systems gets worsening due to the presence of sudden load changes, uncertainties of
parameters etc. Therefore the design of load frequency control is very important in the modern power systems.
This paper presents LFC control technique to reject the typical disturbance as well as control the large-scale
system problems. Parameter uncertainty and load disturbance approach has been proposed to LFC design on the
purpose of rejection of typical disturbances. This paper presents the model order reduction technique of Transfer
function of the single area power system by using Routh approximation. The Second-order reduced system
model has proposed instead of full order system to effectively improve the performance of the closed loop
system. This entire approach is simulated in MATLAB environment for a single –area power system. In
addition to this the reduced order power system is converted into digital domain for digital implementation of
load frequency controller.
Discrete-wavelet-transform recursive inverse algorithm using second-order est...TELKOMNIKA JOURNAL
The recursive-least-squares (RLS) algorithm was introduced as an alternative to LMS algorithm with enhanced performance. Computational complexity and instability in updating the autocolleltion matrix are some of the drawbacks of the RLS algorithm that were among the reasons for the intrduction of the second-order recursive inverse (RI) adaptive algorithm. The 2nd order RI adaptive algorithm suffered from low convergence rate in certain scenarios that required a relatively small initial step-size. In this paper, we propose a newsecond-order RI algorithm that projects the input signal to a new domain namely discrete-wavelet-transform (DWT) as pre step before performing the algorithm. This transformation overcomes the low convergence rate of the second-order RI algorithm by reducing the self-correlation of the input signal in the mentioned scenatios. Expeirments are conducted using the noise cancellation setting. The performance of the proposed algorithm is compared to those of the RI, original second-order RI and RLS algorithms in different Gaussian and impulsive noise environments. Simulations demonstrate the superiority of the proposed algorithm in terms of convergence rate comparedto those algorithms.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
A landing gear assembly consists of various components viz. Lower side stay, Upperside stay, Locking actuators, Extension actuators, Tyres, and Locking pins to name a few. Each unit having a specific operation to deal with, in this project the main unit being studied is the lower brace. The primary objective is to analyse stresses in the element of the lower brace unit using strength of materials or RDM method and Finite Element Method (FEM) and compare both. Using the obtained data a suitable material is proposed for the component. The approach used here is to study the overall behaviour of the element by taking up each aspect, finally summing up the total effect of all the aspects in the functioning of the element.
Study and comparative analysis of resonat frequency for microsrtip fractal an...eSAT Journals
Abstract A new compact fractal patch antenna is designed based on the fractal geometry. Based on the simulation results, the proposed antenna has shown an excellent size reduction possibility with good radiation performance for wireless communication applications. The change in resonating frequency with respect to the dielectric constant of substrate has shown and discussed in this paper. The various resonating frequencies for designed antenna are 8.59GHz, 9.2 GHz and 11.36 GHz for RT Duroid Rogers 6010, FR 4 and RT Duroid Rogers 5880 respectively. The S-parameter (S11) for resonating frequencies is well below -10 dB. The far-field patternandS11oftheproposedantennaissimulatedandanalyzedusingCST Microwave Studio 2011
Water quality index with missing parameterseSAT Journals
Abstract This paper presents the efficient modifications in calculating formula of water quality index. Water quality index provides us a single number which expresses overall water quality at a certain location and time which is based on several quality parameters. The objective of an index is to turn complex water quality data into information that is understandable and usable by the public. In this paper a formula will be found to calculate water quality index when the numerical value of some of it’s quality parameters are missing. The standard formula to calculate water quality index has nine water quality parameters- biochemical oxygen demand, dissolved oxygen, pH, nitrate, phosphate, faecal coliform, turbidity, total dissolve solids and temperature. Sometimes it becomes very difficult to find out the values of all these parameters because of lack of time or because of failure in testing. In that case the formula with missing parameters will help us to calculate water quality index. Index Terms: Water quality index, q- values, weight factors, weighted mean.
System identification of a steam distillation pilot scale using arx and narx ...eSAT Journals
Abstract This paper presents steam temperature models for steam distillation pilot-scale (SDPS) by comparing Pseudo Random Binary Sequence (PRBS) versus Multi-Sine (M-Sine) perturbation signal Both perturbation signals were applied to nonlinear steam distillation system to study the capability of these input signals in exciting nonlinearity of system dynamics. In this work, both linear and nonlinear ARX model structures have been investigated. Five statistical approaches have been observed to evaluate the developed steam temperature models, namely, coefficient of determination, R2; auto-correlation function, ACF; cross-correlation function, CCF; root mean square error, RMSE; and residual histogram. The results showed that the nonlinear ARX models are superior as compared to the linear models when M-Sine perturbation applied to the steam distillation system. While, PRBS perturbation exhibit insufficient to model nonlinear system dynamic Keywords: SDPS, PRBS, M-Sine, ARX, R2, ACF, CCF, RMSE
A mathematical formulation of urban zoning selection criteria in a distribute...eSAT Journals
Abstract
Distributed Service Network is a wide term related to distribution and travelling i.e. distribution of resource among facilities located at various locations and travelling of resource along a distributed network. Policy making problems in distributed service networks can be clearly classified into a number of hierarchical levels. The levels are distinguished by time horizon of the problem, by amount of cost involved in the implementation of a solution, and by the political implications of the solution. In the public sector, it includes ambulance, fire, police and other services. In the private sector courier, taxi, repair, maintenance and the like are considered to be distributed service network.
In this paper an attempt has been made to obtain a mathematical model by which a network can be partitioned into subnetworks in a Distributed Service Network. The constraints like demand equity, contiguity, compactness, enclaves etc. are applied for Zoning.
Keywords: Zoning, Contiguity, subnetwork, Compactness, Enclave.
Performance analysis of al fec raptor code over 3 gpp embms networkeSAT Journals
Abstract Long Term Evolution (LTE) is the current standard for mobile networks based on Third Generation Partnership Project. LTE includes enhanced multimedia broadcast and multicast services (MBMS), also called as Evolved multimedia broadcast and multicast services (eMBMS) where the same content is transmitted to multiple users in one specific area. eMBMS is a new function defined in 3GPP Release 8 specification that supports the delivery of content and streaming to group users into LTE mobile networks. In LTE an important point of demanding multimedia services is to improve the robustness against packet losses. In this direction, in order to support effective point-to-multipoint download and streaming delivery, 3GPP has included an Application Layer Forward Error Correction (AL-FEC) scheme in the standard eMBMS. The standard AL-FEC system is based on systematic, fountain Raptor codes. Raptor coding is very useful in case of packet loss during transmission as it recover all data back from insufficient data at receiver terminal .In our work, in response to the emergence of an enhanced AL-FEC scheme, a raptor code has been implemented and performance is evaluated and the simulation results are obtained. Index Terms: long term evolution; multimedia broadcast multicast services; forward error correction; raptor codes
A survey on hiding user privacy in location based services through clusteringeSAT Journals
Abstract Smartphone’s are being more and more popular as the technology being evolve. The Smartphone’s are capable of providing the location aware services like GPS. They share all the location information with the central location server. When user submit any query then these query also carries some personal information of the user. This query and information is then submitted to the LGS server. At the LBS server this information is not much confidential. Someone can use this information to make user panic. To overcome this we are proposing the new collaborative approach to hide user’s personal data from the LBS server. Our approach does not lead to make changes in the architecture of the LBS server. And we are also not going to use the third party server. Here we are going to use the other user’s device to search other users query so that other user can be get hide from the LBS server. Keywords: Mobile networks, location-based services, location privacy, Bayesian inference attacks, epidemic models
Reusing of glass powder and industrial waste materials in concreteeSAT Journals
Abstract A huge amount of concrete is consumed in the construction work. A good quality concrete is mixing of cement, fine and coarse aggregates, water and admixtures as needed to obtain an optimum quality and economy. In this study investigation were carried out on compressive strength, split tensile strength and water absorption of M-40 grade of concrete mixes with 20% constant replacement of waste glass powder in cement and partial replacement of waste foundry sand in fine aggregate. From the test results, strength are achieved very less on 7th and 14th das but it increases on the 28thday. High strength values found at 40% replacement level in strength parameters. Keywords: waste glass powder, waste foundry sand, eco-friendly, concrete mix.
On selection of periodic kernels parameters in time series predictioncsandit
In the paper the analysis of the periodic kernels parameters is described. Periodic kernels can
be used for the prediction task, performed as the typical regression problem. On the basis of the
Periodic Kernel Estimator (PerKE) the prediction of real time series is performed. As periodic
kernels require the setting of their parameters it is necessary to analyse their influence on the
prediction quality. This paper describes an easy methodology of finding values of parameters of
periodic kernels. It is based on grid search. Two different error measures are taken into
consideration as the prediction qualities but lead to comparable results. The methodology was
tested on benchmark and real datasets and proved to give satisfactory results.
Advanced Stability Analysis of Control Systems with Variable Parametersjournal ijrtem
The purpose of the current research is to advance further the D-Partitioning method and
emphasize on its practical application. It has the objective to clarify it in a user friendly manner in order to
simplify its implementation. By applying the basic initial ideas of the method, the main line of the research is the
development of a generalized stability analysis tool and demonstrating its application. With the aid of this tool,
proper parameter values can be chosen for a desirable performance and stability of a system. The analysis tool
can be practically used when one, two or more system’s parameters are varied independently or simultaneously.
Basically this tool defines regions of stability in the space of the system’s parameters.
Tomography is important for network design and routing optimization. Prior approaches require either
precise time synchronization or complex cooperation. Furthermore, active tomography consumes explicit
probing resulting in limited scalability. To address the first issue we propose a novel Delay Correlation
Estimation methodology named DCE with no need of synchronization and special cooperation. For the
second issue we develop a passive realization mechanism merely using regular data flow without explicit
bandwidth consumption. Extensive simulations in OMNeT++ are made to evaluate its accuracy where we
show that DCE measurement is highly identical with the true value. Also from test result we find that
mechanism of passive realization is able to achieve both regular data transmission and purpose of
tomography with excellent robustness versus different background traffic and package size.
Performance Assessment of Polyphase Sequences Using Cyclic Algorithmrahulmonikasharma
Polyphase Sequences (known as P1, P2, Px, Frank) exist for a square integer length with good auto correlation properties are helpful in the several applications. Unlike the Barker and Binary Sequences which exist for certain length and exhibits a maximum of two digit merit factor. The Integrated Sidelobe level (ISL) is often used to define excellence of the autocorrelation properties of given Polyphase sequence. In this paper, we present the application of Cyclic Algorithm named CA which minimizes the ISL (Integrated Sidelobe Level) related metric which in turn improve the Merit factor to a greater extent is main thing in applications like RADAR, SONAR and communications. To illustrate the performance of the P1, P2, Px, Frank sequences when cyclic Algorithm is applied. we presented a number of examples for integer lengths. CA(Px) sequence exhibits the good Merit Factor among all the Polyphase sequences that are considered.
Numerical Simulation of Gaseous Microflows by Lattice Boltzmann MethodIDES Editor
This work is concerned with application of the
Lattice Boltzmznn Method (LBM) to compute flows in microgeometries.
The choice of using LBM for microflow simulation
is a good one owing to the fact that it is based on the Boltzmann
equation which is valid for the whole range of the Knudsen
number. In this work LBM is applied to simulate the pressure
driven microchannel flows and micro lid-driven cavity flows.
First, the microchannel flow is studied in some details with
the effects of varying the Knudsen number, pressure ratio
and Tangential Momemtum Accomodation Coefficient
(TMAC). The pressure distribution and other parameters are
compared with available experimental and analytical data
with good agreement. After having thus established the
credibility of the code and the method including boundary
conditions, LBM is then used to investigate the micro liddriven
cavity flow. The computations are carried out mainly
for the slip regime and the threshold of the transition regime.
A modular abstraction is presented to implement model predictive control (MPC) on a three phase two level voltage source inverter to control its output current. Traditional ways of coded implementation do not provide insights into the complex nature of MPC; hence a more intuitive, logical and flexible approach for hardware implementation is conceptualized in the form of signal flow graphs (SFGs) for estimation, prediction and optimization. Simulation results show good performance of the approach and easier code generation for real time implementation. RL load is assumed for the inverter and the importance of choosing load inductance and sampling time ratio is emphasized for better control performance.
Controller Design and Load Frequency Control for Single Area Power System wit...IJERA Editor
The performance of power systems gets worsening due to the presence of sudden load changes, uncertainties of
parameters etc. Therefore the design of load frequency control is very important in the modern power systems.
This paper presents LFC control technique to reject the typical disturbance as well as control the large-scale
system problems. Parameter uncertainty and load disturbance approach has been proposed to LFC design on the
purpose of rejection of typical disturbances. This paper presents the model order reduction technique of Transfer
function of the single area power system by using Routh approximation. The Second-order reduced system
model has proposed instead of full order system to effectively improve the performance of the closed loop
system. This entire approach is simulated in MATLAB environment for a single –area power system. In
addition to this the reduced order power system is converted into digital domain for digital implementation of
load frequency controller.
Discrete-wavelet-transform recursive inverse algorithm using second-order est...TELKOMNIKA JOURNAL
The recursive-least-squares (RLS) algorithm was introduced as an alternative to LMS algorithm with enhanced performance. Computational complexity and instability in updating the autocolleltion matrix are some of the drawbacks of the RLS algorithm that were among the reasons for the intrduction of the second-order recursive inverse (RI) adaptive algorithm. The 2nd order RI adaptive algorithm suffered from low convergence rate in certain scenarios that required a relatively small initial step-size. In this paper, we propose a newsecond-order RI algorithm that projects the input signal to a new domain namely discrete-wavelet-transform (DWT) as pre step before performing the algorithm. This transformation overcomes the low convergence rate of the second-order RI algorithm by reducing the self-correlation of the input signal in the mentioned scenatios. Expeirments are conducted using the noise cancellation setting. The performance of the proposed algorithm is compared to those of the RI, original second-order RI and RLS algorithms in different Gaussian and impulsive noise environments. Simulations demonstrate the superiority of the proposed algorithm in terms of convergence rate comparedto those algorithms.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
A landing gear assembly consists of various components viz. Lower side stay, Upperside stay, Locking actuators, Extension actuators, Tyres, and Locking pins to name a few. Each unit having a specific operation to deal with, in this project the main unit being studied is the lower brace. The primary objective is to analyse stresses in the element of the lower brace unit using strength of materials or RDM method and Finite Element Method (FEM) and compare both. Using the obtained data a suitable material is proposed for the component. The approach used here is to study the overall behaviour of the element by taking up each aspect, finally summing up the total effect of all the aspects in the functioning of the element.
Study and comparative analysis of resonat frequency for microsrtip fractal an...eSAT Journals
Abstract A new compact fractal patch antenna is designed based on the fractal geometry. Based on the simulation results, the proposed antenna has shown an excellent size reduction possibility with good radiation performance for wireless communication applications. The change in resonating frequency with respect to the dielectric constant of substrate has shown and discussed in this paper. The various resonating frequencies for designed antenna are 8.59GHz, 9.2 GHz and 11.36 GHz for RT Duroid Rogers 6010, FR 4 and RT Duroid Rogers 5880 respectively. The S-parameter (S11) for resonating frequencies is well below -10 dB. The far-field patternandS11oftheproposedantennaissimulatedandanalyzedusingCST Microwave Studio 2011
Water quality index with missing parameterseSAT Journals
Abstract This paper presents the efficient modifications in calculating formula of water quality index. Water quality index provides us a single number which expresses overall water quality at a certain location and time which is based on several quality parameters. The objective of an index is to turn complex water quality data into information that is understandable and usable by the public. In this paper a formula will be found to calculate water quality index when the numerical value of some of it’s quality parameters are missing. The standard formula to calculate water quality index has nine water quality parameters- biochemical oxygen demand, dissolved oxygen, pH, nitrate, phosphate, faecal coliform, turbidity, total dissolve solids and temperature. Sometimes it becomes very difficult to find out the values of all these parameters because of lack of time or because of failure in testing. In that case the formula with missing parameters will help us to calculate water quality index. Index Terms: Water quality index, q- values, weight factors, weighted mean.
System identification of a steam distillation pilot scale using arx and narx ...eSAT Journals
Abstract This paper presents steam temperature models for steam distillation pilot-scale (SDPS) by comparing Pseudo Random Binary Sequence (PRBS) versus Multi-Sine (M-Sine) perturbation signal Both perturbation signals were applied to nonlinear steam distillation system to study the capability of these input signals in exciting nonlinearity of system dynamics. In this work, both linear and nonlinear ARX model structures have been investigated. Five statistical approaches have been observed to evaluate the developed steam temperature models, namely, coefficient of determination, R2; auto-correlation function, ACF; cross-correlation function, CCF; root mean square error, RMSE; and residual histogram. The results showed that the nonlinear ARX models are superior as compared to the linear models when M-Sine perturbation applied to the steam distillation system. While, PRBS perturbation exhibit insufficient to model nonlinear system dynamic Keywords: SDPS, PRBS, M-Sine, ARX, R2, ACF, CCF, RMSE
A mathematical formulation of urban zoning selection criteria in a distribute...eSAT Journals
Abstract
Distributed Service Network is a wide term related to distribution and travelling i.e. distribution of resource among facilities located at various locations and travelling of resource along a distributed network. Policy making problems in distributed service networks can be clearly classified into a number of hierarchical levels. The levels are distinguished by time horizon of the problem, by amount of cost involved in the implementation of a solution, and by the political implications of the solution. In the public sector, it includes ambulance, fire, police and other services. In the private sector courier, taxi, repair, maintenance and the like are considered to be distributed service network.
In this paper an attempt has been made to obtain a mathematical model by which a network can be partitioned into subnetworks in a Distributed Service Network. The constraints like demand equity, contiguity, compactness, enclaves etc. are applied for Zoning.
Keywords: Zoning, Contiguity, subnetwork, Compactness, Enclave.
Performance analysis of al fec raptor code over 3 gpp embms networkeSAT Journals
Abstract Long Term Evolution (LTE) is the current standard for mobile networks based on Third Generation Partnership Project. LTE includes enhanced multimedia broadcast and multicast services (MBMS), also called as Evolved multimedia broadcast and multicast services (eMBMS) where the same content is transmitted to multiple users in one specific area. eMBMS is a new function defined in 3GPP Release 8 specification that supports the delivery of content and streaming to group users into LTE mobile networks. In LTE an important point of demanding multimedia services is to improve the robustness against packet losses. In this direction, in order to support effective point-to-multipoint download and streaming delivery, 3GPP has included an Application Layer Forward Error Correction (AL-FEC) scheme in the standard eMBMS. The standard AL-FEC system is based on systematic, fountain Raptor codes. Raptor coding is very useful in case of packet loss during transmission as it recover all data back from insufficient data at receiver terminal .In our work, in response to the emergence of an enhanced AL-FEC scheme, a raptor code has been implemented and performance is evaluated and the simulation results are obtained. Index Terms: long term evolution; multimedia broadcast multicast services; forward error correction; raptor codes
A survey on hiding user privacy in location based services through clusteringeSAT Journals
Abstract Smartphone’s are being more and more popular as the technology being evolve. The Smartphone’s are capable of providing the location aware services like GPS. They share all the location information with the central location server. When user submit any query then these query also carries some personal information of the user. This query and information is then submitted to the LGS server. At the LBS server this information is not much confidential. Someone can use this information to make user panic. To overcome this we are proposing the new collaborative approach to hide user’s personal data from the LBS server. Our approach does not lead to make changes in the architecture of the LBS server. And we are also not going to use the third party server. Here we are going to use the other user’s device to search other users query so that other user can be get hide from the LBS server. Keywords: Mobile networks, location-based services, location privacy, Bayesian inference attacks, epidemic models
Reusing of glass powder and industrial waste materials in concreteeSAT Journals
Abstract A huge amount of concrete is consumed in the construction work. A good quality concrete is mixing of cement, fine and coarse aggregates, water and admixtures as needed to obtain an optimum quality and economy. In this study investigation were carried out on compressive strength, split tensile strength and water absorption of M-40 grade of concrete mixes with 20% constant replacement of waste glass powder in cement and partial replacement of waste foundry sand in fine aggregate. From the test results, strength are achieved very less on 7th and 14th das but it increases on the 28thday. High strength values found at 40% replacement level in strength parameters. Keywords: waste glass powder, waste foundry sand, eco-friendly, concrete mix.
Biodiesel as a blended fuel in compression ignition engineseSAT Journals
Abstract Fast depletion of fossil fuels, rapid increase in the prices of petroleum products and harmful exhaust emissions from the engine jointly created renewed interest among researchers to find the suitable alternative fuels. The literature survey shows that the yield of Hibiscus Cannabinus seeds per hectare is about 800 kg and oil yield is about 120 liter (15-18 % yield). Its by products are fiber and cake, find wide spread applications. It is found that physical and chemical properties of Hibiscus Cannabinus oil biodiesel are very close to the diesel. The authors have conducted experimental tests on a single cylinder diesel engine using Hibiscus Cannabinus oil biodiesel and diesel blended fuel. The performance parameters like thermal efficiency, brake specific fuel consumption, fuel – air ratio and smoke tests are determined through experimentation. The authors concluded that the Hibiscus Cannabinus oil biodiesel biodiesel could be used as an alternative fuel in the blending form.
Keywords: Blended fuel, Diesel engine, Exhaust emissions, Hibiscus Cannabinus oil biodiesel
Implementation of cyclic convolution based on fnteSAT Journals
Abstract
Cyclic convolution is also known as circular convolution. It is simpler to compute and produce less output samples compared to linear
convolution. There are many architectures for calculating cyclic convolution of any two signals. Implementation using Fermat
Number Transform (FNT) is one of them. Fermat Number is a positive integer of the form where n is a
nonnegative integer.The basic property of FNT is that they are recursive.
This paper presents a cyclic convolution based on Fermat Number Transform(FNT) in the diminished-1 number system.A Code
Convolution method Without Addition(CCWA) and a Butterfly Operation method Without Addition(BOWA) are proposed to perform
the FNT and its inverse(IFNT) except their final stages in the convolution.The pointwise multiplication in the convolution is
accomplished by Modulo 2n+1 Partial Product Multipliers(MPPM) and output partial products which are inputs to the IFNT.Thus
Modulo 2n+1 carry propagation additions are avoided in the FNT and the IFNT except their final stages and Modulo2n+1
multiplier.The execution delay of the parallel architecture is reduced evidently due to the decrease of Modulo 2n+1 carry propagation
addition.compared with the existing cyclic convolution architecture,the proposed one has better throughput performance and involves
less hardware complexity.Synthesis results using 130nm CMOS technology demonstrate the superiority of the proposed architecture
over the reported solution.
Index Terms: FERMAT NUMBER THEORETIC TRANSFORM, BUTTERFLY ARCHITECTURE, PARALLEL
ARCHITECTURE FOR CYCLIC CONVOLUTION, and COMPARISON AND RESULTS
Finite element simulation of hybrid welding process for welding 304 austeniti...eSAT Journals
Abstract Although autogenous laser welding has many advantages over traditional welding methods in many applications, still the process has a main disadvantage of poor gap bridging capability, which limits its applicability for wider industrial use. Owing to this limiting factor, a great deal of research work was carried out to overcome this disadvantage by using Arc source with laser welding. The combination of laser and Arc (MIG/TIG) welding processes in a same process zone is known as Hybrid Welding. This process involves very high peak temperature and rapid change in thermal cycle both of which are difficult to measure in real time. In this dissertation work, a 3- dimensional finite element model was developed for the analysis of hybrid welding process. Ansys Parametric Design language (APDL) code was developed for the same. The FEA results were validated with experimental results showing good agreement. Hybrid welding Simulations were carried out for AISI 304 Austenitic stainless Steel plate. The effects of laser beam power, Arc Welding and torch angle on the weld-bead geometry i.e. penetration (DP), welded zone width (BW) were investigated. The experimental plan was based on three factor 5 level central composite rotatable design. Second order polynomial equations for predicting the weld-bead geometry were developed for bead width and depth of penetration. The results indicate that the effect of arc current (AC) on bead width was more than on depth of penetration. Hence, the proposed models predict the responses adequately within the limits of welding parameters being used. Index Terms: Hybrid Welding, Ansys Parametric Design language (APDL), FEA, AISI 304 Austenitic stainless Steel, and Central composite rotatable design
Seismic performance assessment of the torsional effect in asymmetric structur...eSAT Journals
Abstract In the recent time we come across many structures which are irregular in shape, this type of cannot be avoided due to the functional and architectural requirements. These type of structures have irregular distribution of centre of mass and centre of rigidity which causes the torsional effect on the structures which is one of the most important factor influencing the seismic damage of the structure. Structures with asymmetric distribution of mass and rigidity undergoes torsional motions during earthquake. To assess the torsional effect on the structures in the present study four types of structures are considered with varying eccentricity subjected to Pushover Analysis and Non-Linear Time History Analysis. The performance of the structures are assessed as per the procedure prescribe in ATC-40 and FEMA-356. The analysis of the structural models is done in ETABS. The results have shown that the structures with less eccentricity and in the direction of the columns orientation are performing well, also ductility, drift, and lateral displacement depends on the eccentricity of the structures. Key Words: Symmetric Structure, Asymmetric Structure, Pushover Analysis, Non-Linear Time History Analysis.
Oscillatory motion control of hinged body using controllereSAT Journals
Abstract Due to technological revolution , there is change in daily life usuage of instrument & equipment.These usuage may be either for leisure or necessary and compulsory for life to live. In past there is necessity of a person to help other person but today`s fast life has restricted this helpful nature of human. This my project will helpful eliminate such necessity in certain cases. Oscillatory motion is very common everywhere. But its control is not upto now deviced tactfully. So it is tried to automate it keeping mind constraints such as cost, power consumption, safety,portability and ease of operating. Proper amalgamation of hardware and software make project flexible and stuff. The repetitive , monotonous and continuous operation is made simple by use of PIC microcontroller. There does not existing prototype or research paper on this subject. It probable first in it type.
An understanding of graphical perceptioneSAT Journals
Abstract Graphics was a two dimensional notion till the nineteenth century. It was only in the twentieth century, during the modern movement, that graphics emerged as a three dimensional tool. During the same time architecture also had a change in its definition and there was a breakthrough in the design industry. Colour which was earlier used as a superficial element for decoration now, started being used as a design element of third dimension in architecture. Designing with colour therefore it must be considered in all its aspects of which are related to one another, so that virtually in any work in which colour plays a role all must be taken into accent. Colours have a profound effect on mind and emotion and influence our mood and feelings. Colour can reinforce ideas of form and material; express its divisions and proportions. Colour can underline an architectural statement, it can punctuate, direct and focus attention and compensate in a way unlike any other abstract element”. How graphical use of colour can create a statement in architecture.
Effect of differential settlement on frame forces a parametric studyeSAT Journals
Abstract It has been well established that packed bed solar collectors perform better as compared to conventional collectors. Results of performance studies on packed bed solar collector are available in literature in which different operating conditions have been considered which make it difficult to compare their performance accurately. Considering this comparative study of performance of solar collector with different packing elements has been made in the present work. Experimental investigations on solar collector packed with iron chips, wire mesh, gravels and glass balls for the same set of operating parameter have been done on a single setup to study the effect of packing material and its geometry on the thermal efficiency of packed bed collector. It is observed that iron chips packed collector is identified as the best packing materials out of the materials selected for study leading to thermal efficiency of 76.21% for the mass flow rate of 0.035 kg/s and porosity of 0.945, which is 69.58% higher as compared to smooth collector. Thermal efficiency of wire mesh packed collector for similar operating conditions is found to be 74.26% which is 65.24% higher than smooth collector. In low porosity range gravel packed collector is found to perform better as compared to glass ball packing. Effect of mass flow rate on the effective efficiency has also been conducted for various packing elements used in the present study. Based on the experimental results, plots have been drawn for efficiency against temperature rise parameters for different packing elements which can be used by the designer for choosing the correct value of mass flow rate for the specific temperature rise application. Key Words: Solar Collector, Iron Chips, Wire Mesh, Gravels, Glass Balls, Packed Bed.
Critical analysis of radar data signal de noising by implementation of haar w...eSAT Journals
Abstract Data signal de-noising is a crucial part of every transaction which involves capturing waves and processing them into understandable format. Most essentially, this process of data signal de-noising is important in the field of military and defence. Because of the rapid development in military communication systems, a limitation arises in the systems. The limitation being - quantity of signals profoundly increases along with noise and other disturbances’ presence in the signal. In order to overcome this drawback, batch de-noising techniques are implemented on the systems to produce clean signals. In this paper, the critical analysis case of RADAR [RAdio Detection And Ranging] data de-noising by implementation of Haar Wavelet Transformation is considered. A signal set simulation containing four signals procured from RADAR data is taken into consideration. The signals are then subjected to de-noising in MATLAB and indigenously developed python tool using Haar Wavelet Transformations. The ensuing results pertaining to accuracy and efficiency of output signals are then compared. Keywords: RADAR data, MATLAB tool, Python, De-noising techniques, Haar Wavelet Transformation, Signal Simulation.
Survey on cloud computing security techniqueseSAT Journals
Abstract Cloud computing is one of the emerging technology in computer science field. It provides various services and resources, still enterprises are disinclined to invest their business in cloud computing. It is because of security issues it has. There are different service models in cloud computing and threats to security also have different. The characteristics that are must be ensured while thinking about data security in cloud computing are integrity, availability and confidentiality. In this paper we are surveying some of the Intrusion Detection and Prevention Systems (IDPS) and comparing them regarding their ability to provide data security. Keywords— Cloud Security, cloud computing, data security, IDPS
Harmonized scheme for data mining technique to progress decision support syst...eSAT Journals
Abstract Decision Support System (DSS) is equivalent synonym as management information systems (MIS). Decision supporting systems include also decisions made upon individual data from external sources, management feeling, and various other data sources not included in business intelligence. They serve as an integrated repository for internal and external data-intelligence critical to understanding and evaluating the business within its environmental context. Data mining have emerged to meet this need. With the addition of models, analytic tools, and user interfaces, they have the potential to provide actionable information that supports effective problem and opportunity identification, critical decision-making, and strategy formulation, implementation, and evaluation. The proposed system will support top level management to make a good decision in any time under any uncertain environment. Keywords: Dss, Dm, Mis, Clustering, Classification, Association Rule, K-Mean, Olap, Matlab
Performance evaluation and emission analysis of 4 s, i.c. engine using ethan...eSAT Journals
Abstract Environment air pollution and global warming are alarming concern worldwide. Increasing air pollution, rapid growth of industrialization and the global trend of urbanization have totally disturbed the eco balance of resources on earth. The present study was done to visualize the potential of ethanol and biodiesel as an alternative fuel in C.I. engine. The salient features of the investigation include: (i) The study of basic fuel properties of ethanol, biodiesel and their blends with diesel for C.I. engine. (ii) To evaluate the potential of using biodiesel, ethanol and their blends with diesel for C.I, engine. (iii) Study of the engine performance and exhaust emission characteristics for various blends. Experiment set up was developed to carryout engine performance and emission characteristic studies on selected fuel blends at different load conditions. The present work has resulted in giving a good insight into the performance and emission characteristics of the C.I. engine using ethanol, biodiesel, diesel fuel blends. As fuel property point of view density and pour point of all the fuel blends are under the standard limits for diesel fuel. Heat of combustion of all blends is found to be lower than that of diesel fuel alone. D70B20E10 give lower CO and HC emission and slightly higher thermal efficiency than other blends Keywords: Heat exchanger, Flow induced vibration, TEMA, HTRI
A study on modelling and simulation of photovoltaic cellseSAT Journals
Abstract This Paper presents a detailed study on the types of modelling of the PV Panel for simulation studies. The main concern of this study is to analyze the results and compare them under standard test conditions. PV systems are generally integrated with specific control algorithms in order to extract the maximum possible power. Hence it is highly imperative that the Maximum Power Point (MPP) is achieved effectively and thus we need to design a model from which the MPPT algorithm can be realized in an efficient way. Also other parameters should be taken into account for finding the best model for the use in simulation. It is very important to choose the appropriate model based on the application. The models used for study in this paper include the single diode model, two diode model and Simscape modelling. MATLAB/Simulink presents a powerful tool to study such systems. The work tests the accuracy of the models under different temperature and irradiance conditions. The two diode model is known to have better accuracy at low irradiance levels which allows for a more accurate prediction of PV system performance. Simscape, part of Simulink environment, has a solar cell block that makes building a PV model straightforward and much easier programming with full demonstration to all system details. On the basis of the study, the best model that can be used for simulation purposes can be selected. It is envisaged that the work can be very useful for professionals who require simple and accurate PV simulators for their design. All the systems here are modeled and simulated in MATLAB/Simulink environment. Keywords: PV cell, STC, MATLAB Simulink, Ideality Factor
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Design of area and power efficient half adder using transmission gateeSAT Journals
Abstract This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors. Keywords: Transmission gate (TG), Half adder, CMOS logic gates, Surface area, Power.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low power test pattern generation for bist applicationseSAT Journals
Abstract This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length. Keywords—Built-in self-test (BIST), low power, single-input change (SIC), test pattern generator (TPG)
Optimum capacity allocation of distributed generation units using parallel ps...eSAT Journals
Abstract This paper proposes the application of Parallel Particle Swarm Optimization (PPSO) technique to find the optimal sizing of multiple DG(Distributed Generation) units in the radial distribution network by reduction in real power losses and enhancement in voltage profile. Message passing interface (MPI) is used for the parallelization of PSO. The initial population of PSO algorithm has been divided between the processors at run time. The proposed technique is tested on standard 123-bus test system and the obtained results show that the simulation time is significantly reduced and is concluded that parallelization helps in enhancing the performance of basic PSO. The procedure has been implemented in an environment in which OpenDSS (Open Distribution System Simulator) is driven from MATLAB. An adaptive weight particle swarm optimization algorithm has been developed in MATLAB , parallelization is achieved using MATLABMPI and the unbalanced three-phase distribution load flow (DLF) has been performed using Electric Power Research Institute’s (EPRI) open source tool OpenDSS. Index Terms: Distributed Generation, Message Passing Interface, Optimal Placement, Parallel Particle Swarm Optimisation
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A REVIEW OF LOW POWERAND AREA EFFICIENT FSM BASED LFSR FOR LOGIC BISTjedt_journal
Built in Self Test circuits enable an integrated circuit to test itself. Built in Self Test reduces test and maintenance costs for an integrated circuit by eliminating the need for expensive test equipment. Built in Self Test also allows an integrated circuit to test at its normal operating speed which is very important for detecting timing faults. Despite all of these advantages Built in Self Test has seen limited use in industry because of area and performance overhead and increased design time. This paper presents automated techniques for implementing BIST in a way that minimizes area and performance overhead. This approach allows applying at-speed test patterns and eliminates the need for an external tester. Proper design of the test pattern generator contributes to reduction in the power consumption of the CUT and the overall power consumption of the BIST circuitry. We have proposed FSM based LFSR which generate maximum correlation among the patterns and targeted on c432, c1908 and c3540 benchmark circuits to validate test power, achieved significant improved in power up to 15% compared to conventional test generator and also achieved optimal area overhead,designed using Verilog HDL and implemented using Xilinx 14.3 and Cadence tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design and testing of systolic array multiplier using fault injecting schemesCSITiaesprime
Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.
Explicit model predictive control of fast dynamic systemeSAT Journals
Abstract Explicit Model Predictive Control approach provides offline computation of the optimization law by Multi Parametric Quadratic Programming. The solution is Piece wise affine in nature. It is explicit representation of the system states and control inputs. Such law then can be solved using binary search tree and can be evaluated for fast dynamic systems. Implementing such controllers can be done on microcontroller or ASIC/FPGA. DC Motor Speed Control - one of the benchmark systems is discussed here in this context. Its PWA law obtained, simulation of closed loop e-MPC is presented and its implementation approach using MPT toolbox and other such toolboxes is shown in brief. Index Terms: Model Predictive Control, explicit, Piece-wise Affine, and Multi Parametric Toolbox
An efficient hardware logarithm generator with modified quasi-symmetrical app...IJECEIAES
This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Two innovative high-speed low power parallel 8-bit counter architectures are proposed. Then, High speed 8-bit frequency divider circuits using the proposed architectures are realized. The proposed parallel counter architectures consist of two sections – The Counting Path and the State Excitation Module. The counting path consists of three counting modules in which the first module (basic module) generates future states for the two remaining counting modules. The State Excitation Module decodes the count states of the basic module and carries this decoding over clock cycles through pipelined DFF to trigger the subsequent counting modules. The existing 8-bit parallel counter architecture [1] consumed a total transistor count of 442 whereas the proposed parallel counters consumed only 274 transistors. The power dissipation of the existing parallel counter architecture and the proposed parallel counter architecture were 4.21mW (PINT) and 3.60mW (PINT) respectively at 250MHz. The worst case delay observed for the 8-bit counter using existing parallel counter architecture [1] and the proposed parallel counter architectures were 7.481ns, 6.737ns and 6.677ns respectively using Altera Quartus II. A reduction in area (transistor count) by 27.45% and a reduction in power dissipation by 16.28% are achieved for the frequency dividers using proposed counter architectures. Also a reduction in delay by 10.75% and 7.62% is achieved for the 8-bit frequency divider circuits using proposed counter methods I & II respectively.
Parallel Processing Technique for Time Efficient Matrix MultiplicationIJERA Editor
In this paper, we have proposed one designs for parallel-parallel input and single output (PPI-SO) matrix-matrix multiplication. In this design differs by high speed area efficient, throughput rate and user defined input format to match application needs. We have compared the proposed designs with the existing similar design and found that, the proposed designs offer higher throughput rate, reduce area at relatively lower hardware cost. We have synthesized the proposed design and the existing design using Xilinx software. Synthesis results shows that proposed design on average consumes nearly 30% less energy than the existing design and involves nearly 70% less area-delay-product than other. Interestingly, the proposed parallel-parallel input and single output (PPI-SO) structure consumes 40% less energy than the existing structure.
In this paper, we propose a new technique for implementing a low power high speed multiplier based on Sleepy Stack Technique and consisting of
minimum number of transistors. Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). An 4 bit x 4 bit
multiplier has also been implemented using the design of only using basic combinational circuits and its performance has been analyzed and
compared with similar multipliers designed with peer combinational design available in literature. The explored method of implementation achieves
a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional
CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
Similar to Implementation of low power divider techniques using radix (20)
Mechanical properties of hybrid fiber reinforced concrete for pavementseSAT Journals
Abstract
The effect of addition of mono fibers and hybrid fibers on the mechanical properties of concrete mixture is studied in the present
investigation. Steel fibers of 1% and polypropylene fibers 0.036% were added individually to the concrete mixture as mono fibers and
then they were added together to form a hybrid fiber reinforced concrete. Mechanical properties such as compressive, split tensile and
flexural strength were determined. The results show that hybrid fibers improve the compressive strength marginally as compared to
mono fibers. Whereas, hybridization improves split tensile strength and flexural strength noticeably.
Keywords:-Hybridization, mono fibers, steel fiber, polypropylene fiber, Improvement in mechanical properties.
Material management in construction – a case studyeSAT Journals
Abstract
The objective of the present study is to understand about all the problems occurring in the company because of improper application
of material management. In construction project operation, often there is a project cost variance in terms of the material, equipments,
manpower, subcontractor, overhead cost, and general condition. Material is the main component in construction projects. Therefore,
if the material management is not properly managed it will create a project cost variance. Project cost can be controlled by taking
corrective actions towards the cost variance. Therefore a methodology is used to diagnose and evaluate the procurement process
involved in material management and launch a continuous improvement was developed and applied. A thorough study was carried
out along with study of cases, surveys and interviews to professionals involved in this area. As a result, a methodology for diagnosis
and improvement was proposed and tested in selected projects. The results obtained show that the main problem of procurement is
related to schedule delays and lack of specified quality for the project. To prevent this situation it is often necessary to dedicate
important resources like money, personnel, time, etc. To monitor and control the process. A great potential for improvement was
detected if state of the art technologies such as, electronic mail, electronic data interchange (EDI), and analysis were applied to the
procurement process. These helped to eliminate the root causes for many types of problems that were detected.
Managing drought short term strategies in semi arid regions a case studyeSAT Journals
Abstract
Drought management needs multidisciplinary action. Interdisciplinary efforts among the experts in various fields of the droughts
prone areas are helpful to achieve tangible and permanent solution for this recurring problem. The Gulbarga district having the total
area around 16, 240 sq.km, and accounts 8.45 per cent of the Karnataka state area. The district has been situated with latitude 17º 19'
60" North and longitude of 76 º 49' 60" east. The district is situated entirely on the Deccan plateau positioned at a height of 300 to
750 m above MSL. Sub-tropical, semi-arid type is one among the drought prone districts of Karnataka State. The drought
management is very important for a district like Gulbarga. In this paper various short term strategies are discussed to mitigate the
drought condition in the district.
Keywords: Drought, South-West monsoon, Semi-Arid, Rainfall, Strategies etc.
Life cycle cost analysis of overlay for an urban road in bangaloreeSAT Journals
Abstract
Pavements are subjected to severe condition of stresses and weathering effects from the day they are constructed and opened to traffic
mainly due to its fatigue behavior and environmental effects. Therefore, pavement rehabilitation is one of the most important
components of entire road systems. This paper highlights the design of concrete pavement with added mono fibers like polypropylene,
steel and hybrid fibres for a widened portion of existing concrete pavement and various overlay alternatives for an existing
bituminous pavement in an urban road in Bangalore. Along with this, Life cycle cost analyses at these sections are done by Net
Present Value (NPV) method to identify the most feasible option. The results show that though the initial cost of construction of
concrete overlay is high, over a period of time it prove to be better than the bituminous overlay considering the whole life cycle cost.
The economic analysis also indicates that, out of the three fibre options, hybrid reinforced concrete would be economical without
compromising the performance of the pavement.
Keywords: - Fatigue, Life cycle cost analysis, Net Present Value method, Overlay, Rehabilitation
Laboratory studies of dense bituminous mixes ii with reclaimed asphalt materialseSAT Journals
Abstract
The issue of growing demand on our nation’s roadways over that past couple of decades, decreasing budgetary funds, and the need to
provide a safe, efficient, and cost effective roadway system has led to a dramatic increase in the need to rehabilitate our existing
pavements and the issue of building sustainable road infrastructure in India. With these emergency of the mentioned needs and this
are today’s burning issue and has become the purpose of the study.
In the present study, the samples of existing bituminous layer materials were collected from NH-48(Devahalli to Hassan) site.The
mixtures were designed by Marshall Method as per Asphalt institute (MS-II) at 20% and 30% Reclaimed Asphalt Pavement (RAP).
RAP material was blended with virgin aggregate such that all specimens tested for the, Dense Bituminous Macadam-II (DBM-II)
gradation as per Ministry of Roads, Transport, and Highways (MoRT&H) and cost analysis were carried out to know the economics.
Laboratory results and analysis showed the use of recycled materials showed significant variability in Marshall Stability, and the
variability increased with the increase in RAP content. The saving can be realized from utilization of recycled materials as per the
methodology, the reduction in the total cost is 19%, 30%, comparing with the virgin mixes.
Keywords: Reclaimed Asphalt Pavement, Marshall Stability, MS-II, Dense Bituminous Macadam-II
Laboratory investigation of expansive soil stabilized with natural inorganic ...eSAT Journals
Abstract
Soil stabilization has proven to be one of the oldest techniques to improve the soil properties. Literature review conducted revealed
that uses of natural inorganic stabilizers are found to be one of the best options for soil stabilization. In this regard an attempt has
been made to evaluate the influence of RBI-81 stabilizer on properties of black cotton soil through laboratory investigations. Black
cotton soil with varying percentages of RBI-81 viz., 0, 0.5, 1, 1.5, 2, and 2.5 percent were studied for moisture density relationships
and strength behaviour of soils. Also the effect of curing period was evaluated as literature review clearly emphasized the strength
gain of soils stabilized with RBI-81 over a period of time. The results obtained shows that the unconfined compressive strength of
specimens treated with RBI-81 increased approximately by 250% for a curing period of 28 days as compared to virgin soil. Further
the CBR value improved approximately by 400%. The studies indicated an increasing trend for soil strength behaviour with
increasing percentage of RBI-81 suggesting its potential applications in soil stabilization.
Influence of reinforcement on the behavior of hollow concrete block masonry p...eSAT Journals
Abstract
Reinforced masonry was developed to exploit the strength potential of masonry and to solve its lack of tensile strength. Experimental
and analytical studies have been carried out to investigate the effect of reinforcement on the behavior of hollow concrete block
masonry prisms under compression and to predict ultimate failure compressive strength. In the numerical program, three dimensional
non-linear finite elements (FE) model based on the micro-modeling approach is developed for both unreinforced and reinforced
masonry prisms using ANSYS (14.5). The proposed FE model uses multi-linear stress-strain relationships to model the non-linear
behavior of hollow concrete block, mortar, and grout. Willam-Warnke’s five parameter failure theory has been adopted to model the
failure of masonry materials. The comparison of the numerical and experimental results indicates that the FE models can successfully
capture the highly nonlinear behavior of the physical specimens and accurately predict their strength and failure mechanisms.
Keywords: Structural masonry, Hollow concrete block prism, grout, Compression failure, Finite element method,
Numerical modeling.
Influence of compaction energy on soil stabilized with chemical stabilizereSAT Journals
Abstract
Increase in traffic along with heavier magnitude of wheel loads cause rapid deterioration in pavements. There is a need to improve
density, strength of soil subgrade and other pavement layers. In this study an attempt is made to improve the properties of locally
available loamy soil using twin approaches viz., i) increasing the compaction of soil and ii) treating the soil with chemical stabilizer.
Laboratory studies are carried out on both untreated and treated soil samples compacted by different compaction efforts. Studies
show that increase in compaction effort results in increase in density of soil. However in soil treated with chemical stabilizer, rate of
increase in density is not significant. The soil treated with chemical stabilizer exhibits improvement in both strength and performance
properties.
Keywords: compaction, density, subgradestabilization, resilient modulus
Geographical information system (gis) for water resources managementeSAT Journals
Abstract
Water resources projects are inherited with overlapping and at times conflicting objectives. These projects are often of varied sizes
ranging from major projects with command areas of millions of hectares to very small projects implemented at the local level. Thus,
in all these projects there is seldom proper coordination which is essential for ensuring collective sustainability.
Integrated watershed development and management is the accepted answer but in turn requires a comprehensive framework that can
enable planning process involving all the stakeholders at different levels and scales is compulsory. Such a unified hydrological
framework is essential to evaluate the cause and effect of all the proposed actions within the drainage basins.
The present paper describes a hydrological framework developed in the form of a Hydrologic Information System (HIS) which is
intended to meet the specific information needs of the various line departments of a typical State connected with water related aspects.
The HIS consist of a hydrologic information database coupled with tools for collating primary and secondary data and tools for
analyzing and visualizing the data and information. The HIS also incorporates hydrological model base for indirect assessment of
various entities of water balance in space and time. The framework would be maintained and updated to reflect fully the most
accurate ground truth data and the infrastructure requirements for planning and management.
Keywords: Hydrological Information System (HIS); WebGIS; Data Model; Web Mapping Services
Forest type mapping of bidar forest division, karnataka using geoinformatics ...eSAT Journals
Abstract
The study demonstrate the potentiality of satellite remote sensing technique for the generation of baseline information on forest types
including tree plantation details in Bidar forest division, Karnataka covering an area of 5814.60Sq.Kms. The Total Area of Bidar
forest division is 5814Sq.Kms analysis of the satellite data in the study area reveals that about 84% of the total area is Covered by
crop land, 1.778% of the area is covered by dry deciduous forest, 1.38 % of mixed plantation, which is very threatening to the
environmental stability of the forest, future plantation site has been mapped. With the use of latest Geo-informatics technology proper
and exact condition of the trees can be observed and necessary precautions can be taken for future plantation works in an appropriate
manner
Keywords:-RS, GIS, GPS, Forest Type, Tree Plantation
Factors influencing compressive strength of geopolymer concreteeSAT Journals
Abstract
To study effects of several factors on the properties of fly ash based geopolymer concrete on the compressive strength and also the
cost comparison with the normal concrete. The test variables were molarities of sodium hydroxide(NaOH) 8M,14M and 16M, ratio of
NaOH to sodium silicate (Na2SiO3) 1, 1.5, 2 and 2.5, alkaline liquid to fly ash ratio 0.35 and 0.40 and replacement of water in
Na2SiO3 solution by 10%, 20% and 30% were used in the present study. The test results indicated that the highest compressive
strength 54 MPa was observed for 16M of NaOH, ratio of NaOH to Na2SiO3 2.5 and alkaline liquid to fly ash ratio of 0.35. Lowest
compressive strength of 27 MPa was observed for 8M of NaOH, ratio of NaOH to Na2SiO3 is 1 and alkaline liquid to fly ash ratio of
0.40. Alkaline liquid to fly ash ratio of 0.35, water replacement of 10% and 30% for 8 and 16 molarity of NaOH and has resulted in
compressive strength of 36 MPa and 20 MPa respectively. Superplasticiser dosage of 2 % by weight of fly ash has given higher
strength in all cases.
Keywords: compressive strength, alkaline liquid, fly ash
Experimental investigation on circular hollow steel columns in filled with li...eSAT Journals
Abstract
Composite Circular hollow Steel tubes with and without GFRP infill for three different grades of Light weight concrete are tested for
ultimate load capacity and axial shortening , under Cyclic loading. Steel tubes are compared for different lengths, cross sections and
thickness. Specimens were tested separately after adopting Taguchi’s L9 (Latin Squares) Orthogonal array in order to save the initial
experimental cost on number of specimens and experimental duration. Analysis was carried out using ANN (Artificial Neural
Network) technique with the assistance of Mini Tab- a statistical soft tool. Comparison for predicted, experimental & ANN output is
obtained from linear regression plots. From this research study, it can be concluded that *Cross sectional area of steel tube has most
significant effect on ultimate load carrying capacity, *as length of steel tube increased- load carrying capacity decreased & *ANN
modeling predicted acceptable results. Thus ANN tool can be utilized for predicting ultimate load carrying capacity for composite
columns.
Keywords: Light weight concrete, GFRP, Artificial Neural Network, Linear Regression, Back propagation, orthogonal
Array, Latin Squares
Experimental behavior of circular hsscfrc filled steel tubular columns under ...eSAT Journals
Abstract
This paper presents an outlook on experimental behavior and a comparison with predicted formula on the behaviour of circular
concentrically loaded self-consolidating fibre reinforced concrete filled steel tube columns (HSSCFRC). Forty-five specimens were
tested. The main parameters varied in the tests are: (1) percentage of fiber (2) tube diameter or width to wall thickness ratio (D/t
from 15 to 25) (3) L/d ratio from 2.97 to 7.04 the results from these predictions were compared with the experimental data. The
experimental results) were also validated in this study.
Keywords: Self-compacting concrete; Concrete-filled steel tube; axial load behavior; Ultimate capacity.
Evaluation of punching shear in flat slabseSAT Journals
Abstract
Flat-slab construction has been widely used in construction today because of many advantages that it offers. The basic philosophy in
the design of flat slab is to consider only gravity forces; this method ignores the effect of punching shear due to unbalanced moments
at the slab column junction which is critical. An attempt has been made to generate generalized design sheets which accounts both
punching shear due to gravity loads and unbalanced moments for cases (a) interior column; (b) edge column (bending perpendicular
to shorter edge); (c) edge column (bending parallel to shorter edge); (d) corner column. These design sheets are prepared as per
codal provisions of IS 456-2000. These design sheets will be helpful in calculating the shear reinforcement to be provided at the
critical section which is ignored in many design offices. Apart from its usefulness in evaluating punching shear and the necessary
shear reinforcement, the design sheets developed will enable the designer to fix the depth of flat slab during the initial phase of the
design.
Keywords: Flat slabs, punching shear, unbalanced moment.
Evaluation of performance of intake tower dam for recent earthquake in indiaeSAT Journals
Abstract
Intake towers are typically tall, hollow, reinforced concrete structures and form entrance to reservoir outlet works. A parametric
study on dynamic behavior of circular cylindrical towers can be carried out to study the effect of depth of submergence, wall thickness
and slenderness ratio, and also effect on tower considering dynamic analysis for time history function of different soil condition and
by Goyal and Chopra accounting interaction effects of added hydrodynamic mass of surrounding and inside water in intake tower of
dam
Key words: Hydrodynamic mass, Depth of submergence, Reservoir, Time history analysis,
Evaluation of operational efficiency of urban road network using travel time ...eSAT Journals
Abstract
Efficiency of the road network system is analyzed by travel time reliability measures. The study overlooks on an important measure of
travel time reliability and prioritizing Tiruchirappalli road network. Traffic volume and travel time were collected using license plate
matching method. Travel time measures were estimated from average travel time and 95th travel time. Effect of non-motorized vehicle
on efficiency of road system was evaluated. Relation between buffer time index and traffic volume was created. Travel time model has
been developed and travel time measure was validated. Then service quality of road sections in network were graded based on
travel time reliability measures.
Keywords: Buffer Time Index (BTI); Average Travel Time (ATT); Travel Time Reliability (TTR); Buffer Time (BT).
Estimation of surface runoff in nallur amanikere watershed using scs cn methodeSAT Journals
Abstract
The development of watershed aims at productive utilization of all the available natural resources in the entire area extending from
ridge line to stream outlet. The per capita availability of land for cultivation has been decreasing over the years. Therefore, water and
the related land resources must be developed, utilized and managed in an integrated and comprehensive manner. Remote sensing and
GIS techniques are being increasingly used for planning, management and development of natural resources. The study area, Nallur
Amanikere watershed geographically lies between 110 38’ and 110 52’ N latitude and 760 30’ and 760 50’ E longitude with an area of
415.68 Sq. km. The thematic layers such as land use/land cover and soil maps were derived from remotely sensed data and overlayed
through ArcGIS software to assign the curve number on polygon wise. The daily rainfall data of six rain gauge stations in and around
the watershed (2001-2011) was used to estimate the daily runoff from the watershed using Soil Conservation Service - Curve Number
(SCS-CN) method. The runoff estimated from the SCS-CN model was then used to know the variation of runoff potential with different
land use/land cover and with different soil conditions.
Keywords: Watershed, Nallur watershed, Surface runoff, Rainfall-Runoff, SCS-CN, Remote Sensing, GIS.
Estimation of morphometric parameters and runoff using rs & gis techniqueseSAT Journals
Abstract
Land and water are the two vital natural resources, the optimal management of these resources with minimum adverse environmental
impact are essential not only for sustainable development but also for human survival. Satellite remote sensing with geographic
information system has a pragmatic approach to map and generate spatial input layers of predicting response behavior and yield of
watershed. Hence, in the present study an attempt has been made to understand the hydrological process of the catchment at the
watershed level by drawing the inferences from moprhometric analysis and runoff. The study area chosen for the present study is
Yagachi catchment situated in Chickamaglur and Hassan district lies geographically at a longitude 75⁰52’08.77”E and
13⁰10’50.77”N latitude. It covers an area of 559.493 Sq.km. Morphometric analysis is carried out to estimate morphometric
parameters at Micro-watershed to understand the hydrological response of the catchment at the Micro-watershed level. Daily runoff
is estimated using USDA SCS curve number model for a period of 10 years from 2001 to 2010. The rainfall runoff relationship of the
study shows there is a positive correlation.
Keywords: morphometric analysis, runoff, remote sensing and GIS, SCS - method
-
Effect of variation of plastic hinge length on the results of non linear anal...eSAT Journals
Abstract The nonlinear Static procedure also well known as pushover analysis is method where in monotonically increasing loads are applied to the structure till the structure is unable to resist any further load. It is a popular tool for seismic performance evaluation of existing and new structures. In literature lot of research has been carried out on conventional pushover analysis and after knowing deficiency efforts have been made to improve it. But actual test results to verify the analytically obtained pushover results are rarely available. It has been found that some amount of variation is always expected to exist in seismic demand prediction of pushover analysis. Initial study is carried out by considering user defined hinge properties and default hinge length. Attempt is being made to assess the variation of pushover analysis results by considering user defined hinge properties and various hinge length formulations available in literature and results compared with experimentally obtained results based on test carried out on a G+2 storied RCC framed structure. For the present study two geometric models viz bare frame and rigid frame model is considered and it is found that the results of pushover analysis are very sensitive to geometric model and hinge length adopted. Keywords: Pushover analysis, Base shear, Displacement, hinge length, moment curvature analysis
Effect of use of recycled materials on indirect tensile strength of asphalt c...eSAT Journals
Abstract
Depletion of natural resources and aggregate quarries for the road construction is a serious problem to procure materials. Hence
recycling or reuse of material is beneficial. On emphasizing development in sustainable construction in the present era, recycling of
asphalt pavements is one of the effective and proven rehabilitation processes. For the laboratory investigations reclaimed asphalt
pavement (RAP) from NH-4 and crumb rubber modified binder (CRMB-55) was used. Foundry waste was used as a replacement to
conventional filler. Laboratory tests were conducted on asphalt concrete mixes with 30, 40, 50, and 60 percent replacement with RAP.
These test results were compared with conventional mixes and asphalt concrete mixes with complete binder extracted RAP
aggregates. Mix design was carried out by Marshall Method. The Marshall Tests indicated highest stability values for asphalt
concrete (AC) mixes with 60% RAP. The optimum binder content (OBC) decreased with increased in RAP in AC mixes. The Indirect
Tensile Strength (ITS) for AC mixes with RAP also was found to be higher when compared to conventional AC mixes at 300C.
Keywords: Reclaimed asphalt pavement, Foundry waste, Recycling, Marshall Stability, Indirect tensile strength.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Planning Of Procurement o different goods and services
Implementation of low power divider techniques using radix
1. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
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Volume: 01 Issue: 03 | Nov-2012, Available @ http://www.ijret.org 496
IMPLEMENTATION OF LOW POWER DIVIDER TECHNIQUES USING
RADIX
Rakesh Jain
Research Scholar M. Tech. VLSI, Mewar University, rk_patni10@yahoo.com
Abstract
This work describes the design of a divder technique Low-power techniques are applied in the design of the unit, and energy-delay
tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not
optimized for energy, without penalizing the latency. In this dividing technique we compare the radix-8 divider is compared with one
obtained by overlapping three radix-2 stages and with a radix-4 divider. Results show that the latency of our divider is similar to that
of the divider with overlapped stages, but the area is smaller. The speed-up of the radix-8 over the radix-4 is about 23.58% and the
energy dissipated to complete a division is almost the same, although the area of the radix-8 is 67.58% larger.
-----------------------------------------------------------------------***-----------------------------------------------------------------------
1. INTRODUCTION
Division is the most complex of the four basic arithmetic
operations and, in general, does not produce an exact answer,
since the dividend is not necessarily a multiple of the divisor.
Therefore, the correct quotient and remainder are usually
obtained through performing a sequence of iterations until the
desired precision is reached. This procedure is called
sequential division and serves as the basic principle for many
practical implementations [1, 3, 4].
This work describes the design of a double-precision radix-8
divider. The unit is designed to reduce the energy dissipation
without penalizing the latency.
The algorithm used is the digit-recurrence division algorithm
described in detail in [3]. Digit-recurrence algorithms retire in
each iteration a fixed number of result bits, determined by the
radix. Higher radices reduce the number of iterations to
complete the operation, but increase the cycle time and the
complexity of the circuit. There are not many implementations
of high-radix dividers, and the purpose of this paper is to
determine the performance and the energy dissipation of a
radix-8 unit. An evaluation of the area and performance of a
radix-8 divider was done in [3] without an actual
implementation. In [4] an algorithm for radix-8 division and
square root with shared hardware is implemented. In [11] the
implementation of a divider with three radix-2 overlapped
stages is presented. In [5] it is commented that stages with
radices larger than four are not convenient because of the
increased complexity of the digit-selection function. We
present here our implementation of a low-power radix-8
divider, compare its performance with the implementation
presented in [11] and evaluate the speed-up and the energy
consumption with respect to a more common radix-4 unit.
Moreover, some energy-delay tradeoffs are considered.
The primary objective of the design is to perform the
operation in the shortest time. Then low-power design
techniques are applied in order to reduce the energy dissipated
in the unit. Area is not minimized, but some energy reduction
techniques reduce the area as well.
The implementation of the divider was done using the
Passport 0.56 m standard-cell library [2]. The structural
model was obtained by both manual design and synthesis of
the functional blocks, and was laid out by using automatic
floor-planning and routing. The latency of the division is
reduced by choosing appropriate parameters in the algorithm
that affect both the critical path and the number of iterations,
2. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
__________________________________________________________________________________________
Volume: 01 Issue: 03 | Nov-2012, Available @ http://www.ijret.org 497
as described in Section 2. Section 3 describes the design for
low-power
In Section 4 the divider is compared with a radix-8 obtained
by overlapping three radix-2 stages, using a scheme similar to
that implemented in the Sun UltraSPARC processor [11], and
with a radix-4 divider [8].
The results show that the energy dissipation in the radix-8 unit
can be reduced by up to 70% with appropriate low-power
design techniques
2.ALGORITHM AND IMPLEMENTATION
The radix-8 division algorithm, described in detail in [3], is
implemented by the residual recurrence
w[j+1] = 8w[j] - qj+1d
j = 0,1……. m
with initial value w[0] = x , where x is the dividend, d the
divisor, and qj+1 the quotient digit at the j-th iteration. Both d
and x are normalized in [0.5, 1). The quotient digit is in
signed-digit representation {-a,…..,-1,0,1, ……, a} with
redundancy factor p = a/7. The residual w[j] is stored in carry-
save representation (wS and wC). The quotient digit is
determined, at each iteration, by the selection function
qi=SEL (ds,y)
where d is d truncated after the-th fractional bit and [y] =
8wS + 8wC truncated after t fractional bits.
The recurrence is implemented with a selection function
(SEL), a multiple generator, a carry-save adder (CSA) and two
registers to store the carry-save representation of the residual.
In order to avoid the implementation of a complicated multiple
generator, the quotient digit is split into two parts qH with
weight 4 and qL with weight 1 (qj = 4qH + qL) and the digit
set of each part is reduced to {-2,-1,0,1,2}. Four signals (M2,
M1, P1, P2) are used to represent these five values in a one-
out-of-four code (zero is coded as (0,0,0,0)). This
representation makes the multiple generator simple.
Since the selection function (SEL) is in the critical path, to
have the minimum latency we have to minimize its delay. We
explored the implementation of three possible values of a: 6,
7, and 10 (the maximum value possible with the above
mentioned representation). Table 1 shows a summary of the
results. The gate-level implementation was obtained by
synthesizing the VHDL description of the selection function
with Compass ASICSynthesizer. This includes both the
assimilation of the carry-save representation of [^y] and the
actual digit-selection function.
Table 1: Summary selection function
From Table 1, we can see that SEL for a = 7 is as fast as for a
= 6, but its area is smaller. Surprisingly, the delay for the over-
redundant case a = 10 is larger. Therefore, the SEL for a = 7 is
chosen, which results in a redundancy factor p = 1.
A first implementation of the divider is shown in Figure 1.
The scheme is completed by a controller (not depicted in the
figure). The conversion block performs the conversion and the
rounding. The quotient is rounded in the last iteration
according to the sign of the final residual and the signal that
detects if it is zero, which are produced by the sign-zero-
detection block (SZD).
To have the divider compliant with IEEE standard for double-
precision (53-bit significand normalized in [1,2)) while
operating with fractional values, 1-bit shifts are performed on
the operands. Moreover, to have a bound residual in the first
iteration (w[0] = x d ), when x�d we shift x one bit to the
right obtaining a fractional quotient. To compute the 53 bits of
the quotient and an additional bit to perform rounding, 54/3 =
18 iterations are required. An additional cycle is required to
load the value x as first residual w[0]. However, for the
proposed architecture and selection function, the simplest way
to accomplish this is to do as follows:
Clear the registers for w (this is done at the end
of the previous division). With the selection
function we have implemented, this produces a
q1 = 1.
Compute w[1] = x - d using the hardware for the
recurrence. This requires a multiplexer, which is
not on the critical path.
For q1 to be 1, we shift the dividend three bits to
the right. As a consequence, it is necessary to
shift the final quotient accordingly,
In conclusion, the load cycle is substituted by an extra
iteration for a total of 20 iterations: 19 to compute the digits
and one for the rounding. Finally, the quotient is normalized in
[1,2) by shifting it four positions to the left. Note that all shifts
are done by wiring and do not affect the latency of the
operation. In the recurrence (w[j]) we need 54 fractional bits
and 2 integer bits: one to hold the sign and the other to avoid
the overflow in the CS-representation (being p = 1).
There are two possible critical paths, one going through qH
and the other through qL. Since the delay of qH is smaller than
that of qL, but the number of adders to traverse is larger, a
good design tries to equalize the delays of both paths. The
resulting critical paths, pre-layout, are
The addition of the delay due to the clock distribution tree and
the interconnection capacitance results in a post-layout critical
path of 10.5 ns.
3. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
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Volume: 01 Issue: 03 | Nov-2012, Available @ http://www.ijret.org 498
Figure 1: Radix-8 divider implementation.
Figure 2: Low-power implementation.
3. LOW POWER IMPLEMENTATION
In this Section we apply techniques for the reduction of the
energy dissipation in the unit of Figure 1. Some of the
techniques applied here are described in [8] for the case of a
radix-4 divider. These are adapted for radix-8 in Sections 3.1-
3.4. In addition, techniques specific to radix-8 are introduced:
Section 3.5 describes the partitioning of the selection function
and Section 3.6 extends the modified convert-and-round
algorithm (refer to [8] for a complete description) to the case p
= 1. Finally, in Section 3.7 an evaluation of the impact of dual
voltage on the low-power implementation is given.
4. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
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Volume: 01 Issue: 03 | Nov-2012, Available @ http://www.ijret.org 499
Figure 2 shows the implementation of the low-power radix-8
divider and Table 2 summarizes the results obtained by
applying the low-power techniques described in Sections 3.1-
3.7. In the Table, entry std refers to the standard
implementation, optimized for speed, and entry l-p is the low-
power implementation. It was not possible to implement dual
voltage with our cell library so that entry d-v is an estimate of
a possible implementation.
3.1. Switching- off not active blocks
The sign-zero-detection block (SZD), which is only used in
the rounding step, is switched off by forcing a constant logic
value at its inputs during the recurrence steps. The reduction is
about 8%.
3.2 Retiming the recurrence
The position of the registers in a sequential system affects the
energy dissipation. Retiming is the transformation that
consists in re-positioning the registers in a sequential circuit
without modifying its external behavior [6].
For the recurrence, the retiming is done by moving the
selection function of Figure 1 from the first part of the cycle to
the last part of the previous cycle (see Figure 3.a and
Figure 3.b). Two new registers (qH and qL) are needed to
store the quotient digit.
By retiming the recurrence we reduce the switching activity in
the multiple generators and in the CSAs, and change the
critical path that is now limited to the eight most-significant
bits. This allows the rest of the bits in the recurrence to be
redesigned for low power.
3.3 Reducing transitions in multiplexer
The multiplexer in Figure 1 is used to select either x in the
first iteration or the residual in the others. The number of
transitions in the mux can be reduced by moving it out of the
recurrence, as shown in Figure 2. Consequently, the operations
in the first cycle are modified by resetting registers qH and qL
to 0 and -1 respectively and by storing x in w[0] = 0 - (-x).
3.4Changing the redundant representation
By using a radix-8 carry-save representation with three sum
bits and one carry bit for each digit in the recurrence, as shown
in Figure 4, we only need to store one carry bit for each digit,
instead of three. This can be done for the 45 LSBs that, after
the retiming, are not on the critical path.
Furthermore, after the retiming, the eight MSBs, assimilated in
the adder inside the selection function block (Figure 2), can be
stored in wS eliminating another eight flip-flops in wC.
Figure 3: Retiming and critical path. a) before retiming, b)
after retiming, c) after retiming and skewing the clock.
Figure 4: Radix-8 carry-save adder (lower).
By retiming, moving the mux, and changing the
representation, the reduction in l-p with respect to std is about
14%.
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Figure 5: partitioned selection function.
3.5 Partitioning and disabling selection function
The quotient-digit selection is a function of three bits of the
divisor and eight of the residual.
In the radix-8 case, Figure 5 shows the partitioning in eight
parts (all the possible values of d3) for both the higher and
lower parts. The demultiplexer transmits the assimilated value
of [^y] to the selected pair of selection tables and forces to
zero the output of the others. Finally, an array of OR gates
combines the partial values.
Experimental results showed that the partitioned selection
function dissipates less energy, but the critical path increased.
The smaller selection functions are faster than the
implementation in one piece, but the delays in the
demultiplexer and the OR gates offset the improvement.
3.6. Modifications in conversion And Rounding
The on-the-fly convert-and-round algorithm [3] performs the
conversion from the signed-digit representation to the
conventional representation in 2's complement. The
conversion is done as the digits are produced and does not
require a carry-propagate adder. The algorithm, in its original
formulation, did not consider the energy dissipation, resulting
in about 30% of the whole divider.
For p = 1, the partial quotient is stored in three registers (Q,
QM, QP) updated in each iteration by shift-and-load
operations, and the final quotient is chosen among those
registers during the rounding. The large amount of energy
dissipated in the unit is mainly due to the shifting during each
iteration and to the number of flip-flops, used to implement
the registers.
As a first step to reduce energy dissipation, we load each digit
in its final position [9]. In this way, we avoid to shift digits
along the registers. To determine the load position we use an
18-bit ring counter C, one bit for each digit to load.
3.7. Using dual voltage
The power dissipated in a cell depends on the square of the
voltage supply (VDD) so that significant amount of energy
can be saved by reducing this voltage [1]. However, by
lowering the voltage the delay increases, so that to maintain
the performance this technique is applied only to cells not in
the critical path. Different power supply voltages require
level-shifting circuitry that dissipate energy. However, by
using two voltages we only need to level-shift when going
from the lower to the higher voltage [13]. In our case, the 45
least-significant bits in the recurrence can be redesigned for
low voltage, as shown in Figure 7. The voltage-level shifters
are not needed until a specific digit moves towards the eleven
MSBs, by shifting across iterations and into the critical path.
By placing the voltage-level shifters (a total of three) in the
digit immediately before the eleven MSBs the cycle time is
not increased and the energy dissipated in the level-shifting
circuitry is small.
We can apply the dual-voltage technique also to the convert-
and-round unit which is not in the critical path. The number of
level-shifters required is 53, as many as the double-precision
significand representation, but because of the new algorithm,
each bit switches at most twice and the energy dissipation in
the level-shifters does not offset the reduction due to the lower
voltage.
We estimated a reduction of about 50% in d-v with respect to
l-p if low-voltage gates were available.
4. COMPARISON WITH RADIX-4
IMPLEMENTATION
To evaluate the tradeoffs between energy and delay, we
compare the radix-8 divider with the radix-4 unit previously
presented in [8]. We chose a radix-4 divider for the
comparison because the algorithm is the same with the only
variation of the radix, and the techniques to reduce the energy
are similar.
The radix-4 divider has the disadvantage of requiring more
cycles to compute the quotient (30 cycles) but the advantage
of a shorter iteration cycle (faster clock) and smaller area.
The performance metric used is the time elapsed per operation
which is tdiv = Tcycle ×(no. of cycles). The energy measure is
the energy per division Ediv and we also include the energy
per cycle Epc. Table 5 summarizes the characteristics of the
two dividers.
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Table 5: Radix-4 vs. radix-8 divider
radix-4 radix-8 [unit]
Tcycle 9.3 11.5 ns
tdiv 260 215 ns
Ediv 26.0 26.6 nJ
Epc 1.9 2.4 nJ
Area 2.2 2.8 mm2
The speed-up for the radix-8 over the radix-4 is about 20%,
while the increase in the energy-per-division is less than 2%.
On the other hand, the radix-8 has an energy-per-cycle which
is 50% larger. Our design shows that the increase of area
(about 50%) does not reflect on the energy dissipated to
complete an operation, which is almost the same because of
the reduction in the number of cycles. The radix-4 divider is
smaller, but it is slower and consumes almost the same amount
of energy per operation.
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