The document proposes a method to determine power-safe test patterns for at-speed scan-based testing to address excessive capture power issues. It involves two main processes: 1) test pattern refinement process which refines existing power-safe patterns to detect faults detected by power-risky patterns while satisfying power constraints, and 2) low-power test pattern regeneration process which generates new power-safe patterns if faults remain undetected after refinement. Experimental results show the method can detect over 75% of power-risky faults through refinement with up to 12.76% reduction in test data volume without loss of fault coverage.