1. The document discusses techniques for minimizing power consumption during scan test activity. It proposes a novel circuit technique to eliminate switching in combinational logic during scan shifting by masking logic inputs. Blocking transistors are added to gate the power supply to first-level gates at flip-flop outputs during scan shifting. 2. A selective trigger scan architecture is proposed that reduces switching between scan cells and test vectors by using NOR gates to compare previous and next test vector values and only applying differences. Scan chain reordering is also used to minimize transitions between flip-flops. 3. Experimental results on ISCAS89 benchmarks show the proposed techniques reduce static power by 6.1-11% and area overhead by 47% compared to