1. The document discusses system calls from the user's perspective, providing a high-level overview of common system call categories like process management, file I/O, and directory management.
2. It explains that system calls provide a controlled entry point for applications to make requests to the operating system kernel to perform privileged operations.
3. Examples of system calls on different platforms like Linux, Windows, and MIPS are provided to illustrate the concept.
The document discusses the ARM architecture, including that it is a 32-bit RISC architecture licensed by ARM Holdings to semiconductor companies, it has both 32-bit and 16-bit instruction sets and operates in different processor modes, and it uses conditional execution and flags to improve code density.
The ARM7TDMI-S processor is a 32-bit RISC microprocessor developed in the 1980s. It uses a 3-stage pipeline to increase processing speed. The pipeline stages are fetch, decode, and execute. The ARM7 has 37 registers, including 31 general-purpose 32-bit registers and status registers. It supports various instruction sets like ARM, Thumb, and Java bytecodes. The ARM architecture emphasizes low power consumption and small size.
This document discusses processor architecture and the ARM processor. It begins with an overview of the von Neumann and Harvard architectures. It then covers the ARM instruction set architecture, including general-purpose register architecture, CISC vs RISC designs, and techniques for exploiting instruction-level parallelism like superscalar and VLIW approaches. The document also discusses the ARM programming model, data types, instruction formats, and conditional execution.
This document provides an overview of four ARM architecture families: ARM7, ARM9, ARM10, and ARM11. It describes the key features and performance improvements of each family over previous generations. The ARM9 introduced a 5-stage pipeline compared to ARM7's 3-stage pipeline, improving clock speed. ARM10 added a branch predictor and separate load/store unit. ARM11 supported SIMD instructions and reduced cache aliasing problems. Each new family optimized the pipeline design and added capabilities to enhance performance and efficiency.
The document describes key aspects of the ARM instruction set architecture, including:
1) Instructions are 32-bits long and most execute in a single cycle. It uses a load/store architecture with separate memory access and data processing instructions.
2) It has several processor modes for handling interrupts and exceptions. Registers are banked between modes to preserve their contents.
3) The instruction set can be extended through coprocessors and includes a compressed 16-bit Thumb instruction set for improved code density.
The document discusses the ARM architecture, including that it is a 32-bit RISC architecture licensed by ARM Holdings to semiconductor companies, it has both 32-bit and 16-bit instruction sets and operates in different processor modes, and it uses conditional execution and flags to improve code density.
The ARM7TDMI-S processor is a 32-bit RISC microprocessor developed in the 1980s. It uses a 3-stage pipeline to increase processing speed. The pipeline stages are fetch, decode, and execute. The ARM7 has 37 registers, including 31 general-purpose 32-bit registers and status registers. It supports various instruction sets like ARM, Thumb, and Java bytecodes. The ARM architecture emphasizes low power consumption and small size.
This document discusses processor architecture and the ARM processor. It begins with an overview of the von Neumann and Harvard architectures. It then covers the ARM instruction set architecture, including general-purpose register architecture, CISC vs RISC designs, and techniques for exploiting instruction-level parallelism like superscalar and VLIW approaches. The document also discusses the ARM programming model, data types, instruction formats, and conditional execution.
This document provides an overview of four ARM architecture families: ARM7, ARM9, ARM10, and ARM11. It describes the key features and performance improvements of each family over previous generations. The ARM9 introduced a 5-stage pipeline compared to ARM7's 3-stage pipeline, improving clock speed. ARM10 added a branch predictor and separate load/store unit. ARM11 supported SIMD instructions and reduced cache aliasing problems. Each new family optimized the pipeline design and added capabilities to enhance performance and efficiency.
The document describes key aspects of the ARM instruction set architecture, including:
1) Instructions are 32-bits long and most execute in a single cycle. It uses a load/store architecture with separate memory access and data processing instructions.
2) It has several processor modes for handling interrupts and exceptions. Registers are banked between modes to preserve their contents.
3) The instruction set can be extended through coprocessors and includes a compressed 16-bit Thumb instruction set for improved code density.
The ARM processor is a 32-bit Reduced Instruction Set Computer (RISC) architecture originally developed in the 1980s at Acorn Computers. It was the first RISC microprocessor developed for commercial use. In 1990, ARM Limited was established to license the ARM architecture to semiconductor manufacturers worldwide. The ARM architecture incorporates features like pipelined execution, single-cycle instructions, load-store architecture, and fixed-length 32-bit instructions. It supports data types, operating modes, registers, instruction sets, and handles exceptions by completing the current instruction before jumping to a specific exception vector location.
AAME ARM Techcon2013 001v02 Architecture and Programmer's modelAnh Dung NGUYEN
The document provides an overview of the ARMv6-M and ARMv7-M architectures and programmer's model. It discusses key aspects including:
- The ARMv7-M programmer's model including registers, modes, exceptions and interrupts.
- ARM Cortex-M microcontrollers which implement the ARMv7-M architecture profile designed for microcontrollers.
- The ARMv7-M instruction set which implements the Thumb instruction set with Thumb-2 technology using a mix of 16-bit and 32-bit instructions.
The ARM architecture overview document describes:
1) The evolution of the ARM architecture from early implementations like ARM7TDMI to modern cores like Cortex-A8.
2) The different profiles of the ARM architecture - application, real-time, and microcontroller - which are optimized for different use cases.
3) Key aspects of the ARM programmer's model including the instruction sets, processor modes, register set, and exception handling behavior.
ARM (Advance RISC Machine) is one of the most licensed and thus widespread processor cores in the world.Used especially in portable devices due to low power consumption and reasonable performance.Several interesting extension available like THUMB instruction set and Jazelle Java Machine.
The document provides an introduction and overview of ARM processors. It discusses the background and architecture of ARM, including that ARM is a RISC processor designed for efficiency. It also describes some key features of ARM including Thumb mode, different memory banks, and specialized instructions. The document then discusses ARM concepts such as the ARM instruction set and assembly language programming.
The document discusses the ARM architecture and interrupt handling. It provides background on ARM and compares RISC and CISC architectures. It describes ARM's instruction sets, data sizes, registers including the program counter and current program status register. It discusses exception handling in ARM, including saving state on exception entry and exit. Interrupts and exceptions are compared to system calls. Memory organization during exceptions is also covered.
The document provides an overview of the ARM Cortex-A8 processor, including its RISC-based superscalar design, 13-stage instruction pipeline, branch prediction features, and NEON SIMD capabilities. The Cortex-A8 achieves high performance while maintaining low power usage. It is widely used in mobile devices and consumer electronics due to its versatility and balance of performance and energy efficiency.
This document summarizes a seminar on ARM architecture presented by Kshitij Gorde. It discusses the history and development of ARM processors, key features of the ARM architecture including the register files and instruction sets. Specific ARM processor families including ARM7, ARM9, ARM10 are described along with their characteristics. The document also covers ARM processor modes, exception handling, and systems that use ARM processors.
The document provides information about the 80386 microprocessor. It includes questions and answers about various features of the 80386.
In 3 sentences:
The document contains questions and answers about the features of the 80386 microprocessor, including its modes of operation, memory management capabilities, flag register format, and differences between .COM and .EXE file types. It also discusses the DOS-BIOS interface, RISC processor features, Pentium system architecture, and virtual 8086 environment memory management. The questions cover technical details about the 80386 to test understanding of its architecture and operation.
This document provides an introduction to the ARM-7 microprocessor architecture. It describes key features of the ARM7TDMI including its 32-bit RISC instruction set, 3-stage pipeline, 37 registers including separate registers for different processor modes, and low power consumption. The document also compares RISC and CISC architectures and summarizes the different versions of the ARM architecture.
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC IEEE SSCS AlexSC
This document provides an overview of ARM architecture, including ARM Cortex-M4 and M3 specifications, and peripherals of the TM4C123GH6PM microcontroller. It discusses the history and development of ARM architecture, from its origins at Acorn Computers to the current licensing model. ARMv7 architecture profiles including A-Profile for application processors, R-Profile for real-time systems, and M-Profile for microcontrollers are also covered. Specific topics to be discussed include GPIO, ADC, interrupts, SPI, I2C, UART, DMA, and timer interfacing.
Arm cm3 architecture_and_programmer_modelGanesh Naik
The document provides an overview of the ARM Cortex-M3 architecture and programmer's model. It discusses the Cortex-M3 register set including general purpose registers, stack pointers, link register, program counter, and special registers. It also covers the Cortex-M3 operation modes of handler mode and thread mode, as well as privileged and user access levels. Finally, it describes exceptions and interrupts handling in Cortex-M3 through vector tables.
ARM is a 32-bit reduced instruction set computing (RISC) architecture developed in 1985. It features a load/store architecture, uniform instruction length, and conditional execution of instructions based on status flags. ARM processors operate in different modes like user, system, and interrupt modes. Newer ARM features include more control over arithmetic logic unit and shifter operations, auto-increment/decrement addressing, and conditional execution of instructions. ARM uses load/store instructions to transfer data between registers and memory.
This document discusses ARM instruction sets. It covers topics like ARM and Thumb instruction sets, assembler syntax, data processing instructions, memory access instructions, branch instructions, and instructions for loading constants. It provides details on different instruction types, their syntax, functionality and examples.
Introduction to Processor Design and ARM ProcessorDarling Jemima
The document discusses computer architecture and the MU0 processor. It provides details on MU0's instruction set, which uses 1-address instructions and has a small set of instructions including LDA, STA, ADD, SUB, JMP, JGE, JNE, and STP. The document also explains MU0's design, which has a program counter, accumulator, instruction register, and arithmetic logic unit. It describes how MU0 executes sample instructions in a step-by-step fashion.
The ARM architecture is a 32-bit load/store RISC architecture. It has 37 32-bit registers including general purpose registers, the program counter, current program status register, and saved program status registers. The ARM supports multiple instruction sets and operating modes. Each mode can access a particular set of registers and the processor mode determines which registers are visible.
This document proposes strategic investments for Kubera Palace in Macau, including Kubera Palace hotel expansion, World Series Speed Baccarat tournament, online gaming platform, and Wynn golf course. It analyzes each opportunity, providing internal and external drivers, required investments, discount rates, NPVs, and ROIs. A finance section evaluates resource requirements and an implementation time table is presented for the Kubera Palace expansion.
This document discusses software-managed translation lookaside buffers (TLBs) and page tables. It begins by describing a virtual linear array approach to page tables that allows indexing directly into the second-level page table without referring to the root page table. It then provides code for a TLB refill handler using this approach. The document discusses trends that increase TLB miss rates and evaluates tradeoffs of software-managed TLBs. It also briefly covers Itanium, P4, and x86 page table structures and segmentation.
The ARM processor is a 32-bit Reduced Instruction Set Computer (RISC) architecture originally developed in the 1980s at Acorn Computers. It was the first RISC microprocessor developed for commercial use. In 1990, ARM Limited was established to license the ARM architecture to semiconductor manufacturers worldwide. The ARM architecture incorporates features like pipelined execution, single-cycle instructions, load-store architecture, and fixed-length 32-bit instructions. It supports data types, operating modes, registers, instruction sets, and handles exceptions by completing the current instruction before jumping to a specific exception vector location.
AAME ARM Techcon2013 001v02 Architecture and Programmer's modelAnh Dung NGUYEN
The document provides an overview of the ARMv6-M and ARMv7-M architectures and programmer's model. It discusses key aspects including:
- The ARMv7-M programmer's model including registers, modes, exceptions and interrupts.
- ARM Cortex-M microcontrollers which implement the ARMv7-M architecture profile designed for microcontrollers.
- The ARMv7-M instruction set which implements the Thumb instruction set with Thumb-2 technology using a mix of 16-bit and 32-bit instructions.
The ARM architecture overview document describes:
1) The evolution of the ARM architecture from early implementations like ARM7TDMI to modern cores like Cortex-A8.
2) The different profiles of the ARM architecture - application, real-time, and microcontroller - which are optimized for different use cases.
3) Key aspects of the ARM programmer's model including the instruction sets, processor modes, register set, and exception handling behavior.
ARM (Advance RISC Machine) is one of the most licensed and thus widespread processor cores in the world.Used especially in portable devices due to low power consumption and reasonable performance.Several interesting extension available like THUMB instruction set and Jazelle Java Machine.
The document provides an introduction and overview of ARM processors. It discusses the background and architecture of ARM, including that ARM is a RISC processor designed for efficiency. It also describes some key features of ARM including Thumb mode, different memory banks, and specialized instructions. The document then discusses ARM concepts such as the ARM instruction set and assembly language programming.
The document discusses the ARM architecture and interrupt handling. It provides background on ARM and compares RISC and CISC architectures. It describes ARM's instruction sets, data sizes, registers including the program counter and current program status register. It discusses exception handling in ARM, including saving state on exception entry and exit. Interrupts and exceptions are compared to system calls. Memory organization during exceptions is also covered.
The document provides an overview of the ARM Cortex-A8 processor, including its RISC-based superscalar design, 13-stage instruction pipeline, branch prediction features, and NEON SIMD capabilities. The Cortex-A8 achieves high performance while maintaining low power usage. It is widely used in mobile devices and consumer electronics due to its versatility and balance of performance and energy efficiency.
This document summarizes a seminar on ARM architecture presented by Kshitij Gorde. It discusses the history and development of ARM processors, key features of the ARM architecture including the register files and instruction sets. Specific ARM processor families including ARM7, ARM9, ARM10 are described along with their characteristics. The document also covers ARM processor modes, exception handling, and systems that use ARM processors.
The document provides information about the 80386 microprocessor. It includes questions and answers about various features of the 80386.
In 3 sentences:
The document contains questions and answers about the features of the 80386 microprocessor, including its modes of operation, memory management capabilities, flag register format, and differences between .COM and .EXE file types. It also discusses the DOS-BIOS interface, RISC processor features, Pentium system architecture, and virtual 8086 environment memory management. The questions cover technical details about the 80386 to test understanding of its architecture and operation.
This document provides an introduction to the ARM-7 microprocessor architecture. It describes key features of the ARM7TDMI including its 32-bit RISC instruction set, 3-stage pipeline, 37 registers including separate registers for different processor modes, and low power consumption. The document also compares RISC and CISC architectures and summarizes the different versions of the ARM architecture.
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC IEEE SSCS AlexSC
This document provides an overview of ARM architecture, including ARM Cortex-M4 and M3 specifications, and peripherals of the TM4C123GH6PM microcontroller. It discusses the history and development of ARM architecture, from its origins at Acorn Computers to the current licensing model. ARMv7 architecture profiles including A-Profile for application processors, R-Profile for real-time systems, and M-Profile for microcontrollers are also covered. Specific topics to be discussed include GPIO, ADC, interrupts, SPI, I2C, UART, DMA, and timer interfacing.
Arm cm3 architecture_and_programmer_modelGanesh Naik
The document provides an overview of the ARM Cortex-M3 architecture and programmer's model. It discusses the Cortex-M3 register set including general purpose registers, stack pointers, link register, program counter, and special registers. It also covers the Cortex-M3 operation modes of handler mode and thread mode, as well as privileged and user access levels. Finally, it describes exceptions and interrupts handling in Cortex-M3 through vector tables.
ARM is a 32-bit reduced instruction set computing (RISC) architecture developed in 1985. It features a load/store architecture, uniform instruction length, and conditional execution of instructions based on status flags. ARM processors operate in different modes like user, system, and interrupt modes. Newer ARM features include more control over arithmetic logic unit and shifter operations, auto-increment/decrement addressing, and conditional execution of instructions. ARM uses load/store instructions to transfer data between registers and memory.
This document discusses ARM instruction sets. It covers topics like ARM and Thumb instruction sets, assembler syntax, data processing instructions, memory access instructions, branch instructions, and instructions for loading constants. It provides details on different instruction types, their syntax, functionality and examples.
Introduction to Processor Design and ARM ProcessorDarling Jemima
The document discusses computer architecture and the MU0 processor. It provides details on MU0's instruction set, which uses 1-address instructions and has a small set of instructions including LDA, STA, ADD, SUB, JMP, JGE, JNE, and STP. The document also explains MU0's design, which has a program counter, accumulator, instruction register, and arithmetic logic unit. It describes how MU0 executes sample instructions in a step-by-step fashion.
The ARM architecture is a 32-bit load/store RISC architecture. It has 37 32-bit registers including general purpose registers, the program counter, current program status register, and saved program status registers. The ARM supports multiple instruction sets and operating modes. Each mode can access a particular set of registers and the processor mode determines which registers are visible.
This document proposes strategic investments for Kubera Palace in Macau, including Kubera Palace hotel expansion, World Series Speed Baccarat tournament, online gaming platform, and Wynn golf course. It analyzes each opportunity, providing internal and external drivers, required investments, discount rates, NPVs, and ROIs. A finance section evaluates resource requirements and an implementation time table is presented for the Kubera Palace expansion.
This document discusses software-managed translation lookaside buffers (TLBs) and page tables. It begins by describing a virtual linear array approach to page tables that allows indexing directly into the second-level page table without referring to the root page table. It then provides code for a TLB refill handler using this approach. The document discusses trends that increase TLB miss rates and evaluates tradeoffs of software-managed TLBs. It also briefly covers Itanium, P4, and x86 page table structures and segmentation.
The document introduces TVI Express, an international direct selling company offering a travel and earn opportunity. It describes TVI's products including free vacations and flights, discounts on travel deals, and a global business opportunity. Becoming a TVI distributor for $250 provides these travel benefits as well as tools to build a business and earn thousands of dollars weekly by sharing the opportunity with others.
April 2011, Quito: Presentation about how ICT systems on different levels (ministry, teacher college, school) could be used and implemented in higher education in Ecuador. Presented at an internal workshop at SENESCYT, the ministry of higher education of Ecuador. Presentation is in Spanish...
Yudie Y. Kartawijaya lives in Garut, West Java, Indonesia. He has a degree in Food and Beverage Management from the National Hotel Institute and is a Certified Food & Beverage Executive through the American Hotel & Motel Association. He has over 15 years of experience in food and beverage management, hotel and resort operations, and cruise ship operations.
The document outlines a seminar on advanced social media marketing for businesses. It discusses the benefits of social media for customer relations, marketing, sales, and search engine optimization. It addresses whether a company should use social media and which networks are most effective. The presentation cautions against common mistakes like not participating actively or failing to engage others. Examples are given of how other companies have successfully used social media. The document concludes by advising listeners to assess their clients' social media use, avoid making false promises, use social media management tools, and consider in-house versus external social media management.
The document provides tips for drawing human bodies, including proportions, head, arms, hands, torso, legs, and feet. It notes that proportions are key, with hands keeping position and bodies counted in heads. Body parts must be balanced, even when dancing. The head details include ears lining up with eyebrows and the nose being the size of the eyes. When drawing arms, the elbow takes the shape of a diamond. Hands can be referenced by looking at one's own. Torso drawings differ for males and females. Legs have curves, with the middle bottom slightly shorter than the top. Feet can be drawn as a circle and triangle. Exceptions are made for cartoons and anime styles.
The document provides information about library resources for a BIOL 4206 class, including 2 million volumes, 15,000 serials, 250 databases, and study rooms. It lists 5 class objectives related to navigating the library website, understanding peer-reviewed articles, and distinguishing primary, secondary, and tertiary literature. It also describes services like remote access, interlibrary loans, and printing and provides brief explanations of peer review, primary/secondary/tertiary sources, Boolean searching, and citation searching.
This document contains contact information for Tran Ngoc Duyen, a sale executive at Ben Thanh Land Investment Corp located at 172-174 Ky Con St, Nguyen Thai Binh Ward, District 1, Ho Chi Minh City. The document lists Duyen's mobile number and email address as the points of contact.
This document discusses optimal detection theory for digital modulation and coding. It contains the following key points:
1) The goal of detection is to minimize error probability by choosing the optimal decision rule that maximizes the probability of the received signal given each possible transmitted signal.
2) The maximum a posteriori (MAP) and maximum likelihood (ML) receivers are introduced as optimal detectors.
3) For binary antipodal signaling in additive white Gaussian noise, the MAP detector reduces to choosing the signal closest to the received signal.
4) Expressions are provided for the error probability of binary signaling schemes in AWGN, including the well-known Q-function expression for binary antipodal signaling.
The document discusses virtual memory and TLB misses. When a TLB miss occurs, the TLB entry for the requested translation must be loaded. This can be done by hardware reloading the TLB from the page table or via a software TLB miss handler. The handler looks up the page table entry, loads the TLB, and resumes execution. Demand paging is also covered, where non-resident pages are swapped to disk and reloaded on access to reduce memory usage based on locality of reference.
The document discusses plans to restructure districts in Manresa, Spain into science quarters. It aims to diversify the local economy away from sectors hit by the crisis towards high value sectors like materials technology and health. Key projects include developing the Central Park Technological Park and a Knowledge-University Campus. The plan also seeks to strengthen the entrepreneurship ecosystem and promote the city to attract investment.
We provide high quality wedding, bridal, engagement, and family photography with a fashion-oriented, artistic style. Our skilled photographers capture meaningful moments beautifully using special lighting techniques and post-processing to ensure colors are correct in the final images. We work to discuss clients' photography needs and provide custom pricing for wedding, portrait, event, and commercial photography sessions anywhere.
This document provides an introduction and overview of ARM processors. It discusses the background and concepts of ARM, including that ARM is a RISC architecture designed for efficiency. It describes key ARM architectural features like the Harvard architecture and conditional execution. The document also covers ARM memory organization, registers, instruction set, programming model, and exceptions.
The ARM7TDMI-S CPU uses a 3-stage pipeline withThumb and ARM instruction sets. It has 7 processor modes and 37 registers. In Thumb state, instructions are 16-bit while operations remain 32-bit. Exceptions cause mode switches and use separate register banks. Interrupts are prioritized with FIQ having lowest latency. The pipeline improves performance but branches reduce its efficiency.
This document discusses general-purpose processors. It begins by introducing general-purpose processors and their basic architecture, which consists of a control unit and datapath that is designed to perform a variety of computation tasks. It then describes the operations of loading, storing, and arithmetic/logical operations that can be performed by the datapath. Subsequent sections provide more details on the control unit and how it sequences operations, instruction cycles, architectural considerations like bit-width and clock frequency, and techniques for improving performance like pipelining and superscalar execution. The document concludes with sections on assembly-level instructions and programmer considerations.
W8_1: Intro to UoS Educational ProcessorDaniel Roggen
Introduction to the University of Sussex Educational Processor
In this unit we introduce the UoS educational processor and it's key components, including register banks, ALU, IO and memory interfaces, etc.
Unit duration: 50mn.
License: LGPL 2.1
The document decomposes the functioning of a processor into elementary operations called micro-operations. It describes the basic elements of a processor including registers, data paths, an ALU, and a control unit. The control unit sequences and executes micro-operations to perform the fetch, indirect, execute, and interrupt cycles of the instruction cycle. The control unit uses a clock, instruction register, and flags to determine the timing and sequencing of micro-operations.
This document discusses the operating system architecture and system calls of the Tock operating system. It describes the key components of Tock including processes, system calls like command, subscribe, yield, and allow, and the driver API. Processes in Tock are isolated and protected with memory protection units. System calls allow processes to interact with drivers to perform actions or register callbacks. Drivers implement the SyscallDriver trait to handle system calls.
The document discusses key aspects of ARM processors including:
- ARM uses a RISC architecture with a load/store design and 32 registers. It has evolved through multiple revisions with increasing pipeline stages.
- Exceptions and interrupts cause a change in processor mode and use of banked registers. The vector table stores addresses for exception handling routines.
- Caches, an MMU, and coprocessors are common extensions to improve ARM core performance and functionality.
- The ARM instruction set exists in ARM, Thumb, and Jazelle variants to balance code size and performance. Conditional execution is supported through condition flags.
This document discusses the Java Virtual Machine (JVM) memory model and just-in-time (JIT) compilation. It explains that the JVM uses dynamic compilation via a JIT to optimize bytecode at runtime. The JIT profiles code and performs optimizations like inlining, loop unrolling, and escape analysis. It also discusses how the JVM memory model allows for instruction reordering and caching but ensures sequential consistency through happens-before rules and volatile variables. The document provides examples of anomalies that can occur without synchronization and how tools like synchronized, locks, and atomic operations can be used to prevent issues.
Microchip's PIC Micro Controller - Presentation Covers- Embedded system,Application, Harvard and Von Newman Architecture, PIC Microcontroller Instruction Set, PIC assembly language programming, PIC Basic circuit design and its programming etc.
The document discusses the ARM Cortex-M3 processor architecture. It describes key features of the Cortex-M3 such as its Harvard bus architecture, 3-stage pipeline, configurable interrupt controller, and optional components like the memory protection unit. It also covers the ARM instruction set architecture, including Thumb-2 instructions, conditional execution, registers, memory mapping, and data processing instructions.
The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the operation of the processor. It tells the computer's memory, arithmetic/logic unit and input and output devices how to respond to a program's instructions.
The document describes XenTT, a tool for deterministic replay in the Xen virtualization platform. XenTT records the execution history of a guest VM, including nondeterministic events like interrupts and I/O. It then replays the execution deterministically to allow for repeatable systems analysis. This is done by making the CPU and execution environment deterministic during replay and precisely recording the timing and location of nondeterministic events during the original run.
This document provides an overview of the Intel x86 architecture, including its registers, instructions, memory management, interrupts and exceptions, task management, and input/output capabilities. It describes the basic execution environment including memory management registers and control registers. It explains the operation modes of protected mode and real mode, and the memory models. It also summarizes the general purpose instructions, system instructions, privilege levels, basic program execution registers, and memory addressing in the x86 architecture.
The document discusses the MIPS instruction set architecture (ISA). It covers the components of the MIPS ISA including register operands, memory operands, arithmetic operations, and control flow operations. It also discusses the interplay between high-level languages like C and low-level machine code in the MIPS ISA. Key aspects of the MIPS ISA include its load-store architecture where all operations use register operands, its use of 32 registers to manage data, and its basic instruction format of operation, source operands, and destination operand.
digital signal processing
Computer Architectures for signal processing
Harvard Architecture, Pipelining, Multiplier
Accumulator, Special Instructions for DSP, extended
Parallelism,General Purpose DSP Processors,
Implementation of DSP Algorithms for var
ious operations,Special purpose DSP
Hardware,Hardware Digital filters and FFT processors,
Case study and overview of TMS320
series processor, ADSP 21XX processor
In this unit we introduce interrupts in processors and microcontrollers. We explain how the UoS processor (which doesn't support interrupts currently) could be extended to support interrupts.
Unit duration: 50mn.
License: LGPL 2.1
Presents features of ARM Processors, ARM architecture variants and Processor families. Further presents, ARM v4T architecture, ARM7-TDMI processor: Register organization, pipelining, modes, exception handling, bus architecture, debug architecture and interface signals.
Lecture-6-PIC Programming in C-good.pdfAvinashJain66
This document provides an overview of PIC programming in C, including:
- Code space limitations on PIC microcontrollers compared to general purpose PCs
- Benefits of using C over assembly language for PIC programming
- Integer and floating point data types in C and their representations on PICs
- Functions for time delays, port I/O programming, and extracting single decimal digits from numbers for display
- Header files, logic operations, and the #define directive in PIC C programming
The document provides information about the ARM architecture including:
1. ARM started as a replacement for the 8-bit 6502 chip in 1985 and was later spun off as its own company focusing on embedded CPU cores.
2. ARM is a 32-bit architecture with a load/store design using 3-operand instructions. It has a large register set and pipelined execution, along with some CISC features like complex multiply and load/store instructions.
3. The ARM programming model includes 7 processor modes, 37 registers including general purpose and special registers like the program counter and status registers, and conditional execution of instructions.
This document discusses problems involving modulation techniques and signal detection. Problem 1 asks to sketch modulated waves for 8-ary ASK, 4-ary PSK, and 4-ary FSK modulation of a binary sequence. Problem 2 provides a formula for probability of error for 4-ary PAM and asks to calculate average power. Problem 3 does similarly for 4-ary QAM. Problem 4 describes a binary system with an integrate-and-dump detector and asks to analyze the detector and find minimum error probability.
This document contains 4 problems related to digital and analog communications techniques:
1) It describes Delta Modulation and how it works to encode analog signals, including issues with slope overload. It also introduces Adaptive Delta Modulation as an improvement.
2) It compares Differential Pulse Code Modulation to standard Pulse Code Modulation.
3) It provides exercises on encoding a binary sequence using BPSK, DPSK, and 4-ary ASK modulation. It also covers removing phase ambiguity in DPSK.
4) It presents a problem on time division multiplexing analog and digital sources at different data rates.
The document discusses problems related to analogue and digital communications. It contains 5 problems:
1) Drawing the spectrum of a message signal sampled at different rates and specifying the cutoff frequency to fully recover the original signal from its sampled version.
2) Sketching the resulting pulse code modulation (PCM) wave for one cycle of an input signal that is quantized using a 4-bit binary system.
3) Determining the number of quantizing levels, quantizer step size, average quantizing noise power, and output signal-to-noise ratio for a sinusoidal modulating wave quantized using an n-bit code word.
4) Finding the Nyquist sampling rate for two signals.
This document provides a tutorial on analogue and digital communications. It contains 5 questions about Fourier transforms and frequency domain analysis of signals. Question 1 asks about the Fourier transform and spectra of a continuous time signal. Question 2 finds the Fourier transform and spectra of another signal. Question 3 analyzes a signal composed of two sinusoidal components. Questions 4 and 5 determine the Fourier transforms of rectangular and truncated sinusoidal signals.
This document contains two questions about FM signals and phase-locked loops (PLL). Question 1 asks about the instantaneous frequency, modulation index, effective bandwidth using Carson's rule and universal rule, and Fourier transform of an FM signal. Question 2 provides a block diagram of a PLL and asks the student to show equations for the voltage controlled oscillator output, input to the VCO, and how the PLL locks into the input signal's phase. It also asks how the input to the VCO would be related to the message signal for an FM input.
1) The document discusses different modulation techniques including AM, DSB-SC, SSB, and VSB.
2) It provides examples of carrier and message signals for AM and DSB-SC modulation. Equations for the modulated signals and corresponding spectra are given.
3) Questions are asked about modulation index, bandwidth requirements, power efficiency for AM, and the block diagram and output for coherent detection of DSB-SC.
1) The document describes digital signal detection techniques at the receiver of a digital communication system.
2) It discusses the maximum a posteriori probability (MAP) and maximum likelihood (ML) detection criteria. The ML criterion reduces to choosing the signal that minimizes the Euclidean distance between the received signal vector and possible transmitted signals.
3) Detection errors occur when the received signal, distorted by noise, falls inside the decision region of another signal. The probability of error depends on the noise distribution around the actual transmitted signal.
1. This document discusses M-ary modulation techniques, which allow more than two amplitude, phase, or frequency levels to transmit more bits per symbol. This increases transmission rate or reduces bandwidth compared to binary modulation.
2. M-ary modulation techniques discussed include M-ASK, M-PSK, M-FSK, and M-QAM. M-ASK maps k bits to one of M amplitude levels. M-PSK maps k bits to one of M phase shifts of the carrier. M-QAM combines M-ASK with quadrature carriers to modulate both amplitude and phase.
3. Higher order modulation like M-QAM can significantly increase transmission rate but requires more transmission power and complex
The document provides an overview of digital passband modulation techniques. It discusses binary modulation schemes including amplitude-shift keying (ASK), frequency-shift keying (FSK), and phase-shift keying (BPSK). It also covers differential phase-shift keying (DPSK), which removes phase ambiguity in BPSK using differential encoding and decoding. Key aspects like signal representation, spectrum, and detection methods are described for each technique.
This document discusses an integrate-and-dump detector used in digital communications. It describes the operation of the integrate-and-dump detector, showing how it integrates the received signal plus noise over each symbol interval. The output of the integrator is used to detect whether a 1 or 0 was transmitted. An expression is derived for the probability of detection error in terms of the signal amplitude, noise power spectral density, and symbol interval. An example is also provided to calculate the error probability for a given binary signaling scheme and system parameters.
This document discusses quantization in analog-to-digital conversion. It describes how an analog signal is sampled, quantized by representing samples with discrete levels, and encoded into a digital signal. Quantization introduces noise that can be reduced by using more quantization levels or a smaller step size between levels. Non-uniform quantization allocates more levels to signal amplitudes that occur more frequently to improve efficiency compared to uniform quantization.
This document discusses multiplexing techniques used in communications systems. It describes frequency division multiplexing (FDM), time division multiplexing (TDM), and digital multiplexing used for digital telephone systems. FDM combines signals by assigning each a unique portion of the frequency spectrum. TDM combines signals by assigning each a unique time slot within a repeating time frame. Digital telephone systems use TDM to combine 24 digitized voice channels into a 193-bit frame transmitted every 125 microseconds.
This document discusses pulse code modulation (PCM) for analog to digital conversion. PCM involves sampling an analog signal, quantizing the sample values, and encoding the quantized levels into binary codes. The sampling rate must be at least twice the bandwidth of the analog signal. More bits per code provide higher quality but require more bandwidth. PCM is used in telephone systems with 8-bit coding at 8 kHz sampling, and in compact discs with 16-bit coding at 44.1 kHz sampling.
This document discusses delta modulation and adaptive delta modulation techniques for analogue to digital conversion.
Delta modulation encodes the difference between the input signal and a reference signal into a single bit per sample, creating a staircase-like approximation of the original signal. Adaptive delta modulation varies the step size according to the input signal level to prevent slope overload. Differential pulse code modulation encodes the difference between the current and predicted sample values, sending this difference value instead of absolute sample amplitudes.
This document discusses quantization in analog-to-digital conversion. It describes how an analog signal is sampled, quantized by representing samples with discrete levels, and encoded into a digital signal. Quantization introduces noise that can be reduced by using more quantization levels or a smaller step size between levels. Non-uniform quantization allocates more levels to signal amplitudes that occur more frequently to more efficiently represent the signal.
This document discusses quantization in analog-to-digital conversion. It describes how an analog signal is sampled, quantized by representing samples with discrete levels, and encoded into a digital signal. Quantization introduces noise that can be reduced by using more quantization levels or a smaller step size between levels. Non-uniform quantization allocates more levels to signal amplitudes that occur more frequently to more efficiently represent the signal.
This document discusses pulse modulation techniques in communications. It begins by reviewing continuous-wave modulation techniques studied previously, such as amplitude modulation and angle modulation. It then previews that pulse modulation will be studied next, including analog pulse modulation where a pulse feature varies continuously with the message, and digital pulse modulation using a sequence of coded pulses. The document provides explanations and equations regarding sampling of continuous-time signals, the sampling theorem, and recovery of the original analog signal from its samples. It also introduces pulse amplitude modulation (PAM) using natural and flat-top sampling, as well as pulse duration modulation (PDM) and pulse position modulation (PPM).
This document describes the operation of a phase-locked loop (PLL) circuit for demodulating frequency modulated (FM) signals. It contains 6 pages describing:
1) The basic block diagram of a PLL including a voltage controlled oscillator, multiplier, loop filter, and voltage controlled oscillator.
2) The mathematical equations showing how the PLL locks the phase and frequency of the voltage controlled oscillator to that of the incoming FM signal.
3) When the PLL is in phase lock and near phase lock based on the phase error between the signals.
4) How the PLL can be used to demodulate an FM signal and recover the original message signal by matching the phase and frequency of the voltage controlled
This document discusses the transmission of frequency modulated (FM) waves. It explains that the bandwidth of an FM wave is theoretically infinite but is effectively limited in practice. Carson's rule provides an estimate of the bandwidth but is not always accurate. The document also describes Armstrong's method for generating FM waves using narrowband phase modulation and frequency multiplication, and demodulating FM waves using envelope detection after taking the derivative of the received signal.
This document discusses angle modulation techniques for communications. It begins by defining phase modulation (PM) and frequency modulation (FM), where the carrier angle or frequency varies with the modulating signal. Key differences between PM and FM are outlined. Properties of angle modulation like constant transmitted power and irregular zero crossings are described. Narrowband FM is analyzed using sinusoidal modulation. Generation of narrowband FM using an integrator is also shown.
2. Learning Outcomes
• A high-level understanding of System Calls
– Mostly from the user’s perspective
• From textbook (section 1.6)
• Exposure architectural details of the MIPS R3000
– Detailed understanding of the of exception handling mechanism
• From “Hardware Guide” on class web site
• Understanding of the existence of compiler function
calling conventions
– Including details of the MIPS ‘C’ compiler calling convention
• Understanding of how the application kernel boundary is
crossed with system calls in general
• Including an appreciation of the relationship between a case study
(OS/161 system call handling) and the general case.
2
3. Operating System
System Calls
Kernel Level
Operating System
Requests Applications
(System Calls)
User Level
Applications Applications
3
4. System Calls
• Can be viewed as special function calls
– Provides for a controlled entry into the kernel
– While in kernel, they perform a privileged
operation
– Returns to original caller with the result
• The system call interface represents the
abstract machine provided by the
operating system.
4
5. A Brief Overview of Classes
System Calls
• From the user’s perspective
– Process Management
– File I/O
– Directories management
– Some other selected Calls
– There are many more
• On Linux, see man syscalls for a list
5
12. The MIPS R2000/R3000
• Before looking at system call mechanics in
some detail, we need a basic
understanding of the MIPS R3000
12
13. MIPS R3000
• Load/store architecture
– No instructions that operate on memory except load
and store
– Simple load/stores to/from memory from/to registers
• Store word: sw r4, (r5)
– Store contents of r4 in memory using address contained in
register r5
• Load word: lw r3,(r7)
– Load contents of memory into r3 using address contained in r7
– Delay of one instruction after load before data available in
destination register
» Must always an instruction between a load from memory
and the subsequent use of the register.
– lw, sw, lb, sb, lh, sh,….
13
14. MIPS R3000
• Arithmetic and logical operations are
register to register operations
• E.g., add r3, r2, r1
• No arithmetic operations on memory
• Example
– add r3, r2, r1 ⇒ r3 = r2 + r1
• Some other instructions
– add, sub, and, or, xor, sll, srl
14
15. MIPS R3000
• All instructions are encoded in 32-bit
• Some instructions have immediate operands
– Immediate values are constants encoded in the
instruction itself
– Only 16-bit value
– Examples
• Add Immediate: addi r2, r1, 2048
⇒ r2 = r1 + 2048
• Load Immediate : li r2, 1234
⇒ r2 = 1234
15
16. MIPS Registers
• User-mode accessible
registers
– 32 general purpose registers
• r0 hardwired to zero
• r31 the link register for jump-
and-link (JAL) instruction
– HI/LO
• 2 * 32-bits for multiply and
divide
– PC
• Not directly visible
• Modified implicitly by jump and
branch instructions
16
17. Branching and Jumping
li r2, 1
• Branching and
jumping have a sw r0,(r3)
branch delay slot j 1f
– The instruction li r2, 2
following a branch li r2, 3
or jump is always
1: sw r2, (r3)
executed prior to
destination
17
18. Jump and Link Instruction
M
• JAL is used to
implement function 0x10 jal 1f
calls 0x14 nop
– r31 = PC+8 0x18 lw r4,(r6)
• Return Address M
register (RA) is 1:
used to return from 0x2a sw r2, (r3)
function call M
0x38 jr r31
18
0x3a nop
20. Coprocessor 0
• The processor control registers
are located in CP0
– Exception/Interrupt management
registers
– Translation management registers
CP0
• CP0 is manipulated using mtc0 CP1 (floating point)
(move to) and mfc0 (move PC: 0x0300
from) instructions HI/LO
– mtc0/mfc0 are only accessible in R1
kernel mode.
Rn
20
21. CP0 Registers
• Exception Management • Miscellaneous
• c0_cause
– Cause of the recent – c0_prid
exception • Processor Identifier
• c0_status
– Current status of the • Memory Management
CPU
• c0_epc • c0_index
– Address of the • c0_random
instruction that caused
the exception • c0_entryhi
• c0_badvaddr • c0_entrylo
– Address accessed that • c0_context
caused the exception
– More about these later
in course
21
23. c0_status
• IM • KU
– Individual interrupt mask – 0 = kernel
bits – 1 = user mode
– 6 external • IE
– 2 software – 0 = all interrupts masked
– 1 = interrupts enable
• Mask determined via IM bits
• c, p, o = current, previous, old
23
24. c0_cause
• IP • BD
– Interrupts pending – If set, the instruction
• 8 bits indicating current that caused the
state of interrupt lines exception was in a
• CE branch delay slot
– Coprocessor error • ExcCode
• Attempt to access
disabled Copro. – The code number of
the exception taken
24
27. c0_epc
• The Exception Program nop
Counter sw r3 (r4) c0_epc
– Points to address of where nop
to restart execution after
handling the exception or
interrupt
– Example
• Assume sw r3,(r4)
causes a fault exception
Aside: We are ignore BD-bit in
c0_cause which is also used in
reality on rare occasions.
27
30. Hardware exception handling
PC EPC
0x12345678 ?
Cause
• Let’s now walk
through an exception ?
– Assume an interrupt
occurred as the Status KUo IEo KUp IEp KUc IEc
previous instruction ? ? ? ? 1 1
completed
– Note: We are in user
mode with interrupts
enabled
30
31. Hardware exception handling
PC EPC
0x12345678 0x12345678
Cause
?
• Instruction address at Status KUo IEo KUp IEp KUc IEc
which to restart after ? ? ? ? 1 1
the interrupt is
transferred to EPC
31
32. Hardware exception handling
Interrupts
PC EPC
disabled
0x12345678 and previous
0x12345678
state shifted
Causealong
?
Kernel Mode is Status KUo IEo KUp IEp KUc IEc
set, and ? ? 1 1 0 0
previous mode
shifted along
32
33. Hardware exception handling
PC EPC
0x12345678 0x12345678
Cause
0
Status KUo IEo KUp IEp KUc IEc
? ? 1 1 0 0
Code for the
exception placed in
Cause. Note
Interrupt code = 0
33
34. Hardware exception handling
PC EPC
0x80000080 0x12345678
Cause
0
Status KUo IEo KUp IEp KUc IEc
? ? 1 1 0 0
Address of general
exception vector
placed in PC
34
35. Hardware exception handling
PC EPC
0x80000080 0x12345678
• CPU is now running in Cause
kernel mode at
0x80000080, with 0
interrupts disabled
Status KUo IEo KUp IEp KUc IEc
• All information required to
– Find out what caused the ? ? 1 1 0 0
exception
– Restart after exception Badvaddr
handling
is in coprocessor
registers
35
36. Returning from an exception
• For now, lets ignore
– how the exception is actually handled
– how user-level registers are preserved
• Let’s simply look at how we return from the
exception
36
37. Returning from an exception
PC EPC
0x80001234 0x12345678
• This code to return is Cause
0
lw r27, saved_epc
Status KUo IEo KUp IEp KUc IEc
nop
jr r27 Load the contents1of 0 0
? ? 1
rfe EPC which is usually
moved earlier to
somewhere in memory
by the exception handler
37
38. Returning from an exception
PC EPC
0x12345678 0x12345678
• This code to return is Cause
0
lw r27, saved_epc
Status KUo IEo KUp IEp KUc IEc
nop
jr r27 ? ? 1 1 0 0
Store the EPC back in
rfe
the PC
38
39. Returning from an exception
PC EPC
0x12345678 In the branch delay slot,
0x12345678
execute a restore from
• This code to return is Causeinstruction
exception
0
lw r27, saved_epc
Status KUo IEo KUp IEp KUc IEc
nop
jr r27 ? ? ? ? 1 1
rfe
39
40. Returning from an exception
PC EPC
0x12345678 0x12345678
• We are now back in the Cause
same state we were in
0
when the exception
happened Status KUo IEo KUp IEp KUc IEc
? ? ? ? 1 1
40
41. Function Stack Frames
• Each function call allocates Stack
a new stack frame for local Frame
variables, the return Pointer
address, previous frame f1() stack
pointer etc. frame
– Frame pointer: start of Stack
current stack frame Pointer
– Stack pointer: end of current
stack frame
• Example: assume f1() calls
f2(), which calls f3().
41
42. Function Stack Frames
• Each function call allocates Stack
a new stack frame for local
variables, the return
address, previous frame f1() stack
pointer etc. frame
– Frame pointer: start of Frame
current stack frame Pointer
– Stack pointer: end of current f2() stack
stack frame frame
Stack
• Example: assume f1() calls
Pointer
f2(), which calls f3().
42
43. Function Stack Frames
• Each function call allocates Stack
a new stack frame for local
variables, the return
address, previous frame f1() stack
pointer etc. frame
– Frame pointer: start of
current stack frame
– Stack pointer: end of current f2() stack
stack frame
Frame frame
• Example: assume f1() calls Pointer
f2(), which calls f3(). f3() stack
Stack frame
Pointer
43
44. Compiler Register Conventions
• Given 32 registers, which registers are
used for
– Local variables?
– Argument passing?
– Function call results?
– Stack Pointer?
44
46. Stack Frame
• MIPS calling
convention for
gcc
– Args 1-4 have
space
reserved for
them
46
47. Example Code
main () int sixargs(int a, int b,
{ int c, int d, int e,
int i; int f)
{
i = return a + b + c + d
sixargs(1,2,3,4,5,6); + e + f;
} }
47
52. User and Kernel Execution
• Simplistically, execution state consists of
– Registers, processor mode, PC, SP
• User applications and the kernel have their
own execution state.
• System call mechanism safely transfers
from user execution to kernel execution
and back.
52
53. System Call Mechanism in
Principle
• Processor mode
– Switched from user-mode to kernel-mode
• Switched back when returning to user mode
• SP
– User-level SP is saved and a kernel SP is initialised
• User-level SP restored when returning to user-mode
• PC
– User-level PC is saved and PC set to kernel entry
point
• User-level PC restored when returning to user-level
– Kernel entry via the designated entry point must be
strictly enforced
53
54. System Call Mechanism in
Principle
• Registers
– Set at user-level to indicate system call type and its
arguments
• A convention between applications and the kernel
– Some registers are preserved at user-level or kernel-
level in order to restart user-level execution
• Depends on language calling convention etc.
– Result of system call placed in registers when
returning to user-level
• Another convention
54
55. Why do we need system calls?
• Why not simply jump into the kernel via a
function call????
– Function calls do not
• Change from user to kernel mode
– and eventually back again
• Restrict possible entry points to secure locations
55
56. Steps in Making a System Call
There are 11 steps in making the system call
read (fd, buffer, nbytes) 56
57. MIPS System Calls
• System calls are invoked via a syscall
instruction.
– The syscall instruction causes an exception and
transfers control to the general exception handler
– A convention (an agreement between the kernel and
applications) is required as to how user-level software
indicates
• Which system call is required
• Where its arguments are
• Where the result should go
57
58. OS/161 Systems Calls
• OS/161 uses the following conventions
– Arguments are passed and returned via the
normal C function calling convention
– Additionally
• Reg v0 contains the system call number
• On return, reg a3 contains
– 0: if success, v0 contains successful result
– not 0: if failure, v0 has the errno.
» v0 stored in errno
» -1 returned in v0
58
59. ra Preserved ra
fp fp Convention
Convention for sp for kernel
kernel entry sp
gp Preserved for gp exit
k1 C calling
convention
k1
k0 k0
s7 Preserved s7
M M
s0 s0
t9 t9
M M
t0
Success?
t0
a3 Args in a3
a2 a2
a1 a1
a0 a0
v1 Result v1
v0 v0
AT AT
zero SysCall No. zero
59
60. • Seriously low-
level code follows
move a0,s3
• This code is not addiu a1,sp,16
for the faint jal 40068c <read>
hearted li a2,1024
move s0,v0
blez s0,400194 <docat+0x94>
60
61. User-Level System Call Walk
Through – Calling read()
int read(int filehandle, void *buffer, size_t size)
• Three arguments, one return value
• Code fragment calling the read function
400124: 02602021 move a0,s3
400128: 27a50010 addiu a1,sp,16
40012c: 0c1001a3 jal 40068c <read>
400130: 24060400 li a2,1024
400134: 00408021 move s0,v0
400138: 1a000016 blez s0,400194 <docat+0x94>
• Args are loaded, return value is tested
61
62. Inside the read() syscall function
part 1
0040068c <read>:
40068c: 08100190 j 400640 <__syscall>
400690: 24020005 li v0,5
• Appropriate registers are preserved
– Arguments (a0-a3), return address (ra), etc.
• The syscall number (5) is loaded into v0
• Jump (not jump and link) to the common
syscall routine
62
63. The read() syscall function
part 2 Generate a syscall
exception
00400640 <__syscall>:
400640: 0000000c syscall
400644: 10e00005 beqz a3,40065c <__syscall+0x1c>
400648: 00000000 nop
40064c: 3c011000 lui at,0x1000
400650: ac220000 sw v0,0(at)
400654: 2403ffff li v1,-1
400658: 2402ffff li v0,-1
40065c: 03e00008 jr ra
400660: 00000000 nop
63
64. The read() syscall function
Test success, if yes,
part 2 branch to return
00400640 <__syscall>: from function
400640: 0000000c syscall
400644: 10e00005 beqz a3,40065c <__syscall+0x1c>
400648: 00000000 nop
40064c: 3c011000 lui at,0x1000
400650: ac220000 sw v0,0(at)
400654: 2403ffff li v1,-1
400658: 2402ffff li v0,-1
40065c: 03e00008 jr ra
400660: 00000000 nop
64
65. The read() syscall function
part 2
00400640 <__syscall>: If failure, store code
400640: 0000000c syscall in errno
400644: 10e00005 beqz a3,40065c <__syscall+0x1c>
400648: 00000000 nop
40064c: 3c011000 lui at,0x1000
400650: ac220000 sw v0,0(at)
400654: 2403ffff li v1,-1
400658: 2402ffff li v0,-1
40065c: 03e00008 jr ra
400660: 00000000 nop
65
66. The read() syscall function
part 2
00400640 <__syscall>: Set read() result to
400640: 0000000c syscall -1
400644: 10e00005 beqz a3,40065c <__syscall+0x1c>
400648: 00000000 nop
40064c: 3c011000 lui at,0x1000
400650: ac220000 sw v0,0(at)
400654: 2403ffff li v1,-1
400658: 2402ffff li v0,-1
40065c: 03e00008 jr ra
400660: 00000000 nop
66
67. The read() syscall function
part 2
00400640 <__syscall>:
Return to location
400640: 0000000c syscall
after where read()
400644: 10e00005
was called
beqz a3,40065c <__syscall+0x1c>
400648: 00000000 nop
40064c: 3c011000 lui at,0x1000
400650: ac220000 sw v0,0(at)
400654: 2403ffff li v1,-1
400658: 2402ffff li v0,-1
40065c: 03e00008 jr ra
400660: 00000000 nop
67
68. Summary
• From the caller’s perspective, the read() system
call behaves like a normal function call
– It preserves the calling convention of the language
• However, the actual function implements its own
convention by agreement with the kernel
– Our OS/161 example assumes the kernel preserves
appropriate registers(s0-s8, sp, gp, ra).
• Most languages have similar support libraries
that interface with the operating system.
68
69. System Calls - Kernel Side
• Things left to do
– Change to kernel stack
– Preserve registers by saving to memory (the stack)
– Leave saved registers somewhere accessible to
• Read arguments
• Store return values
– Do the “read()”
– Restore registers
– Switch back to user stack
– Return to application
69
70. exception:
move k1, sp /* Save previous stack pointer in k1 */
mfc0 k0, c0_status /* Get status register */
andi k0, k0, CST_Kup /* Check the we-were-in-user-mode bit */
beq k0, $0, 1f /* If clear, from kernel, already have stack */
nop /* delay slot */
/* Coming from user mode - load kernel stack into sp */
la k0, curkstack /* get address of "curkstack" */
lw sp, 0(k0) /* get its value */
nop /* Note k0, k1
delay slot for the load */
registers
1:
mfc0 k0, c0_cause /*
available for
Now, load the exception cause. */
j common_exception /* kernel use
Skip to common code */
nop /* delay slot */
70
71. exception:
move k1, sp /* Save previous stack pointer in k1 */
mfc0 k0, c0_status /* Get status register */
andi k0, k0, CST_Kup /* Check the we-were-in-user-mode bit */
beq k0, $0, 1f /* If clear, from kernel, already have stack */
nop /* delay slot */
/* Coming from user mode - load kernel stack into sp */
la k0, curkstack /* get address of "curkstack" */
lw sp, 0(k0) /* get its value */
nop /* delay slot for the load */
1:
mfc0 k0, c0_cause /* Now, load the exception cause. */
j common_exception /* Skip to common code */
nop /* delay slot */
71
72. common_exception:
/*
* At this point:
* Interrupts are off. (The processor did this for us.)
* k0 contains the exception cause value.
* k1 contains the old stack pointer.
* sp points into the kernel stack.
* All other registers are untouched.
*/
/*
* Allocate stack space for 37 words to hold the trap frame,
* plus four more words for a minimal argument block.
*/
addi sp, sp, -164
72
73. /* The order here must match mips/include/trapframe.h. */
sw ra, 160(sp) /* dummy for gdb */
sw s8, 156(sp) /* save s8 */
sw sp, 152(sp) /* dummy for gdb */
sw gp, 148(sp) /* save gp */
sw k1, 144(sp) /* dummy for gdb */
sw k0, 140(sp) /* dummy for gdb */
These six stores are
a “hack” to avoid
sw k1, 152(sp) /* real saved sp */
nop /* delay slot for store */
confusing GDB
You can ignore the
mfc0 k1, c0_epc /* Copr.0 reg 13 == PC for exception of why and
details */
sw k1, 160(sp) /* real saved PC */ how
73
74. /* The order here must match mips/include/trapframe.h. */
sw ra, 160(sp) /* dummy for gdb */
sw s8, 156(sp) /* save s8 */ The real work starts
sw sp, 152(sp) /* dummy for gdb */ here
sw gp, 148(sp) /* save gp */
sw k1, 144(sp) /* dummy for gdb */
sw k0, 140(sp) /* dummy for gdb */
sw k1, 152(sp) /* real saved sp */
nop /* delay slot for store */
mfc0 k1, c0_epc /* Copr.0 reg 13 == PC for exception */
sw k1, 160(sp) /* real saved PC */
74
76. /*
* Save special registers.
*/
mfhi t0 We can now use the
mflo t1 other registers (t0, t1)
sw t0, 32(sp) that we have
sw t1, 28(sp) preserved on the stack
/*
* Save remaining exception context information.
*/
sw k0, 24(sp) /* k0 was loaded with cause earlier */
mfc0 t1, c0_status /* Copr.0 reg 11 == status */
sw t1, 20(sp)
mfc0 t2, c0_vaddr /* Copr.0 reg 8 == faulting vaddr */
sw t2, 16(sp)
/*
* Pretend to save $0 for gdb's benefit.
*/
sw $0, 12(sp)
76
77. /*
* Prepare to call mips_trap(struct trapframe *)
*/
addiu a0, sp, 16 /* set argument */
jal mips_trap /* call it */
nop /* delay slot */
Create a pointer to the
base of the saved
registers and state in
the first argument
register
77
78. struct trapframe {
u_int32_t tf_vaddr; /* vaddr register */ Kernel Stack
u_int32_t tf_status; /* status register */
u_int32_t tf_cause; /* cause register */
u_int32_t tf_lo;
u_int32_t tf_hi;
u_int32_t tf_ra;/* Saved register 31 */
u_int32_t tf_at;/* Saved register 1 (AT) */
epc
u_int32_t tf_v0;/* Saved register 2 (v0) */ s8
u_int32_t tf_v1;/* etc. */ sp
u_int32_t tf_a0;
u_int32_t tf_a1; By creating a pointer to gp
u_int32_t tf_a2; k1
u_int32_t tf_a3; here of type struct k0
u_int32_t tf_t0;
M
trapframe *, we can t9
u_int32_t tf_t7; access the user’s saved t8
u_int32_t tf_s0;
M registers as normal M
u_int32_t tf_s7;
variables within ‘C’ at
u_int32_t tf_t8;
u_int32_t tf_t9;
ra
u_int32_t tf_k0;/* dummy (see exception.S comments) */ hi
u_int32_t tf_k1;/* dummy */ lo
u_int32_t tf_gp;
u_int32_t tf_sp;
cause
u_int32_t tf_s8; status
u_int32_t tf_epc; /* coprocessor 0 epc register
*/
vaddr
}; 78
79. /*
Now we arrive in the ‘C’ kernel
* General trap (exception) handling function for mips.
* This is called by the assembly-language exception handler once
* the trapframe has been set up.
*/
void
mips_trap(struct trapframe *tf)
{
u_int32_t code, isutlb, iskern;
int savespl;
/* The trap frame is supposed to be 37 registers long. */
assert(sizeof(struct trapframe)==(37*4));
/* Save the value of curspl, which belongs to the old context. */
savespl = curspl;
/* Right now, interrupts should be off. */
curspl = SPL_HIGH;
79
80. What happens next?
• The kernel deals with whatever caused the
exception
– Syscall
– Interrupt
– Page fault
– It potentially modifies the trapframe, etc
• E.g., Store return code in v0, zero in a3
• ‘mips_trap’ eventually returns
80
81. exception_return:
/* 16(sp) no need to restore tf_vaddr */
lw t0, 20(sp) /* load status register value into t0 */
nop /* load delay slot */
mtc0 t0, c0_status /* store it back to coprocessor 0 */
/* 24(sp) no need to restore tf_cause */
/* restore special registers */
lw t1, 28(sp)
lw t0, 32(sp)
mtlo t1
mthi t0
/* load the general registers */
lw ra, 36(sp)
lw AT, 40(sp)
lw v0, 44(sp)
lw v1, 48(sp)
lw a0, 52(sp)
lw a1, 56(sp)
lw a2, 60(sp)
lw a3, 64(sp)
81