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LPC 2148 Instructions Set.ppt

The document provides information about the ARM architecture including: 1. ARM started as a replacement for the 8-bit 6502 chip in 1985 and was later spun off as its own company focusing on embedded CPU cores. 2. ARM is a 32-bit architecture with a load/store design using 3-operand instructions. It has a large register set and pipelined execution, along with some CISC features like complex multiply and load/store instructions. 3. The ARM programming model includes 7 processor modes, 37 registers including general purpose and special registers like the program counter and status registers, and conditional execution of instructions.

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1 TM 1 Agenda  Introduction Architecture Programmers Model Instruction Set
2 TM 2 History of ARM • ARM (Acorn RISC Machine) started as a new, powerful, CPU design for the replacement of the 8-bit 6502 in Acorn Computers (Cambridge, UK, 1985) • First models had only a 26-bit program counter, limiting the memory space to 64 MB (not too much by today standards, but a lot at that time). • 1990 spin-off: ARM renamed Advanced RISC Machines • ARM now focuses on Embedded CPU cores • IP licensing: Almost every silicon manufacturer sells some microcontroller with an ARM core. Some even compete with their own designs. • Processing power with low current consumption • Good MIPS/Watt figure • Ideal for portable devices • Compact memories: 16-bit opcodes (Thumb) • New cores with added features • Harvard architecture (ARM9, ARM11, Cortex) • Floating point arithmetic • Vector computing (VFP, NEON) • Java language (Jazelle)
3 TM 3 Facts • 32-bit CPU • 3-operand instructions (typical): ADD Rd,Rn,Operand2 • RISC design… • Few, simple, instructions • Load/store architecture (instructions operate on registers, not memory) • Large register set • Pipelined execution • … Although with some CISC touches… • Multiplication and Load/Store Multiple are complex instructions (many cycles longer than regular, RISC, instructions) • … And some very specific details • No stack. Link register instead • PC as a regular register • Conditional execution of all instructions • Flags altered or not by data processing instructions (selectable) • Concurrent shifts/rotations (at the same time of other processing) • …
4 TM 4
5 TM 5 Agenda Introduction  Architecture Programmers Model Instruction Set
Address Register REGISTER BANK PC Address Incrementer SHIFT Multiplier Write Data Reg. translator D[31:0] INSTRUCCTION DECODER Control Lines ARM Thumb to Instruction Reg. Read Data Reg. B bus A bus ALU bus PC bus A[31:0] A.L.U. ARM7TDMI Block Diagram
7 TM 7 ARM Pipelining examples • Fetch: Read Op-code from memory to internal Instruction Register • Decode: Activate the appropriate control lines depending on Opcode • Execute: Do the actual processing
8 TM 8 ARM7TDMI Pipelining (I) FETCH DECODE EXECUTE FETCH DECODE EXECUTE FETCH DECODE EXECUTE time 3 2 1 instruction • Simple instructions (like ADD) Complete at a rate of one per cycle
9 TM 9 ARM7TDMI Pipelining (II) FETCH DECODE EXECUTE FETCH DECODE FETCH EXECUTE DECODE FETCH DECODE EXECUTE FETCH DECODE EXECUTE Cal. ADDR 1 2 3 Data Xfer. time instruction 5 4 ADD STR ADD ADD ADD stall stall • More complex instructions: STR : 2 effective clock cycles (+1 cycle)
10 TM 10 Agenda Introduction Architecture  Programmers Model Instruction Set
11 TM 11 Data Sizes and Instruction Sets  The ARM is a 32-bit architecture.  When used in relation to the ARM:  Byte means 8 bits  Halfword means 16 bits (two bytes)  Word means 32 bits (four bytes)  Most ARM’s implement two instruction sets  32-bit ARM Instruction Set  16-bit Thumb Instruction Set
12 TM 12 Processor Modes  The ARM has seven operating modes:  User : unprivileged mode under which most tasks run  FIQ : entered when a high priority (fast) interrupt is raised  IRQ : entered when a low priority (normal) interrupt is raised  SVC : (Supervisor) entered on reset and when a Software Interrupt instruction is executed  Abort : used to handle memory access violations  Undef : used to handle undefined instructions  System : privileged mode using the same registers as user mode
13 TM 13 The Registers  ARM has 37 registers all of which are 32-bits long.  1 dedicated program counter  1 dedicated current program status register  5 dedicated saved program status registers  30 general purpose registers  The current processor mode governs which of several banks is accessible. Each mode can access  a particular set of r0-r12 registers  a particular r13 (the stack pointer, sp) and r14 (the link register, lr)  the program counter, r15 (pc)  the current program status register, cpsr Privileged modes (except System) can also access  a particular spsr (saved program status register)
14 TM 14 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ IRQ SVC Undef Abort User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers FIQ IRQ SVC Undef Abort r0 r1 r2 r3 r4 r5 r6 r7 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User IRQ SVC Undef Abort r8 r9 r10 r11 r12 r13 (sp) r14 (lr) FIQ Mode IRQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ SVC Undef Abort r13 (sp) r14 (lr) Undef Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ SVC Abort r13 (sp) r14 (lr) SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ Undef Abort r13 (sp) r14 (lr) Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User, SYS FIQ IRQ SVC Undef r13 (sp) r14 (lr) The ARM Register Set
15 TM 15 Special Registers  Special function registers:  PC (R15): Program Counter. Any instruction with PC as its destination register is a program branch  LR (R14): Link Register. Saves a copy of PC when executing the BL instruction (subroutine call) or when jumping to an exception or interrupt routine - It is copied back to PC on the return from those routines  SP (R13): Stack Pointer. There is no stack in the ARM architecture. Even so, R13 is usually reserved as a pointer for the program-managed stack  CPSR : Current Program Status Register. Holds the visible status register  SPSR : Saved Program Status Register. Holds a copy of the previous status register while executing exception or interrupt routines - It is copied back to CPSR on the return from the exception or interrupt - No SPSR available in User or System modes
16 TM 16 Register Organization Summary User mode r0-r7, r15, and cpsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r0 r1 r2 r3 r4 r5 r6 r7 User, SYS r13 (sp) r14 (lr) spsr IRQ User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Undef User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr SVC User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Abort User mode r0-r12, r15, and cpsr Note: System mode uses the User mode register set
17 TM 17 Program Status Registers  Condition code flags  N = Negative result from ALU  Z = Zero result from ALU  C = ALU operation Carried out  V = ALU operation oVerflowed Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. T Bit (Arch. with Thumb mode only) T = 0: Processor in ARM state T = 1: Processor in Thumb state Never change T directly (use BX instead) Changing T in CPSR will lead to unexpected behavior due to pipelining Tip: Don’t change undefined bits. This allows for code compatibility with newer ARM processors  Mode bits 10000 User 10001 FIQ 10010 IRQ 10011 Supervisor 10111 Abort 11011 Undefined 11111 System I F T N Z C V 31 28 27 24 23 16 15 7 8 6 5 4 mode 0 undefined f x c s
18 TM 18  When the processor is executing in ARM state:  All instructions are 32 bits wide  All instructions must be word aligned  Therefore the PC value is stored in bits [31:2] and bits [1:0] are zero  Due to pipelining, the PC points 8 bytes ahead of the current instruction, or 12 bytes ahead if current instruction includes a register-specified shift  When the processor is executing in Thumb state:  All instructions are 16 bits wide  All instructions must be halfword aligned  Therefore the PC value is stored in bits [31:1] and bit [0] is zero Program Counter (R15)
19 TM 19 Vector Table Exception Handling  When an exception occurs, the ARM:  Copies CPSR into SPSR_<mode>  Sets appropriate CPSR bits:  Changes to ARM state  Changes to related mode  Disables IRQ  Disables FIQ (only on fast interrupts)  Stores the return address in LR_<mode>  Sets PC to vector address  To return, exception handler needs to:  Restore CPSR from SPSR_<mode>  Restore PC from LR_<mode> (more about this later…) This can only be done in ARM state. FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00
20 TM 20 Agenda Introduction Architecture Programmers Model  Instruction Set (for ARM state)
21 TM 21  ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field.  This improves code density and performance by reducing the number of forward branch instructions. CMP r3,#0 CMP r3,#0 BEQ skip ADDNE r0,r1,r2 ADD r0,r1,r2 skip  By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using “S” (comparisons always set the flags). loop … SUBS r1,r1,#1 BNE loop if Z flag clear then branch decrement r1 and set flags Conditional Execution and Flags
22 TM 22 Condition Codes Not equal Unsigned higher or same Unsigned lower Minus Equal Overflow No overflow Unsigned higher Unsigned lower or same Positive or Zero Less than Greater than Less than or equal Always Greater or equal EQ NE CS/HS CC/LO PL VS HI LS GE LT GT LE AL MI VC Suffix Description Z=0 C=1 C=0 Z=1 Flags tested N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V  The 15 possible condition codes are listed below:  Note AL is the default and does not need to be specified
23 TM 23 Advantages of conditional execution
24 TM 24 Examples of conditional execution  Use a sequence of several conditional instructions if (a==0) func(1); CMP r0,#0 MOVEQ r0,#1 BLEQ func  Set the flags, then use various condition codes if (a==0) x=0; if (a>0) x=1; CMP r0,#0 MOVEQ r1,#0 MOVGT r1,#1  Use conditional compare instructions if (a==4 || a==10) x=0; CMP r0,#4 CMPEQ r0,#10 MOVEQ r1,#0
25 TM 25 Data processing Instructions  Consist of :  Arithmetic: ADD ADC SUB SBC RSB RSC  Logical: AND ORR EOR BIC  Comparisons: CMP CMN TST TEQ  Data movement: MOV MVN  These instructions only work on registers, NOT memory. L, Literal: 0: Operand 2 from register, 1: Operand 2 immediate  Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2  {S} means that the Status register is going to be updated  Comparisons always update the status register. Rd is not specified  Data movement does not specify Rn  Second operand is sent to the ALU via barrel shifter. 31 28 25 24 20 16 15 12 11 0 21 19 0 Rd Operand 2 Rn S op-code L 0 cond.
26 TM 26 Register, optionally with shift operation  Shift value can be either be:  5 bit unsigned integer  Specified in bottom byte of another register.  Used for multiplication by a power of 2 Example: ADD R1, R2, R3, LSL #2 (R2 + R3*4) -> R1 Immediate value  8 bit number, with a range of 0-255.  Rotated right through even number of positions  Allows increased range of 32-bit constants to be loaded directly into registers Result Operand 1 Barrel Shifter Operand 2 ALU Using the Barrel Shifter: The Second Operand
27 TM 27 The Barrel Shifter Destination CF 0 Destination CF LSL : Logical Left Shift ASR: Arithmetic Right Shift Multiplication by a power of 2 Division by a power of 2, preserving the sign bit Destination CF ...0 Destination CF LSR : Logical Shift Right ROR: Rotate Right Division by a power of 2 Bit rotate with wrap around from LSB to MSB Destination RRX: Rotate Right Extended Single bit rotate with wrap around from CF to MSB CF
28 TM 28  No ARM instruction can contain a 32 bit immediate constant  All ARM instructions are fixed as 32 bits long  The data processing instruction format has 12 bits available for operand2  4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2  Rule to remember is “8-bits shifted by an even number of bit positions”. 0 7 11 8 immed_8 Shifter ROR rot x2 Immediate constants (1)
29 TM 29  To allow larger constants to be loaded, the assembler offers a pseudo- instruction:  LDR rd, =const (notice the “=“ sign)  This will either:  Produce a MOV or MVN instruction to generate the value (if possible). or  Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code).  For example  LDR r0,=0xFF => MOV r0,#0xFF  LDR r0,=0x55555555 => LDR r0,[PC,#Imm12] … … DCD 0x55555555  This is the recommended way of loading constants into a register Loading 32 bit constants
30 TM 30 Data processing instr. FLAGS  Flags are changed only if the S bit of the op-code is set: Mnemonics ending with “s”, like “movs”, and comparisons: cmp, cmn, tst, teq  N and Z have the expected meaning for all instructions  N: bit 31 (sign) of the result  Z: set if result is zero  Logical instructions (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN)  V: unchanged  C: from barrel shifter if shift ≠ 0. Unchanged otherwise  Arithmetic instructions (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN)  V: Signed overflow from ALU  C: Carry (bit 32 of result) from ALU  When PC is the destination register (exception return)  CPSR is copied from SPSR. This includes all the flags.  No change in user or system modes Example: SUBS PC,LR,#4 @ return from IRQ
31 TM 31 Arithmetic Operations Operations are: ADD operand1 + operand2 ADC operand1 + operand2 + carry SUB operand1 - operand2 SBC operand1 - operand2 + carry -1 RSB operand2 - operand1 RSC operand2 - operand1 + carry - 1 Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 Examples ADD r0, r1, r2 SUBGT r3, r3, #1 RSBLES r4, r5, #5
32 TM 32 Comparisons The only effect of the comparisons is to UPDATE THE CONDITION FLAGS. Thus no need to set S bit. Operations are: CMP operand1 - operand2, but result not written CMN operand1 + operand2, but result not written TSToperand1 AND operand2, but result not written TEQ operand1 EOR operand2, but result not written Syntax: <Operation>{<cond>} Rn, Operand2 Examples: CMP r0, r1 TSTEQ r2, #5
33 TM 33 Logical Operations Operations are: AND operand1 AND operand2 EOR operand1 EOR operand2 ORR operand1 OR operand2 BIC operand1 AND NOT operand2 [ie bit clear] Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 Examples: AND r0, r1, r2 BICEQ r2, r3, #7 EORS r1,r3,r0
34 TM 34 Data Movement Operations are: MOV operand2 MVN NOT operand2 Note that these make no use of operand1. Syntax: <Operation>{<cond>}{S} Rd, Operand2 Examples: MOV r0, r1 MOVS r2, #10 MVNEQ r1,#0
35 TM 35 Multiply  Syntax:  MUL{<cond>}{S} Rd, Rm, Rs Rd = Rm * Rs  MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd = (Rm * Rs) + Rn  [U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := Rm*Rs  [U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo  Cycle time  Basic MUL instruction  2-5 cycles on ARM7TDMI  1-3 cycles on StrongARM/XScale  2 cycles on ARM9E/ARM102xE  +1 cycle for ARM9TDMI (over ARM7TDMI)  +1 cycle for accumulate (not on 9E though result delay is one cycle longer)  +1 cycle for “long”  Above are “general rules” - refer to the TRM for the core you are using for the exact details
36 TM 36  Branch : B{<cond>} label  Branch with Link : BL{<cond>} subroutine_label  The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC  ± 32 Mbyte range  How to perform longer branches or absolute address branches? solution: LDR PC,… 28 31 24 0 Cond 1 0 1 L Offset Condition field Link bit 0 = Branch 1 = Branch with link 23 25 27 Branch instructions
37 TM 37 Single register data transfer LDR STR Word LDRB STRB Byte LDRH STRH Halfword LDRSB Signed byte load LDRSH Signed halfword load  Memory system must support all access sizes  Syntax:  LDR{<cond>}{<size>} Rd, <address>  STR{<cond>}{<size>} <address>, Rn e.g. LDREQB
38 TM 38 Address accessed  Address accessed by LDR/STR is specified by a base register plus an offset  For word and unsigned byte accesses, offset can be  An unsigned 12-bit immediate value (ie 0 - 4095 bytes). LDR r0,[r1,#8]  A register, optionally shifted by an immediate value LDR r0,[r1,r2] LDR r0,[r1,r2,LSL#2]  This can be either added or subtracted from the base register: LDR r0,[r1,#-8] LDR r0,[r1,-r2] LDR r0,[r1,-r2,LSL#2]  For halfword and signed halfword / byte, offset can be:  An unsigned 8 bit immediate value (ie 0-255 bytes).  A register (unshifted).  Choice of pre-indexed or post-indexed addressing
39 TM 39 0x5 0x5 r1 0x200 Base Register 0x200 r0 0x5 Source Register for STR Offset 12 0x20c r1 0x200 Original Base Register 0x200 r0 0x5 Source Register for STR Offset 12 0x20c r1 0x20c Updated Base Register Base-update form (‘!’): STR r0,[r1,#12]! Pre or Post Indexed Addressing?  Pre-indexed: STR r0,[r1,#12]  Post-indexed: STR r0,[r1],#12 Base register always updated
40 TM 40 LDM / STM operation  Load/Store Multiple Syntax: <LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>  4 addressing modes: LDMIA / STMIA increment after LDMIB / STMIB increment before LDMDA / STMDA decrement after LDMDB / STMDB decrement before IA r1 Increasing Address r4 r0 r1 r4 r0 r1 r4 r0 r1 r4 r0 r10 IB DA DB LDMxx r10, {r0,r1,r4} STMxx r10, {r0,r1,r4} Base Register (Rb) Base-update possible: LDM r10!,{r0-r6}
41 TM 41 Atomic data swap  Exchanges a word or byte between a register and a memory location  This operation cannot be interrupted, not even by DMA  Main use: Operating System semaphores  Syntax:  SWP {<cond>} Rd, Rm, [Rn]  SWPB{<cond>} Rd, Rm, [Rn] Rd=[Rn]; [Rn]=Rm (Rd and Rm can be the same)

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LPC 2148 Instructions Set.ppt

  • 1.
  • 2.
    2 TM 2 History ofARM • ARM (Acorn RISC Machine) started as a new, powerful, CPU design for the replacement of the 8-bit 6502 in Acorn Computers (Cambridge, UK, 1985) • First models had only a 26-bit program counter, limiting the memory space to 64 MB (not too much by today standards, but a lot at that time). • 1990 spin-off: ARM renamed Advanced RISC Machines • ARM now focuses on Embedded CPU cores • IP licensing: Almost every silicon manufacturer sells some microcontroller with an ARM core. Some even compete with their own designs. • Processing power with low current consumption • Good MIPS/Watt figure • Ideal for portable devices • Compact memories: 16-bit opcodes (Thumb) • New cores with added features • Harvard architecture (ARM9, ARM11, Cortex) • Floating point arithmetic • Vector computing (VFP, NEON) • Java language (Jazelle)
  • 3.
    3 TM 3 Facts • 32-bitCPU • 3-operand instructions (typical): ADD Rd,Rn,Operand2 • RISC design… • Few, simple, instructions • Load/store architecture (instructions operate on registers, not memory) • Large register set • Pipelined execution • … Although with some CISC touches… • Multiplication and Load/Store Multiple are complex instructions (many cycles longer than regular, RISC, instructions) • … And some very specific details • No stack. Link register instead • PC as a regular register • Conditional execution of all instructions • Flags altered or not by data processing instructions (selectable) • Concurrent shifts/rotations (at the same time of other processing) • …
  • 4.
  • 5.
  • 6.
    Address Register REGISTER BANK PC Address Incrementer SHIFT Multiplier Write DataReg. translator D[31:0] INSTRUCCTION DECODER Control Lines ARM Thumb to Instruction Reg. Read Data Reg. B bus A bus ALU bus PC bus A[31:0] A.L.U. ARM7TDMI Block Diagram
  • 7.
    7 TM 7 ARM Pipeliningexamples • Fetch: Read Op-code from memory to internal Instruction Register • Decode: Activate the appropriate control lines depending on Opcode • Execute: Do the actual processing
  • 8.
    8 TM 8 ARM7TDMI Pipelining(I) FETCH DECODE EXECUTE FETCH DECODE EXECUTE FETCH DECODE EXECUTE time 3 2 1 instruction • Simple instructions (like ADD) Complete at a rate of one per cycle
  • 9.
    9 TM 9 ARM7TDMI Pipelining(II) FETCH DECODE EXECUTE FETCH DECODE FETCH EXECUTE DECODE FETCH DECODE EXECUTE FETCH DECODE EXECUTE Cal. ADDR 1 2 3 Data Xfer. time instruction 5 4 ADD STR ADD ADD ADD stall stall • More complex instructions: STR : 2 effective clock cycles (+1 cycle)
  • 10.
  • 11.
    11 TM 11 Data Sizesand Instruction Sets  The ARM is a 32-bit architecture.  When used in relation to the ARM:  Byte means 8 bits  Halfword means 16 bits (two bytes)  Word means 32 bits (four bytes)  Most ARM’s implement two instruction sets  32-bit ARM Instruction Set  16-bit Thumb Instruction Set
  • 12.
    12 TM 12 Processor Modes The ARM has seven operating modes:  User : unprivileged mode under which most tasks run  FIQ : entered when a high priority (fast) interrupt is raised  IRQ : entered when a low priority (normal) interrupt is raised  SVC : (Supervisor) entered on reset and when a Software Interrupt instruction is executed  Abort : used to handle memory access violations  Undef : used to handle undefined instructions  System : privileged mode using the same registers as user mode
  • 13.
    13 TM 13 The Registers ARM has 37 registers all of which are 32-bits long.  1 dedicated program counter  1 dedicated current program status register  5 dedicated saved program status registers  30 general purpose registers  The current processor mode governs which of several banks is accessible. Each mode can access  a particular set of r0-r12 registers  a particular r13 (the stack pointer, sp) and r14 (the link register, lr)  the program counter, r15 (pc)  the current program status register, cpsr Privileged modes (except System) can also access  a particular spsr (saved program status register)
  • 14.
    14 TM 14 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14(lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ IRQ SVC Undef Abort User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers FIQ IRQ SVC Undef Abort r0 r1 r2 r3 r4 r5 r6 r7 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User IRQ SVC Undef Abort r8 r9 r10 r11 r12 r13 (sp) r14 (lr) FIQ Mode IRQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ SVC Undef Abort r13 (sp) r14 (lr) Undef Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ SVC Abort r13 (sp) r14 (lr) SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ Undef Abort r13 (sp) r14 (lr) Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User, SYS FIQ IRQ SVC Undef r13 (sp) r14 (lr) The ARM Register Set
  • 15.
    15 TM 15 Special Registers Special function registers:  PC (R15): Program Counter. Any instruction with PC as its destination register is a program branch  LR (R14): Link Register. Saves a copy of PC when executing the BL instruction (subroutine call) or when jumping to an exception or interrupt routine - It is copied back to PC on the return from those routines  SP (R13): Stack Pointer. There is no stack in the ARM architecture. Even so, R13 is usually reserved as a pointer for the program-managed stack  CPSR : Current Program Status Register. Holds the visible status register  SPSR : Saved Program Status Register. Holds a copy of the previous status register while executing exception or interrupt routines - It is copied back to CPSR on the return from the exception or interrupt - No SPSR available in User or System modes
  • 16.
    16 TM 16 Register OrganizationSummary User mode r0-r7, r15, and cpsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r0 r1 r2 r3 r4 r5 r6 r7 User, SYS r13 (sp) r14 (lr) spsr IRQ User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Undef User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr SVC User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Abort User mode r0-r12, r15, and cpsr Note: System mode uses the User mode register set
  • 17.
    17 TM 17 Program StatusRegisters  Condition code flags  N = Negative result from ALU  Z = Zero result from ALU  C = ALU operation Carried out  V = ALU operation oVerflowed Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. T Bit (Arch. with Thumb mode only) T = 0: Processor in ARM state T = 1: Processor in Thumb state Never change T directly (use BX instead) Changing T in CPSR will lead to unexpected behavior due to pipelining Tip: Don’t change undefined bits. This allows for code compatibility with newer ARM processors  Mode bits 10000 User 10001 FIQ 10010 IRQ 10011 Supervisor 10111 Abort 11011 Undefined 11111 System I F T N Z C V 31 28 27 24 23 16 15 7 8 6 5 4 mode 0 undefined f x c s
  • 18.
    18 TM 18  Whenthe processor is executing in ARM state:  All instructions are 32 bits wide  All instructions must be word aligned  Therefore the PC value is stored in bits [31:2] and bits [1:0] are zero  Due to pipelining, the PC points 8 bytes ahead of the current instruction, or 12 bytes ahead if current instruction includes a register-specified shift  When the processor is executing in Thumb state:  All instructions are 16 bits wide  All instructions must be halfword aligned  Therefore the PC value is stored in bits [31:1] and bit [0] is zero Program Counter (R15)
  • 19.
    19 TM 19 Vector Table ExceptionHandling  When an exception occurs, the ARM:  Copies CPSR into SPSR_<mode>  Sets appropriate CPSR bits:  Changes to ARM state  Changes to related mode  Disables IRQ  Disables FIQ (only on fast interrupts)  Stores the return address in LR_<mode>  Sets PC to vector address  To return, exception handler needs to:  Restore CPSR from SPSR_<mode>  Restore PC from LR_<mode> (more about this later…) This can only be done in ARM state. FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00
  • 20.
  • 21.
    21 TM 21  ARMinstructions can be made to execute conditionally by postfixing them with the appropriate condition code field.  This improves code density and performance by reducing the number of forward branch instructions. CMP r3,#0 CMP r3,#0 BEQ skip ADDNE r0,r1,r2 ADD r0,r1,r2 skip  By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using “S” (comparisons always set the flags). loop … SUBS r1,r1,#1 BNE loop if Z flag clear then branch decrement r1 and set flags Conditional Execution and Flags
  • 22.
    22 TM 22 Condition Codes Notequal Unsigned higher or same Unsigned lower Minus Equal Overflow No overflow Unsigned higher Unsigned lower or same Positive or Zero Less than Greater than Less than or equal Always Greater or equal EQ NE CS/HS CC/LO PL VS HI LS GE LT GT LE AL MI VC Suffix Description Z=0 C=1 C=0 Z=1 Flags tested N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V  The 15 possible condition codes are listed below:  Note AL is the default and does not need to be specified
  • 23.
    23 TM 23 Advantages ofconditional execution
  • 24.
    24 TM 24 Examples ofconditional execution  Use a sequence of several conditional instructions if (a==0) func(1); CMP r0,#0 MOVEQ r0,#1 BLEQ func  Set the flags, then use various condition codes if (a==0) x=0; if (a>0) x=1; CMP r0,#0 MOVEQ r1,#0 MOVGT r1,#1  Use conditional compare instructions if (a==4 || a==10) x=0; CMP r0,#4 CMPEQ r0,#10 MOVEQ r1,#0
  • 25.
    25 TM 25 Data processingInstructions  Consist of :  Arithmetic: ADD ADC SUB SBC RSB RSC  Logical: AND ORR EOR BIC  Comparisons: CMP CMN TST TEQ  Data movement: MOV MVN  These instructions only work on registers, NOT memory. L, Literal: 0: Operand 2 from register, 1: Operand 2 immediate  Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2  {S} means that the Status register is going to be updated  Comparisons always update the status register. Rd is not specified  Data movement does not specify Rn  Second operand is sent to the ALU via barrel shifter. 31 28 25 24 20 16 15 12 11 0 21 19 0 Rd Operand 2 Rn S op-code L 0 cond.
  • 26.
    26 TM 26 Register, optionallywith shift operation  Shift value can be either be:  5 bit unsigned integer  Specified in bottom byte of another register.  Used for multiplication by a power of 2 Example: ADD R1, R2, R3, LSL #2 (R2 + R3*4) -> R1 Immediate value  8 bit number, with a range of 0-255.  Rotated right through even number of positions  Allows increased range of 32-bit constants to be loaded directly into registers Result Operand 1 Barrel Shifter Operand 2 ALU Using the Barrel Shifter: The Second Operand
  • 27.
    27 TM 27 The BarrelShifter Destination CF 0 Destination CF LSL : Logical Left Shift ASR: Arithmetic Right Shift Multiplication by a power of 2 Division by a power of 2, preserving the sign bit Destination CF ...0 Destination CF LSR : Logical Shift Right ROR: Rotate Right Division by a power of 2 Bit rotate with wrap around from LSB to MSB Destination RRX: Rotate Right Extended Single bit rotate with wrap around from CF to MSB CF
  • 28.
    28 TM 28  NoARM instruction can contain a 32 bit immediate constant  All ARM instructions are fixed as 32 bits long  The data processing instruction format has 12 bits available for operand2  4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2  Rule to remember is “8-bits shifted by an even number of bit positions”. 0 7 11 8 immed_8 Shifter ROR rot x2 Immediate constants (1)
  • 29.
    29 TM 29  Toallow larger constants to be loaded, the assembler offers a pseudo- instruction:  LDR rd, =const (notice the “=“ sign)  This will either:  Produce a MOV or MVN instruction to generate the value (if possible). or  Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code).  For example  LDR r0,=0xFF => MOV r0,#0xFF  LDR r0,=0x55555555 => LDR r0,[PC,#Imm12] … … DCD 0x55555555  This is the recommended way of loading constants into a register Loading 32 bit constants
  • 30.
    30 TM 30 Data processinginstr. FLAGS  Flags are changed only if the S bit of the op-code is set: Mnemonics ending with “s”, like “movs”, and comparisons: cmp, cmn, tst, teq  N and Z have the expected meaning for all instructions  N: bit 31 (sign) of the result  Z: set if result is zero  Logical instructions (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN)  V: unchanged  C: from barrel shifter if shift ≠ 0. Unchanged otherwise  Arithmetic instructions (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN)  V: Signed overflow from ALU  C: Carry (bit 32 of result) from ALU  When PC is the destination register (exception return)  CPSR is copied from SPSR. This includes all the flags.  No change in user or system modes Example: SUBS PC,LR,#4 @ return from IRQ
  • 31.
    31 TM 31 Arithmetic Operations Operationsare: ADD operand1 + operand2 ADC operand1 + operand2 + carry SUB operand1 - operand2 SBC operand1 - operand2 + carry -1 RSB operand2 - operand1 RSC operand2 - operand1 + carry - 1 Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 Examples ADD r0, r1, r2 SUBGT r3, r3, #1 RSBLES r4, r5, #5
  • 32.
    32 TM 32 Comparisons The onlyeffect of the comparisons is to UPDATE THE CONDITION FLAGS. Thus no need to set S bit. Operations are: CMP operand1 - operand2, but result not written CMN operand1 + operand2, but result not written TSToperand1 AND operand2, but result not written TEQ operand1 EOR operand2, but result not written Syntax: <Operation>{<cond>} Rn, Operand2 Examples: CMP r0, r1 TSTEQ r2, #5
  • 33.
    33 TM 33 Logical Operations Operationsare: AND operand1 AND operand2 EOR operand1 EOR operand2 ORR operand1 OR operand2 BIC operand1 AND NOT operand2 [ie bit clear] Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 Examples: AND r0, r1, r2 BICEQ r2, r3, #7 EORS r1,r3,r0
  • 34.
    34 TM 34 Data Movement Operationsare: MOV operand2 MVN NOT operand2 Note that these make no use of operand1. Syntax: <Operation>{<cond>}{S} Rd, Operand2 Examples: MOV r0, r1 MOVS r2, #10 MVNEQ r1,#0
  • 35.
    35 TM 35 Multiply  Syntax: MUL{<cond>}{S} Rd, Rm, Rs Rd = Rm * Rs  MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd = (Rm * Rs) + Rn  [U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := Rm*Rs  [U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo  Cycle time  Basic MUL instruction  2-5 cycles on ARM7TDMI  1-3 cycles on StrongARM/XScale  2 cycles on ARM9E/ARM102xE  +1 cycle for ARM9TDMI (over ARM7TDMI)  +1 cycle for accumulate (not on 9E though result delay is one cycle longer)  +1 cycle for “long”  Above are “general rules” - refer to the TRM for the core you are using for the exact details
  • 36.
    36 TM 36  Branch: B{<cond>} label  Branch with Link : BL{<cond>} subroutine_label  The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC  ± 32 Mbyte range  How to perform longer branches or absolute address branches? solution: LDR PC,… 28 31 24 0 Cond 1 0 1 L Offset Condition field Link bit 0 = Branch 1 = Branch with link 23 25 27 Branch instructions
  • 37.
    37 TM 37 Single registerdata transfer LDR STR Word LDRB STRB Byte LDRH STRH Halfword LDRSB Signed byte load LDRSH Signed halfword load  Memory system must support all access sizes  Syntax:  LDR{<cond>}{<size>} Rd, <address>  STR{<cond>}{<size>} <address>, Rn e.g. LDREQB
  • 38.
    38 TM 38 Address accessed Address accessed by LDR/STR is specified by a base register plus an offset  For word and unsigned byte accesses, offset can be  An unsigned 12-bit immediate value (ie 0 - 4095 bytes). LDR r0,[r1,#8]  A register, optionally shifted by an immediate value LDR r0,[r1,r2] LDR r0,[r1,r2,LSL#2]  This can be either added or subtracted from the base register: LDR r0,[r1,#-8] LDR r0,[r1,-r2] LDR r0,[r1,-r2,LSL#2]  For halfword and signed halfword / byte, offset can be:  An unsigned 8 bit immediate value (ie 0-255 bytes).  A register (unshifted).  Choice of pre-indexed or post-indexed addressing
  • 39.
    39 TM 39 0x5 0x5 r1 0x200 Base Register 0x200 r0 0x5 Source Register forSTR Offset 12 0x20c r1 0x200 Original Base Register 0x200 r0 0x5 Source Register for STR Offset 12 0x20c r1 0x20c Updated Base Register Base-update form (‘!’): STR r0,[r1,#12]! Pre or Post Indexed Addressing?  Pre-indexed: STR r0,[r1,#12]  Post-indexed: STR r0,[r1],#12 Base register always updated
  • 40.
    40 TM 40 LDM /STM operation  Load/Store Multiple Syntax: <LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>  4 addressing modes: LDMIA / STMIA increment after LDMIB / STMIB increment before LDMDA / STMDA decrement after LDMDB / STMDB decrement before IA r1 Increasing Address r4 r0 r1 r4 r0 r1 r4 r0 r1 r4 r0 r10 IB DA DB LDMxx r10, {r0,r1,r4} STMxx r10, {r0,r1,r4} Base Register (Rb) Base-update possible: LDM r10!,{r0-r6}
  • 41.
    41 TM 41 Atomic dataswap  Exchanges a word or byte between a register and a memory location  This operation cannot be interrupted, not even by DMA  Main use: Operating System semaphores  Syntax:  SWP {<cond>} Rd, Rm, [Rn]  SWPB{<cond>} Rd, Rm, [Rn] Rd=[Rn]; [Rn]=Rm (Rd and Rm can be the same)