The document discusses the ARM architecture and interrupt handling. It provides background on ARM and compares RISC and CISC architectures. It describes ARM's instruction sets, data sizes, registers including the program counter and current program status register. It discusses exception handling in ARM, including saving state on exception entry and exit. Interrupts and exceptions are compared to system calls. Memory organization during exceptions is also covered.

1. - SSM 24-1 [ Na_Min_Yeop ]
- naminyeop@naver.com
ARM Architecture
& Interrupt Handling
http://infocenter.arm.com/help/index.jsp

2. ARM Introduction

3. Von Neuman VS Havard

4. ARM Background
RISCs before ARM
- Berkeley RISC I / II
- Stanford MIPS
Features used from Berkeley
RISC
- A load-store architecture
- Fixed-length 32-bit
instructions
- 3-address instruction formats
CISC vs. RISC
- CISC: Complex Instruction Set Computer
- RISC: Reduced Instruction Set Computer
- Trade off between expressiveness and
simplicity
- RISC has become de facto standard for
modern microprocessors
RISC is good to reduce the semantic gap
between
- High-level language and machine
instruction
- Mostly, covered by the compiler

5. ARM – Data Sizes and Instruction Sets
The ARMv7 is a 32-bit architecture.
- 32-bit integer registers
- 32-bit virtual addresses
- 32-bit physical address, but with support for up to 40-bit physical
addresses
The ARMv8 is a 64-bit architecture.
- 64-bit integer registers
- 64-bit virtual addresses
- 40-bit physical address, but with support for up to 48-bit physical
addresses

6. ARM Instruction Sets
ARM
- 32-bit fixed size instructions
Thumb
- Set of instructions with restrictions that are 16-bit fixed size
- Software can switch between Thumb and ARM
Thumb2
- Extension to Thumb allowing some 32-bit instructions intermixed with 16-bit instructions
- Now renamed to Thumb
Jazelle-DBX (Direct Bytecode eXecution)
- Ability to execute JVM bytecodes directly on hardware
ThumbEE (Jazelle-RCT Runtime Compilation Target)
- Thumb2 Execution Environment, with behavior changes to support runtime environment languages (e.g. Java, C#)

7. Details of ARM Architectural variants : T
T
- Stands for Thumb
Thumb instruction set
- 16 bit re-encoded subset of 32bit ARM instruction set
Small code size
- Up to 40% compression
- Simplified design

8. ARM’s Visible Registers
User-level programming
- General purpose registers
- r0 – r14 (32 bit registers)
- Program Counter (PC)
- R15
- Current Program Status Register
- CPSR
System-level programming and for exceptions
- Others
Notes
- r13: is commonly used as a stack pointer
- r14: is used as a link register

9. PC( Program Counter)
When the processor is executing in ARM state:
- All instructions are 32 bits in length
- All instructions must be word aligned
PC value is stored in bits [31:2]
- bits [1:0] equal to zero (word-aligned)
R14 is used as the subroutine link register (LR) and stores the
return address when Branch with Link (BL) operations are
performed, calculated from the PC.
To return from a linked branch
- MOV r15,r14
- MOV pc,lr

10. CPSR( Current Program status register)
Used to store the condition code bits
- Examples
Record the result of a comparison operation
Control whether or not a conditional branch is taken
Format
If(value == 0){
operation 1
}
Else{
operation 2
}

11. CPSR( Current Program status register)
Mode: Processor mode
[ ARM7 TDMI ]
- User mode(usr): Normal program execution mode
- Fast Interrupt mode(fiq): Supports a high-speed data transfer or
channel process
- Interrupt mode(irq): Used for general-purpose interrupt
handling
- Supervisor mode(svc): Protected mode for the operating system
- Abort mode(abt): implements virtual memory and/or memory
protection
- System mode(sys): A privileged user mode for the operating
system. (runs OS tasks)
- Undefined mode(und): supports a software emulation of
hardware coprocessors

12. CPSR( Current Program status register)

13. CPSR( Current Program status register)
T( ARM or Thumb instruction set )
- ARM: 32-bit, word-aligned ARM instructions are executed in this state
- Thumb:16-bit, half-word-aligned Thumb instructions are executed in this state
IF
- Interrupt enables and protection from the change by user programs (Ch. 5)
NZCV
- Condition code flags
- Result of the last ALU operation
- N:Negative / Z: Zero / C: Carry-out / V: Overflow

14. SPSR( Standard for Saved Program Status Register)
Purpose
- Loaded with CPSR when an exceptions occurs
Format
- Same to CPSR
Functions
- Same to CPSR
 Hold information of the most recently performed ALU operation.
 Control the enabling and disabling of interrupts
 Set the processor operating mode

15. Two basic ways of ordering bits
Some machines such as PowerPC and MIPS can do both
ARM, but primarily big endian
Memory System & Edian
Data size
- Byte: 8-bits
- Half-word: 16-bits
- Word: 32-bits

16. Understand of Interrupt
In systems programming, an interrupt is a signal to the processor emitted by
hardware or software indicating an event that needs immediate attention. An
interrupt alerts the processor to a high-priority condition requiring the
interruption of the current code the processor is executing. The processor responds
by suspending its current activities, saving its state, and executing
a function called an interrupt handler (or an interrupt service routine, ISR) to
deal with the event. This interruption is temporary, and, after the interrupt
handler finishes, the processor resumes normal activities.[1] There are two types of
interrupts: hardware interrupts and software interrupts.
https://en.wikipedia.org/wiki/Interrupt

17. What is the difference between
interrupt and exception????
Interrupt is an as asynchronous event that is typically generated by hardware(Ex, I/O) not in
sync with processor instruction execution. While exceptions are synchronous events generated
when processor detect any predefined condition while executing instruction.
What is the difference between
interrupt and System call????
http://www.differencebetween.com/difference-between-system-call-and-vs-interrupt/
System call is a call to a subroutine built in to the system, while Interrupt is an event, which
causes the processor to temporarily hold the current execution. However one major difference is
that system calls are synchronous, whereas interrupts are not. That means system calls occur at
a fixed time (usually determined by the programmer), but interrupts can occur at any time due
an unexpected event such as a key press on the keyboard by the user. Therefore, when ever a
system call occurs the processor only has to remember where to return to, but in the event of an
interrupt, the processor has to remember both the place to return to and the state of the system.
Unlike a system call, an interrupt usually does not have anything to do with the current
program.

18. Exception - 1
Break the normal execution of program
- Handle the interrupts from peripherals
- Guarantee the currently executed instruction in execution
pipeline
General exception procedure
- The current state is saved by copying the PC into r14_exc and
CPSR into SPSR_exc
- Processor operating mode is changed to the appropriate
exception mode
- PC is forced to a value between 0016 and IC16, the particular
value depending on the type of exception

19. Type of exceptions
- FIQ (Fast Interrupt reQuest)
Externally generated by taking the nFIQ input LOW
Fast handling for data or channel transfer
- IRQ(Interrupt ReQuest)
Normal interrupt caused by a LOW level on the nIRQ input
- ABORT
Signaled by the external ABORT input
Indicates that the current memory access cannot be completed
- Software interrupt
Generated by the software interrupt instruction (SWI)
Getting into Supervisor mode
Usually to request a particular supervisor function. OS support

20. When entering an exception
1. Preserves the address of the next
instruction in the appropriate Link
Register (r14)
2. Copies the CPSR into the appropriate
SPSR, Save r0~r7 to stack memory
3. Forces the CPSR mode bits to a value
which depends on the exception
( mode change / Interrupt mask disable )
4. Forces the PC to fetch the next instruction
from the relevant exception vector

21. When leaving exception
1. Move the Link Register to the PC
2. Copies the SPSR back to the CPSR
3. Clears the interrupt disable flags,
it they were set on entry

22. Memory Viewpoint
Fiq Program
User Program
Vector table