L17 equidistant pulse firing scheme
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Part of Lecture series on EE321N, Power Electronics-I delivered by me during Fifth Semester of B.Tech. Electrical Engg., 2012 Z H College of Engg. & Technology, Aligarh Muslim University, Aligarh Please comment and feel free to ask anything related. Thanks!
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Part of Lecture series on EE321N, Power Electronics-I delivered by me during Fifth Semester of B.Tech. Electrical Engg., 2012
Z H College of Engg. & Technology, Aligarh Muslim University, Aligarh
Please comment and feel free to ask anything related. Thanks!
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1) The cosine control scheme employs a cosine wave obtained from the input supply voltage through an integrator. This cosine wave is compared to a DC reference signal to generate trigger pulses for thyristors.
2) The firing angle is governed by the intersection of the cosine wave and control signal, providing a linear relationship between output voltage and control signal.
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L14 cosine control scheme
Part of Lecture series on EE321N, Power Electronics-I delivered by me during Fifth Semester of B.Tech. Electrical Engg., 2012
Z H College of Engg. & Technology, Aligarh Muslim University, Aligarh
Please comment and feel free to ask anything related. Thanks!
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3) The scheme uses comparators, flip-flops, and a carrier wave to generate pulse trains that trigger the thyristors at the appropriate firing angles determined by the cosine wave and control signal intersection.
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Part A: Comparators and Switching (5%)
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1. Start at the output and work backwards.
2. Select a latch circuit (flip-flop) and determine what combinations of inputs are needed to
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3. Determine the logic needed to combine two comparator outputs in such a way as to
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4. Choose comparator outputs which will correctly drive the logic. Remember that the
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It is strongly recommended that you assemble and test your circuit.
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2) Darlington transistors have a higher gain than single transistors, alleviating the need for high base drive currents.
3) Proper operation requires that transistors remain in saturation to avoid high power dissipation, and within safe operating areas defined by maximum voltage, current, and power boundaries.
2 transistor thyristor
1. Power bipolar junction transistors and Darlington transistors are high power versions of conventional transistors used as static switches in power electronics. They have current ratings of several hundred amps and voltage ratings of several hundred volts.
2. Darlington transistors have a higher gain than single transistors and are used when higher base currents are needed to adequately turn on the transistor.
3. The safe operating area of a transistor specifies boundaries on its current and voltage ratings to ensure safe operation without damage. Exceeding these boundaries can lead to avalanche breakdown or second breakdown failure mechanisms.
L13 ic based triggering circuit
Part of Lecture series on EE321N, Power Electronics-I delivered by me during Fifth Semester of B.Tech. Electrical Engg., 2012
Z H College of Engg. & Technology, Aligarh Muslim University, Aligarh
Please comment and feel free to ask anything related. Thanks!
Auto selection of any aviliable phase
This document describes a circuit that automatically selects any available phase from a 3 phase power supply system if one phase fails. It uses transformers connected to each phase, rectifiers, regulators, optoisolators, AND gates, inverters, a relay driver, and relays. When one phase fails, the circuit uses logic gates to switch the load to the next available phase through the relay contacts, ensuring continuous power to single phase loads.
SAIKAT-VECC final
The document describes the design of a current to voltage converter for currents in the range of 1 nA to 1 μA. It uses the LMC660 operational amplifier IC with a feedback resistance of 1 MΩ to provide a conversion rate of 1 μA/V. The project objectives, components used, theoretical design, practical implementation on a breadboard, and PCB design are discussed over multiple sections. The current to voltage converter circuit was designed using software and then etched onto a PCB board for implementation.
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A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO
This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltagecontrolled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistorcapacitor (RC) low-pass filter (LPF). By adopting a double-balanced mixer
topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW dc power from 1-V supply voltage.
Research Report-Kaidi Du-EECE4993
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A low power cmos analog circuit design for acquiring multichannel eeg signals
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
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CVT design
The document describes the components and operation of a constant voltage transformer (CVT). A CVT uses a ferroresonant circuit including an inductor, capacitor, and saturable transformer to regulate the output voltage against variations in input voltage, frequency, and load. It provides a constant output voltage through the saturating and limiting action of the saturable transformer. The output is a square wave suitable for rectifier applications. Design equations provided calculate component values, winding turns and sizes, losses, and other parameters for a CVT given specific voltage, power, and frequency specifications.
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L17 equidistant pulse firing scheme
- 1. Time to turn up your Assignments
- 2. Today’s Task (Assigned in Lec-2) Find out • A list of power electronic device manufacturers • Any magazine (Non IEEE) pertaining to PE • Relevant analysis softwares (other than MATLAB) • Read out an article on significance of Power Electronics 217-Nov-15
- 3. EE-321 N Lecture-17 Equidistant Pulse Firing Scheme
- 4. Block Diagram 17-Nov-15 EE-321N, Lec-16 4
- 5. 17-Nov-15 EE-321N, Lec-16 5 Phase Comparator Low Pass Filter Amplifier VCO Counter ÷6N Voltage Comparator Counter ÷N 6 State Ring Counter M/S Decoding Pulse Amplifier To gates of T1 to T6 Vc Fm, v Fc F0= 6NFc PLL
- 6. Description & Working • There are two techniques to control thyristor valves or circuits like Graetz Bridge (3 Phase bridge converter) used in HVDC systems: 1. Individual Phase Control (IPC) 2. Equidistant Pulse Control (EPC) • EPC has replaced IPC due its ability to suppress harmonics 17-Nov-15 EE-321N, Lec-16 6
- 7. Working...contd • Harmonics result from non-equidistant pulses from the firing & control circuit leading to unequal firing angles. • Also the change in line frequency causes appreciable error in the firing angle • In EPC scheme, a single pulse train is generated whose phase can be shifted by a control voltage, Vc 17-Nov-15 EE-321N, Lec-16 7
- 8. Working...contd • This pulse train is then directed to six thyristors through a ring counter, pulse amplifier etc. • The main block is the Phase Locked Loop (PLL) which maintains the o/p frequency of the VCO at 6N times the mains frequency. • Any change in Fm also causes change in VCO frequency 17-Nov-15 EE-321N, Lec-16 8
- 9. Working...contd • The VCO o/p frequency F0 is divided by N to obtain Fc which is compared with and maintained at the same freq. as Fm • There may be phase difference b/w Fc and Fm but this should be as small as possible to minimize any error in the firing angle • If N is the frequency multiplying factor then max. error in equidistant spacing is given by 360°/N. (e. g. N = 600, max. error = 0.6°) 17-Nov-15 EE-321N, Lec-16 9
- 10. Working...contd • The phase control of the pulse train is obtained by comparing the synchronized supply voltage with a control voltage. • The comparator resets the ÷ N counter and a clock pulse is also produced using a M/S. • This pulse resets the ring counter at the end of count 6. The o/p of ring counter is steered through appropriate block to the thyristor gates. 17-Nov-15 EE-321N, Lec-16 10
- 11. (Mine) Course Completes ! 17-Nov-15 EE-321N, Lec-16 11