The document discusses different instruction set architectures including stack, accumulator, memory-memory, register-memory, and load-store architectures. It compares the pros and cons of each in terms of hardware requirements, parallelism, pipelining, and compiler optimization. Instruction formats are classified based on the number of operands and addresses. Code size and number of required memory accesses are compared for 4-address, 3-address, 2-address, 1-address, and 0-address instructions.

1. +
Computer Architecture
CNE-301
Lecturer: Irfan Ali

2. Instruction Set Architecture (ISA)
Memory addressing, instructions, data types, memory architecture, interrupts,
exception handling, external I/O

3. + Instruction Set Architecture (ISA)
• Serves as an interface between software and
hardware.
• Provides a mechanism by which the software tells
the hardware what should be done.
instruction set
High level language code : C, C++, Java, Fortran,
hardware
Assembly language code: architecture specific statements
Machine language code: architecture specific bit patterns
software
compiler
assembler

4. +
Well know ISA’s
 X86 (based on intel 8086 CPU in 1978, Intel family, also
followed by AMD)
 ARM (32-bit & 64-Bit, initially Acorn RISC machine)
 MIPS (32-bit & 64-bit by microprocessor without interlocked
pipeline stages)
 SPARC( 32-bit & 64-bit by sun microsystem)
 PIC (8-bit to 32-bit microchip)
 Z80( 8-bit)

5. + Instruction Set Design Issues
Instruction set design issues include:
 Where are operands stored?
 registers, memory, stack, accumulator
 How many explicit operands are there?
 0, 1, 2, or 3
 How is the operand location specified?
 register, immediate, indirect, . . .
 What type & size of operands are supported?
 byte, int, float, double, string, vector. . .
 What operations are supported?
 add, sub, mul, move, compare . . .

6. + Classifying ISAs
Accumulator (before 1960):
1-address add A acc ¬ acc +
mem[A]
Stack (1960s to 1970s):
0-address add tos ¬ tos + next
Memory-Memory (1970s to 1980s):
2-address add A, B mem[A] ¬
mem[A] + mem[B]
3-address add A, B, C mem[A] ¬
mem[B] + mem[C]

7. +
Register-Memory (1970s to present, e.g. 80x86):
2-address add R1, A R1 ¬ R1 + mem[A]
load R1, A R1 ¬ mem[A]
Register-Register (Load/Store) (1960s to present, e.g. MIPS):
3-address add R1, R2, R3 R1 ¬ R2 + R3
load R1, R2 R1 ¬ mem[R2]
store R1, R2 mem[R1] ¬ R2

8. + Operand Locations in Four ISA
Classes GPR

9. + Code Sequence C = A + B
for Four Instruction Sets
Stack Accumulator Register
(register-memory)
Register
(load-store)
Push A
Push B
Add
Pop C
Load A
Add B
Store C
Load R1, A
Add R1, B
Store C, R1
Load R1,A
Load R2, B
Add R3, R1, R2
Store C, R3
memory memory
acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2

10. + Stack Architectures
 Instruction set:
add, sub, mult, div, . . .
push A, pop A
 Example: A*B - (A+C*B)
push A
push B
mul
push A
push C
push B
mul
add
sub
A B
A
A*B
A*B
A*B
A*B
A
A
C
A*B
A A*B
A C B B*C A+B*C result

11. + Stacks: Pros and Cons
– Pros
– Good code density (implicit top of stack)
– Low hardware requirements
– Easy to write a simpler compiler for stack
architectures
– Cons
– Stack becomes the bottleneck
– Little ability for parallelism or pipelining
– Data is not always at the top of stack when need, so
additional instructions like TOP and SWAP are needed
– Difficult to write an optimizing compiler for stack
architectures

12. Accumulator Architectures
 Instruction set:
add A, sub A, mult A, div A, . . .
load A, store A
 Example: A*B - (A+C*B)
 load B
 mul C
 add A
 store D
 load A
 mul B
 sub D
B B*C A+B*C AA+B*C A*B result
acc = acc +,-,*,/ mem[A]

13. Accumulators: Pros and Cons
●
Pros
 Very low hardware requirements
 Easy to design and understand
●
Cons
 Accumulator becomes the bottleneck
 Little ability for parallelism or
pipelining
 High memory traffic

14. Memory-Memory Architectures
• Instruction set:
(3 operands) add A, B, C sub A, B, C mul A, B, C
(2 operands) add A, B sub A, B mul A, B
• Example: A*B - (A+C*B)
– 3 operands 2 operands
– mul D, A, B mov D, A
– mul E, C, B mul D, B
– add E, A, E mov E, C
– sub E, D, E mul E, B
– add E, A
– sub E, D

15. Memory-Memory: Pros and
Cons
• Pros
– Requires fewer instructions (especially if 3 operands)
– Easy to write compilers for (especially if 3 operands)
• Cons
– Very high memory traffic (especially if 3 operands)
– Variable number of clocks per instruction
– With two operands, more data movements are required

16. Register-Memory Architectures
• Instruction set:
add R1, A sub R1, A mul R1, B
load R1, A store R1, A
• Example: A*B - (A+C*B)
load R1, A
mul R1, B /* A*B */
store R1, D
load R2, C
mul R2, B /* C*B */
add R2, A /* A + CB */
sub R2, D /* AB - (A + C*B) */
R1 = R1 +,-,*,/ mem[B]

17. Memory-Register: Pros and Cons
●
Pros
● Some data can be accessed without loading first
● Instruction format easy to encode
● Good code density
●
Cons
● Operands are not equivalent
● May limit number of registers

18. Load-Store Architectures
• Instruction set:
add R1, R2, R3 sub R1, R2, R3 mul R1, R2, R3
load R1, &A store R1, &A move R1, R2
• Example: A*B - (A+C*B)
load R1, &A
load R2, &B
load R3, &C
mul R7, R3, R2 /* C*B */
add R8, R7, R1 /* A + C*B */
mul R9, R1, R2 /* A*B */
sub R10, R9, R8 /* A*B - (A+C*B) */
R3 = R1 +,-,*,/ R2

19. Load-Store: Pros and Cons
Pros
●
Simple, fixed length instruction encodings
●
Instructions take similar number of cycles
●
Relatively easy to pipeline and make superscalar
Cons
●
Higher instruction count
●
Not all instructions need three operands
●
Dependent on good compiler

20. +
Classification of instructions
4-address instructions
3-address instructions
2-address instructions
1-address instructions
0-address instructions

21. +
Classification of instructions
(continued…)
The 4-address instruction specifies the two
source operands, the destination operand and
the address of the next instruction
op code source 2destination next addresssource 1

22. +
Classification of instructions
(continued…)
A 3-address instruction specifies addresses for
both operands as well as the result
op code source 2destination source 1

23. +Classification of instructions
(continued…)
A 2-address instruction overwrites one operand
with the result
One field serves two purposes
op code destination
source 1
source 2
• A 1-address instruction has a dedicated CPU register,
called the accumulator, to hold one operand & the
result –No address is needed to specify the
accumulator
op code source 2

24. +
Classification of instructions
(continued…)
A 0-address instruction uses a stack to hold
both operands and the result. Operations are
performed between the value on the top of the
stack TOS) and the second value on the stack
(SOS) and the result is stored on the TOS
op code

25. +
Comparison of
instruction formats
As an example assume:
that a single byte is used for the op code
the size of the memory address space is 16
Mbytes
a single addressable memory unit is a byte
Size of operands is 24 bits
Data bus size is 8 bits

26. +
Comparison of
instruction formats
We will use the following two
parameters to compare the five
instruction formats mentioned before
Code size
 Has an effect on the storage requirements
Number of memory accesses
 Has an effect on execution time

27. +
4-address instruction
Code size = 1+3+3+3+3 = 13 bytes
No of bytes accessed from memory
13 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 22 bytes
op code source 2destination next addresssource 1
1 byte 3 bytes 3 bytes 3 bytes3 bytes

28. +
3-address instruction
Code size = 1+3+3+3 = 10 bytes
No of bytes accessed from memory
10 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 19 bytes
1 byte 3 bytes 3 bytes3 bytes
op code source 2destination source 1

29. +
2-address instruction
Code size = 1+3+3 = 7 bytes
No of bytes accessed from memory
7 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 16 bytes
op code destination
source 1
source 2
1 byte 3 bytes3 bytes

30. +
1-address instruction
Code size = 1+3= 4 bytes
No of bytes accessed from memory
4 bytes for instruction fetch +
3 bytes for source operand fetch +
0 bytes for storing destination operand
Total = 7 bytes
1 byte 3 bytes
op code source 2

31. +
0-address instruction
Code size = 1= 1 bytes
# of bytes accessed from memory
1 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 10 bytes
1 byte
op code

32. +
Summary
Instruction Format Code
size
Number of
memory bytes
4-address instruction 13 22
3-address instruction 10 19
2-address instruction 7 16
1-address instruction 4 7
0-address instruction 1 10

33. +
Example 2.1 text
expression evaluation a = (b+c)*d
- e
3-Address 2-Address 1-Address 0-Address
add a, b, c
mpy a, a, d
sub a, a, e
load a, b
add a, c
mpy a, d
sub a, e
lda b
add c
mpy d
sub e
sta a
push b
push c
add
push d
mpy
push e
sub
pop a