The document lists various M.Tech projects in VLSI, focusing on digital circuit design and backend implementations. It includes project ideas such as designing arithmetic logic units, room controllers, and memory cells using Verilog and VHDL. Contact information for further inquiries is provided throughout the document.

1. M tech Projects in VLSI
MINI Project List:contact info- 8130809758, info@siliconmentor.com
Front End Projects (Digital Circuit Design)
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Design of 16 bit Arithmetic logic unit using Verilog HDL
Design of Different real time adders using Verilog HDL
Design of Automatic room controller using Verilog HDL
Design of Digital clock using Verilog HDL
Design of Electronic voting machine using Verilog HDL
Design and implementation of SPI using VHDL/Verilog

2. M tech Projects in VLSI
MINI Project List:contact info- 8130809758, info@siliconmentor.com
Front End Projects (Digital Circuit Design)
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Design of Traffic light controller using VHDL/Verilog
Design of Round Robin arbiter using VHDL/Verilog
Design of Delta to Sigma Convertor using VHDL/Verilog
Design of Barrel shifter using VHDL
Design of Digital Comparator using basic gates using VHDL/Verilog
Design of a candy vending machine controller using Verilog HDL
Design of a Asynchronous FIFO with gray counter using Verilog HDL

3. M tech Projects in VLSI
Major Projects in VLSI & ECE
contact info – 8130809758 ,
info@siliconmentor.com
Frontend Implementation (Digital circuit design)
• Design and Verification of Intel 8255 PPI (Programmable
Peripheral Interface)
• Design & Verification of SPI ( Serial Peripheral Interface)
• Design & Implementation of AMBA AHB Protocol
• Development of PID controlled System based prototype
model for DC voltage conversion system
• Wireless system for fall detection using 3-axis Digital
accelerometer
• Complete prototyping of BPSK system on FPGAs

4. VLSI Backend Projects
Major Projects in VLSI & ECE
contact info – 8130809758 ,
info@siliconmentor.com
• Design & Simulation of SRAM memory cell for multi ported SRAM.
• Hybrid modelling and power analysis of SRAM based register file for 130 nm
technology.
• Reduced leakage based low power SRAM cell for main memory of
microcontrollers.
• Soft error tolerant nanometer scale SRAM memory cell for space applications.
• Multi dimensional party based hamming codes for correcting the SRAM memory
faults under high EMI conditions.
• ASIC cell realization of low power clocked shared paired flip flop.
• Performance Analysis of Modified Feed Through Logic for Low Power and High
Speed
• ESD Detection Circuit for 3*VDD-Tolerant I/O Buffer in Low Voltage CMOS
Processes with Low Leakage Currents.
• Low power CMOS design with sleep transistor for submicron VLSI technologies.