Arithmetic and Logic Unit (ALU) is a vital component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. For the optimization of speed in adders, the most important factor is carry generation. For the implementation of a fast adder, the generated carry should be driven to the output as fast as possible, thereby reducing the worst path delay which determines the ultimate speed of the digital structure. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer that leads to increase of area usage and power consumption. The basic idea of this paper is to use Binary to Excess-1 Converters (BEC) to achieve lower area and power consumption.
Power Efficient and High Speed Carry Skip Adder using Binary to Excess One Co...rahulmonikasharma
The design of high-speed and low-power VLSI architectures need efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption. Adders are the key components in general purpose microprocessors and digital signal processors. As a result, it is very pertinent that its performance augers well for their speed performance. Additionally, the area is an essential factor which is to be taken into account in the design of fast adders. Towards this end, high-speed, low power and area efficient addition and multiplication have always been a fundamental requirement of high-performance processors and systems. The major speed limitation of adders arises from the huge carry propagation delay encountered in the conventional adder circuits, such as ripple carry adder and carry save adder. Observing that a carry may skip any addition stages on certain addend and augend bit values, researchers developed the carry-skip technique to speed up addition in the carry-ripple adder. Using a multilevel structure, carry-skip logic determines whether a carry entering one block may skip the next group of blocks. Because multilevel skip logic introduces longer delays, Therefore, in this paper we examine The basic idea of this work is to use Binary to Excess- 1 converter (BEC) instead of RCA with Cin=1 in conventional CSkA in order to reduce the area and power. BEC uses less number of logic gates than N-bit full adder.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Power Efficient and High Speed Carry Skip Adder using Binary to Excess One Co...rahulmonikasharma
The design of high-speed and low-power VLSI architectures need efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption. Adders are the key components in general purpose microprocessors and digital signal processors. As a result, it is very pertinent that its performance augers well for their speed performance. Additionally, the area is an essential factor which is to be taken into account in the design of fast adders. Towards this end, high-speed, low power and area efficient addition and multiplication have always been a fundamental requirement of high-performance processors and systems. The major speed limitation of adders arises from the huge carry propagation delay encountered in the conventional adder circuits, such as ripple carry adder and carry save adder. Observing that a carry may skip any addition stages on certain addend and augend bit values, researchers developed the carry-skip technique to speed up addition in the carry-ripple adder. Using a multilevel structure, carry-skip logic determines whether a carry entering one block may skip the next group of blocks. Because multilevel skip logic introduces longer delays, Therefore, in this paper we examine The basic idea of this work is to use Binary to Excess- 1 converter (BEC) instead of RCA with Cin=1 in conventional CSkA in order to reduce the area and power. BEC uses less number of logic gates than N-bit full adder.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
A Parallel Computing Model for Segmentation of Vehicle Number Plate through W...theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
A Parallel Computing Model for Segmentation of Vehicle Number Plate through W...theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the
design of this basic adder unit. The speed of operation of a circuit is one of the important performance
criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many
research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The
improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the
previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for
comparative analysis. The coding is done in Verilog hardware description language (HDL) and the
simulation is carried out in Xilinx ISE 13.1 environment.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
Multiplication is the most time consuming process in various signal processing operations like convolution,
circular convolution, auto-correlation and cross-correlation. With advances in technology, many researchers have
tried and are trying to design multipliers which offer either of the following- high speed, low power consumption,
regularity of layout and hence less area or even combination of them in multiplier. However area and speed are
two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best
trade off solution among the both of them. To have features like high speed and low power consumption
multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using various
algorithm in VLSI technology. The Wallace Tree Multipliers are compared with existing multipliers in terms of
improvement in features like area, delay and power consumption by using different logical operation.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
a technical review of efficient and high speed adders for vedic multipliersINFOGAIN PUBLICATION
n the VLSI system design, the main regions of research are the reduced size & increase speed path logic systems. A fundamental requirement of high speed, addition and multiplication is always needed for the high performance digital processors. In the digital system, the speed of addition depend on the propagation of carry, which is generated successively, after the previous bit has been summed & carry is propagated, into the next location. There are numerous types of adders available likes Ripple Carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Avoid Adder, and Carry Select Adder, which have their own benefits and drawbacks. With the advances technology, proposal of Carry select adder (CSA) which deals either of the high speed, low power consumption, regularity of layout a smaller amount area and compact VLSI design implementation. Researchers justify that Ripple Carry Adder had a lesser area but having lesser in speed, in comparing with Carry Select Adders are fastest speed but possess a larger area. The Carry Look Ahead Adder is in between the spectrum having proper trade-offs between time and area complexities.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
Multiplications and additions are most widely and more often used arithmetic computations performed in
all digital signal processing applications. Addition is the basic operation for many digital application. The
aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system
is mainly influenced by the performance of the adders. Multipliers are also very important component in
digital systems
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Data Mining is a significant field in today’s data-driven world. Understanding and implementing its concepts can lead to discovery of useful insights. This paper discusses the main concepts of data mining, focusing on two main concepts namely Association Rule Mining and Time Series Analysis
A Review on Real Time Integrated CCTV System Using Face Detection for Vehicle...rahulmonikasharma
We are describes the technique for real time human face detection and counting the number of passengers in vehicle and also gender of the passengers.The Image processing technology is very popular,now at present all are going to use it for various purpose. It can be applied to various applications for detecting and processing the digital images. Face detection is a part of image processing. It is used for finding the face of human in a given area. Face detection is used in many applications such as face recognition, people tracking, or photography. In this paper,The webcam is installed in public vehicle and connected with Raspberry Pi model. We use face detection technique for detecting and counting the number of passengers in public vehicle via webcam with the help of image processing and Raspberry Pi.
Considering Two Sides of One Review Using Stanford NLP Frameworkrahulmonikasharma
Sentiment analysis is a type of natural language processing for tracking the mood of the public about a particular product or a topic and is useful in several ways. Polarity shift is the most classical task which aims at classifying the reviews either positive or negative. But in many cases, in addition to the positive and negative reviews, there still many neutral reviews exist. However, the performance sometimes limited due to the fundamental deficiencies in handling the polarity shift problem. We propose an Improvised Dual Sentiment Analysis (IDSA) model to address this problem for sentiment classification. We first propose a novel data expansion technique by creating sentiment-reversed review for each training and test review. We develop a corpus based method to construct a pseudo-antonym dictionary. It removes DSA’s dependency on an external antonym dictionary for review reversion. We conduct a range of experiments and the results demonstrates the effectiveness of DSA in addressing the polarity shift in sentiment classification. .
A New Detection and Decoding Technique for (2×N_r ) MIMO Communication Systemsrahulmonikasharma
The requirements of fifth generation new radio (5G- NR) access networks are very high capacity and ultra-reliability. In this paper, we proposed a V-BLAST2 × N_r MIMO system that is analyzed, improved, and expected to achieve both very high throughput and ultra- reliability simultaneously.A new detection technique called parallel detection algorithm is proposed. The performance of the proposed algorithm compared with existing linear detection algorithms. It was seen that the proposed technique increases the speed of signal transmission and prevents error propagation which may be present in serial decoding techniques. The new algorithm reduces the bit error probability and increases the capacity simultaneouslywithout using a standard STC technique. However, it was seen that the BER of systems using the proposed algorithm is slightly higher than a similar system using only STC technique. Simulation results show the advantages of using the proposed technique.
Broadcasting Scenario under Different Protocols in MANET: A Surveyrahulmonikasharma
A wireless network enables people to communicate and access applications and information without wires. This provides freedom of movement and the ability to extend applications to different parts of a building, city, or nearly anywhere in the world. Wireless networks allow people to interact with e-mail or browse the Internet from a location that they prefer. Adhoc Networks are self-organizing wireless networks, absent any fixed infrastructure. broadcasting of data through proper channel is essential. Various protocols are designed to avoid the loss of data. In this paper an overview of different broadcast protocols are discussed.
Sybil Attack Analysis and Detection Techniques in MANETrahulmonikasharma
Security is important for many sensor network applications. A particularly harmful attack against sensor and ad hoc networks is known as the Sybil attack [6], where a node Illegitimately claims multiple identities.Mobility cause a main problem when we talk about security in Mobile Ad-hoc networks. It doesn’t depend on fixed architecture, the nodes are continuously moving in a random fashion. In this article we will focus on identifying the Sybil attack in MANET. It uses air medium for communication so it is more prone to the attack. Sybil attack is one in which single node present multiple fake identities to other nodes, which cause destruction.
A Landmark Based Shortest Path Detection by Using A* and Haversine Formularahulmonikasharma
In 1900, less than 20 percent of the world populace lived in cities, in 2007, fair more than 50 percent of the world populace lived in cities. In 2050, it has been anticipated that more than 70 percent of the worldwide population (about 6.4 billion individuals) will be city tenants. There's more weight being set on cities through this increment in population [1]. With approach of keen cities, data and communication technology is progressively transforming the way city regions and city inhabitants organize and work in reaction to urban development. In this paper, we create a nonspecific plot for navigating a route throughout city A asked route is given by utilizing combination of A* Algorithm and Haversine equation. Haversine Equation gives least distance between any two focuses on spherical body by utilizing latitude and longitude. This least distance is at that point given to A* calculation to calculate minimum distance. The method for identifying the shortest path is specify in this paper.
Processing Over Encrypted Query Data In Internet of Things (IoTs) : CryptDBs,...rahulmonikasharma
Internet of Things (IoT) is the developing technologies that would be the biggest agents to modify the current world. Machine-to-machine communications perform with virtual, mobile and instantaneous connections. In IoT system, it consists of data-gathering sensors various other household devices. Intended for protecting IoT system, the end-to-end secure communication is a necessary measure to protect against unauthorized entities (e.g., modification attacks and eavesdropping,) and the data unprotected on the Cloud. The most important concern hereby is how to preserve the insightful information and to provide the privacy of user data. In IoT, the encrypted data computing is based on techniques appear to be promising approaches. In this paper, we discuss about the recent secure database systems, which are capable to execute SQL queries over encrypted data.
Quality Determination and Grading of Tomatoes using Raspberry Pirahulmonikasharma
In India cultivation of tomatoes is carried out by traditional methods and techniques. Today tremendous improvement in field of agriculture technologies and products can be seen. The tomatoes affect the overall production drastically. Image processing technique can be key technique for finding good qualities of tomatoes and grading. This work aimed to study different types of algorithms used for quality grading and sorting of fruit from the acquire image. In previous years several types of techniques are applied to analyses the good quality fruits. A simple system can be implemented using Raspberry pi with computer vision technology and image processing algorithms.
Comparative of Delay Tolerant Network Routings and Scheduling using Max-Weigh...rahulmonikasharma
Network management and Routing is supportively done by performing with the nodes, due to infrastructure-less nature of the network in Ad hoc networks or MANET. The nodes are maintained itself from the functioning of the network, for that reason the MANET security challenges several defects. Routing process and Scheduling is a significant idea to enhance the security in MANET. Other than, scheduling has been recognized to be a key issue for implementing throughput/capacity optimization in Ad hoc networks. Designed underneath conventional (LT) light tailed assumptions, traffic fundamentally faces Heavy-tailed (HT) assumption of the validity of scheduling algorithms. Scheduling policies are utilized for communication networks such as Max-Weight, backpressure and ACO, which are provably throughput optimality and the Pareto frontier of the feasible throughput region under maximal throughput vector. In wireless ad-hoc network, the issue of routing and optimal scheduling performs with time varying channel reliability and multiple traffic streams. Depending upon the security issues within MANETs in this paper presents a comparative analysis of existing scheduling policies based on their performance to progress the delay performance in most scenarios. The security issues of MANETs considered from this paper presents a relative analysis of existing scheduling policies depend on their performance to progress the delay performance in most developments.
DC Conductivity Study of Cadmium Sulfide Nanoparticlesrahulmonikasharma
The dc conductivity of consolidated nanoparticle of CdS has been studied over the temperature range from 303 K to 523 K and the conductivity has been found to be much larger than that of single crystals.
A Survey on Peak to Average Power Ratio Reduction Methods for LTE-OFDMrahulmonikasharma
OFDM (Orthogonal Frequency Division Multiplexing) is generally preferred for high data rate transmission in digital communication. The Long-Term Evolution (LTE) standards for the fourth generation (4G) wireless communication systems. Orthogonal Frequency Division Multiple Access (OFDMA) and Single Carrier Frequency Division Multiple Access (SC-FDMA) are the two multiple access techniques which are generally used in LTE.OFDM system has a major shortcoming of high peak to average power ratio (PAPR) value. This paper explains different PAPR reduction techniques and presents a comparison of the various techniques based on theoretical results. It also presents a survey of the various PAPR reduction techniques and the state of the art in this area.
IOT Based Home Appliance Control System, Location Tracking and Energy Monitoringrahulmonikasharma
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High Speed and Low Power Consumption Carry Skip Adder using Binary to Excess-One Converter
1. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 595 – 598
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High Speed and Low Power Consumption Carry Skip Adder using Binary to
Excess-One Converter
Sanyukta Vijaykumar Chahande
Research Scholar (M. Tech), Dept of ECE
Anjuman College of Engineering and Technology
Nagpur, India
sanyuktavchahande@gmail.com
Prof. Mohammad Nasiruddin
Associate. Professor & Head of ECE Dept
Anjuman College of Engineering and Technology
Nagpur, India
mn151819@gmail.com
Abstract—Arithmetic and Logic Unit (ALU) is a vital component of any CPU. In ALU, adders play a major role not only in addition but also in
performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better
performance of an ALU and therefore the processor. For the optimization of speed in adders, the most important factor is carry generation. For
the implementation of a fast adder, the generated carry should be driven to the output as fast as possible, thereby reducing the worst path delay
which determines the ultimate speed of the digital structure. In conventional carry skip adder the multiplexer is used as a skip logic that provides
a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may
be a large critical path delay revealed by the multiplexer that leads to increase of area usage and power consumption. The basic idea of this paper
is to use Binary to Excess-1 Converters (BEC) to achieve lower area and power consumption.
Keywords- Arithmetic and Logic Unit(ALU), Carry Skip Adder, Binary to Excess-1 Converters(BEC)
__________________________________________________*****_________________________________________________
I. INTRODUCTION
Well expressed in words that if you can count, you can control.
Addition is a basic operation for any digital system, digital
signal processing or control system. A fast and accurate
operation of a digital system is greatly influenced by the
performance of the adders. Adders are also very important
component in digital systems because of their extensive use in
other basic digital operations such as subtraction, multiplication
and division. Hence, improving performance of the digital
adder would greatly advance the execution of binary operations
inside a circuit compromised of such blocks. The performance
of a digital circuit block is gauged by analyzing its power
dissipation, layout area and its operating speed.Addition is an
indispensable operation for any high speed digital system,
digital signal processing or control system.Therefore pertinent
choice of adder topologies is an essentialimportance in the
design of VLSI integrated circuits for high speed and high
performance circuits.
II. TYPE OF ADDERS
The design of various adders such as Ripple Carry Adder
(RCA),Carry Increment Adder (CIA), CarryLook Ahead
Adder (CLA), Carry Save Adder (CSA), Carry SelectAdder
(CSLA) and Carry Skip Adder (CSkA) are discussed below.
A. Ripple carry Adder(RCA)
Ripple Carry Adder (RCA) is a basic adder which works on
basic addition principle [1]. The architecture of RCA is shown
in figure below. RCA contains series structure of Full Adders
(FA); each FA is used to add two bits along with carry bit.
The carry generated from each full adder is given to next full
adder and so on. Hence, the carry is propagated in a serial
computation[1]. Hence, delay is more as the number of bits is
increased in RCA.
B. Carry Increment Adder(CIA)
The design of Carry Increment Adder (CIA) consists of
RCA’s andincremental circuitry [1]. The incremental circuit
can be designedusing HA’s in ripple carry chain with a
sequential order. Theaddition operation is done by dividing
total number of bits in togroup of 4bits and addition operation
is done using several 4bit RCA’s. The architecture of CIA is
C. Carry Look Aheah Adder(CLA)
As seen in the ripple-carry adder, its limiting factor is the time
it takes to propagate the carry. The carry look-ahead adder
2. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 595 – 598
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solves this problem by calculating the carry signals in advance,
based on the input signals. The result is a reduced carry
propagation time.To be able to understand how the carry look-
ahead adder works, we have to manipulate the Boolean
expression dealing with the full adder. The Propagate P and
generate G in a full-adder, is given as:
Pi = Ai XOR Bi Carry propagate
Gi = AiBi Carry generate
Notice that both propagate and generate signals depend only on
the input bits and thus will be valid after one gate delay.
The new expressions for the output sum and the carryout are
given by:
Si = Pi Ci-1
Ci+1= Gi + PiCi
These equations show that a carry signal will be generated in
two cases:
1) if both bits Ai and Bi are 1
2) if either Ai or Bi is 1 and the carry-in Ci is 1.
D. Carry Save Adder(CSA)
In Carry Save Adder (CSA), three bits are added parallelly at
a time. In this scheme, the carry is not propagated through the
stages. Instead, carry is stored in present stage, and updated as
addend value in the next stage. Hence, the delay due to the
carry is reduced in this scheme. The architecture of CSA is
shown in figure
E. Carry Select Adder(CSLA)
Carry Select Adder (CSLA) architecture consists of
independent generation of sum and carry i.e., Cin=1 and
Cin=0 executed parallelly. Depending upon Cin, the external
multiplexers select the carry to be propagated to next stage.
Further, based on the carry input, the sum will be selected.
F. Carry Skip Adder(CSkA)
As the name indicates, Carry Skip Adder (CSkA) uses skip
logic in the propagation of carry. It is designed to speed up
theaddition operation by adding a propagation of carry bit
around aportion of entire adder. Figure shows the architecture
of CSkA.
III. PRIOR WORK
The conventional structure of the CSKA consists of stages
containing chain of full adders (FAs) (RCA block) and 2:1
multiplexer (carry skip logic). The RCA blocks are connected
to each other through 2:1 multiplexers, which can be placed
into one or more level structures [19]. The CSKA
configuration (i.e., the number of the FAs per stage) has a
great impact on the speed of this type of adder [23]. Many
3. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 595 – 598
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methods have been suggested for finding the optimum number
of the FAs [18]–[26]. The techniques presented in [19]–[24]
make use of VSSs to minimize the delay of adders based on a
single level carry skip logic. In [25], some methods to increase
the speed of the multilevel CSKAs are proposed. The
techniques, however, cause area and power increase
considerably and less regular layout.
The CSka with AOI/OAI logic structure is based on
combining the concatenation and the incrementation schemes
[13] with the Conv-CSKA structure, and hence, is denoted by
CI-CSKA. It provides us with the ability to use simpler carry
skip logics. The logic replaces2:1 multiplexers by AOI/OAI
compound gates (Fig. 2). The gates, which consist of fewer
transistors, have lower delay ,area, and smaller power
consumption compared with those of the 2:1 multiplexer [37].
Note that, in this structure, as the carry propagates through the
skip logics, it becomes complemented. Therefore, at the output
of the skip logic of even stages, the complement of the carry is
generated. The structure has a considerable lower propagation
delay with as lightly smaller area compared with those of the
conventional one. Note that while the power consumptions of
the AOI(or OAI) gate are smaller than that of the multiplexer,
the power consumption of the proposed CI-CSKA is a little
more than that of the conventional one. This is due to the
increase in the number of the gates.
IV. PROPOSED WORK
Based on the discussion presented in Section III, it is
concluded that by reducing the delay of the skip logic, one
may lower the propagation delay of the CSKA significantly.
Hence, in this paper, we present a modified CSKA structure
that reduces this delay.
The basic idea of this work is to use Binary to Excess- 1
converter (BEC) instead of RCA with Cin=1 in conventional
CSLA in order to reduce the area and power.BEC uses less
number of logic gates than N-bit full adder structure. To
replace N bit RCA, an N+1 bit BEC is required. Therefore,
Modified CSkA has low power and less area than conventional
CSkA.
4. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 595 – 598
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V. CONCLUSION
In this paper, Carry Skip Adder (CSKA) structure was
proposed, which exhibits a higher speed and lower energy
consumption compared with the conventional structure. The
speed is through the use of Binary to Excess One converter for
the carry skip logics. The results also suggested that the CSKA
structure is a very good adder for the applications where both
the speed and energy consumption are critical. In addition, a
modified structure was proposed which reduces power
consumption without affecting the delay of the structures.
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