The design of high-speed and low-power VLSI architectures need efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption. Adders are the key components in general purpose microprocessors and digital signal processors. As a result, it is very pertinent that its performance augers well for their speed performance. Additionally, the area is an essential factor which is to be taken into account in the design of fast adders. Towards this end, high-speed, low power and area efficient addition and multiplication have always been a fundamental requirement of high-performance processors and systems. The major speed limitation of adders arises from the huge carry propagation delay encountered in the conventional adder circuits, such as ripple carry adder and carry save adder. Observing that a carry may skip any addition stages on certain addend and augend bit values, researchers developed the carry-skip technique to speed up addition in the carry-ripple adder. Using a multilevel structure, carry-skip logic determines whether a carry entering one block may skip the next group of blocks. Because multilevel skip logic introduces longer delays, Therefore, in this paper we examine The basic idea of this work is to use Binary to Excess- 1 converter (BEC) instead of RCA with Cin=1 in conventional CSkA in order to reduce the area and power. BEC uses less number of logic gates than N-bit full adder.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
a technical review of efficient and high speed adders for vedic multipliersINFOGAIN PUBLICATION
n the VLSI system design, the main regions of research are the reduced size & increase speed path logic systems. A fundamental requirement of high speed, addition and multiplication is always needed for the high performance digital processors. In the digital system, the speed of addition depend on the propagation of carry, which is generated successively, after the previous bit has been summed & carry is propagated, into the next location. There are numerous types of adders available likes Ripple Carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Avoid Adder, and Carry Select Adder, which have their own benefits and drawbacks. With the advances technology, proposal of Carry select adder (CSA) which deals either of the high speed, low power consumption, regularity of layout a smaller amount area and compact VLSI design implementation. Researchers justify that Ripple Carry Adder had a lesser area but having lesser in speed, in comparing with Carry Select Adders are fastest speed but possess a larger area. The Carry Look Ahead Adder is in between the spectrum having proper trade-offs between time and area complexities.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
High Speed and Low Power Consumption Carry Skip Adder using Binary to Excess-...rahulmonikasharma
Arithmetic and Logic Unit (ALU) is a vital component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. For the optimization of speed in adders, the most important factor is carry generation. For the implementation of a fast adder, the generated carry should be driven to the output as fast as possible, thereby reducing the worst path delay which determines the ultimate speed of the digital structure. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer that leads to increase of area usage and power consumption. The basic idea of this paper is to use Binary to Excess-1 Converters (BEC) to achieve lower area and power consumption.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
a technical review of efficient and high speed adders for vedic multipliersINFOGAIN PUBLICATION
n the VLSI system design, the main regions of research are the reduced size & increase speed path logic systems. A fundamental requirement of high speed, addition and multiplication is always needed for the high performance digital processors. In the digital system, the speed of addition depend on the propagation of carry, which is generated successively, after the previous bit has been summed & carry is propagated, into the next location. There are numerous types of adders available likes Ripple Carry Adder, Carry Look Ahead Adder, Carry Save Adder, Carry Avoid Adder, and Carry Select Adder, which have their own benefits and drawbacks. With the advances technology, proposal of Carry select adder (CSA) which deals either of the high speed, low power consumption, regularity of layout a smaller amount area and compact VLSI design implementation. Researchers justify that Ripple Carry Adder had a lesser area but having lesser in speed, in comparing with Carry Select Adders are fastest speed but possess a larger area. The Carry Look Ahead Adder is in between the spectrum having proper trade-offs between time and area complexities.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
High Speed and Low Power Consumption Carry Skip Adder using Binary to Excess-...rahulmonikasharma
Arithmetic and Logic Unit (ALU) is a vital component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. For the optimization of speed in adders, the most important factor is carry generation. For the implementation of a fast adder, the generated carry should be driven to the output as fast as possible, thereby reducing the worst path delay which determines the ultimate speed of the digital structure. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer that leads to increase of area usage and power consumption. The basic idea of this paper is to use Binary to Excess-1 Converters (BEC) to achieve lower area and power consumption.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
High –Speed Implementation of Design and Analysis by Using Parallel Prefix Ad...IOSRJECE
The binary adder is the critical element in most digital circuit designs including the digital signal processors (DSP) and microprocessor data unit path. As such as extensive research continues to be focused on improving the power, delay, improvement of the adder. The design and analysis of the parallel prefix adders (carry select adders) is to be implemented by using Verilog. In VLSI implementations, parallel prefix adders are very high speed performance. Binary adders are one of the most essential logic elements within a digital system. Therefore, binary addition is essential that any improvement in binary addition can result in a performance boost for any computing system and hence, help improve the performance of the entire system. Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. This paper investigates (the Kogge-Stone, sparse Kogge-Stone, Ladner fischer adder, Brent-Kung adder) and compares them to the simple Ripple Carry Adder (RCA) for high number of binary bits.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Adders are one of the most widely digital
components in the digital integrated circuit design and are the
necessary part of Digital Signal Processing (DSP) applications.
With the advances in technology, researchers have tried and are
trying to design adders which offer either high speed, low power
consumption, less area or the combination of them. The addition
of the two bits is very Based on the various speed-up schemes for
binary addition, a comprehensive overview and a qualitative
evaluation of the different existing basic adder architectures are
given in this paper. In addition, their comparison is performed in
the thesis for the performance analysis. We will synthesize the
adders - Ripple Carry adder, Carry look- ahead Adder, Carry
Save Adder in ISE XIILINX 10.1 by using HDL - Verilog and
will simulate them in Modelsim 6.4a. We will Compare above
mentioned adders in terms of Delay, Slices Used and Look up
tables used by the adder architecture.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast ...Kumar Goud
Abstract— Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process; one of them is Wallace tree multiplier. Wallace Tree CSA structures have been used to sum the partial products in reduced time. In this paper Wallace tree construction is investigated and evaluated. Speed of traditional Wallace tree multiplier can be improved by using compressor techniques. In this paper Wallace tree is constructed by traditional method and with the help of compressor techniques such as 4:2 compressor, 5:2 compressor, 6:2 compressor, 7:2 compressor. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity.
Index Terms—Component, formatting, style, styling, insert. (key words)
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
Data Mining is a significant field in today’s data-driven world. Understanding and implementing its concepts can lead to discovery of useful insights. This paper discusses the main concepts of data mining, focusing on two main concepts namely Association Rule Mining and Time Series Analysis
A Review on Real Time Integrated CCTV System Using Face Detection for Vehicle...rahulmonikasharma
We are describes the technique for real time human face detection and counting the number of passengers in vehicle and also gender of the passengers.The Image processing technology is very popular,now at present all are going to use it for various purpose. It can be applied to various applications for detecting and processing the digital images. Face detection is a part of image processing. It is used for finding the face of human in a given area. Face detection is used in many applications such as face recognition, people tracking, or photography. In this paper,The webcam is installed in public vehicle and connected with Raspberry Pi model. We use face detection technique for detecting and counting the number of passengers in public vehicle via webcam with the help of image processing and Raspberry Pi.
Considering Two Sides of One Review Using Stanford NLP Frameworkrahulmonikasharma
Sentiment analysis is a type of natural language processing for tracking the mood of the public about a particular product or a topic and is useful in several ways. Polarity shift is the most classical task which aims at classifying the reviews either positive or negative. But in many cases, in addition to the positive and negative reviews, there still many neutral reviews exist. However, the performance sometimes limited due to the fundamental deficiencies in handling the polarity shift problem. We propose an Improvised Dual Sentiment Analysis (IDSA) model to address this problem for sentiment classification. We first propose a novel data expansion technique by creating sentiment-reversed review for each training and test review. We develop a corpus based method to construct a pseudo-antonym dictionary. It removes DSA’s dependency on an external antonym dictionary for review reversion. We conduct a range of experiments and the results demonstrates the effectiveness of DSA in addressing the polarity shift in sentiment classification. .
A New Detection and Decoding Technique for (2×N_r ) MIMO Communication Systemsrahulmonikasharma
The requirements of fifth generation new radio (5G- NR) access networks are very high capacity and ultra-reliability. In this paper, we proposed a V-BLAST2 × N_r MIMO system that is analyzed, improved, and expected to achieve both very high throughput and ultra- reliability simultaneously.A new detection technique called parallel detection algorithm is proposed. The performance of the proposed algorithm compared with existing linear detection algorithms. It was seen that the proposed technique increases the speed of signal transmission and prevents error propagation which may be present in serial decoding techniques. The new algorithm reduces the bit error probability and increases the capacity simultaneouslywithout using a standard STC technique. However, it was seen that the BER of systems using the proposed algorithm is slightly higher than a similar system using only STC technique. Simulation results show the advantages of using the proposed technique.
Broadcasting Scenario under Different Protocols in MANET: A Surveyrahulmonikasharma
A wireless network enables people to communicate and access applications and information without wires. This provides freedom of movement and the ability to extend applications to different parts of a building, city, or nearly anywhere in the world. Wireless networks allow people to interact with e-mail or browse the Internet from a location that they prefer. Adhoc Networks are self-organizing wireless networks, absent any fixed infrastructure. broadcasting of data through proper channel is essential. Various protocols are designed to avoid the loss of data. In this paper an overview of different broadcast protocols are discussed.
Sybil Attack Analysis and Detection Techniques in MANETrahulmonikasharma
Security is important for many sensor network applications. A particularly harmful attack against sensor and ad hoc networks is known as the Sybil attack [6], where a node Illegitimately claims multiple identities.Mobility cause a main problem when we talk about security in Mobile Ad-hoc networks. It doesn’t depend on fixed architecture, the nodes are continuously moving in a random fashion. In this article we will focus on identifying the Sybil attack in MANET. It uses air medium for communication so it is more prone to the attack. Sybil attack is one in which single node present multiple fake identities to other nodes, which cause destruction.
A Landmark Based Shortest Path Detection by Using A* and Haversine Formularahulmonikasharma
In 1900, less than 20 percent of the world populace lived in cities, in 2007, fair more than 50 percent of the world populace lived in cities. In 2050, it has been anticipated that more than 70 percent of the worldwide population (about 6.4 billion individuals) will be city tenants. There's more weight being set on cities through this increment in population [1]. With approach of keen cities, data and communication technology is progressively transforming the way city regions and city inhabitants organize and work in reaction to urban development. In this paper, we create a nonspecific plot for navigating a route throughout city A asked route is given by utilizing combination of A* Algorithm and Haversine equation. Haversine Equation gives least distance between any two focuses on spherical body by utilizing latitude and longitude. This least distance is at that point given to A* calculation to calculate minimum distance. The method for identifying the shortest path is specify in this paper.
Processing Over Encrypted Query Data In Internet of Things (IoTs) : CryptDBs,...rahulmonikasharma
Internet of Things (IoT) is the developing technologies that would be the biggest agents to modify the current world. Machine-to-machine communications perform with virtual, mobile and instantaneous connections. In IoT system, it consists of data-gathering sensors various other household devices. Intended for protecting IoT system, the end-to-end secure communication is a necessary measure to protect against unauthorized entities (e.g., modification attacks and eavesdropping,) and the data unprotected on the Cloud. The most important concern hereby is how to preserve the insightful information and to provide the privacy of user data. In IoT, the encrypted data computing is based on techniques appear to be promising approaches. In this paper, we discuss about the recent secure database systems, which are capable to execute SQL queries over encrypted data.
Quality Determination and Grading of Tomatoes using Raspberry Pirahulmonikasharma
In India cultivation of tomatoes is carried out by traditional methods and techniques. Today tremendous improvement in field of agriculture technologies and products can be seen. The tomatoes affect the overall production drastically. Image processing technique can be key technique for finding good qualities of tomatoes and grading. This work aimed to study different types of algorithms used for quality grading and sorting of fruit from the acquire image. In previous years several types of techniques are applied to analyses the good quality fruits. A simple system can be implemented using Raspberry pi with computer vision technology and image processing algorithms.
Comparative of Delay Tolerant Network Routings and Scheduling using Max-Weigh...rahulmonikasharma
Network management and Routing is supportively done by performing with the nodes, due to infrastructure-less nature of the network in Ad hoc networks or MANET. The nodes are maintained itself from the functioning of the network, for that reason the MANET security challenges several defects. Routing process and Scheduling is a significant idea to enhance the security in MANET. Other than, scheduling has been recognized to be a key issue for implementing throughput/capacity optimization in Ad hoc networks. Designed underneath conventional (LT) light tailed assumptions, traffic fundamentally faces Heavy-tailed (HT) assumption of the validity of scheduling algorithms. Scheduling policies are utilized for communication networks such as Max-Weight, backpressure and ACO, which are provably throughput optimality and the Pareto frontier of the feasible throughput region under maximal throughput vector. In wireless ad-hoc network, the issue of routing and optimal scheduling performs with time varying channel reliability and multiple traffic streams. Depending upon the security issues within MANETs in this paper presents a comparative analysis of existing scheduling policies based on their performance to progress the delay performance in most scenarios. The security issues of MANETs considered from this paper presents a relative analysis of existing scheduling policies depend on their performance to progress the delay performance in most developments.
DC Conductivity Study of Cadmium Sulfide Nanoparticlesrahulmonikasharma
The dc conductivity of consolidated nanoparticle of CdS has been studied over the temperature range from 303 K to 523 K and the conductivity has been found to be much larger than that of single crystals.
A Survey on Peak to Average Power Ratio Reduction Methods for LTE-OFDMrahulmonikasharma
OFDM (Orthogonal Frequency Division Multiplexing) is generally preferred for high data rate transmission in digital communication. The Long-Term Evolution (LTE) standards for the fourth generation (4G) wireless communication systems. Orthogonal Frequency Division Multiple Access (OFDMA) and Single Carrier Frequency Division Multiple Access (SC-FDMA) are the two multiple access techniques which are generally used in LTE.OFDM system has a major shortcoming of high peak to average power ratio (PAPR) value. This paper explains different PAPR reduction techniques and presents a comparison of the various techniques based on theoretical results. It also presents a survey of the various PAPR reduction techniques and the state of the art in this area.
IOT Based Home Appliance Control System, Location Tracking and Energy Monitoringrahulmonikasharma
Home automation has been a dream of sciences for so many years. It could wind up conceivable in twentieth century simply after power all family units and web administrations were begun being utilized on across the board level. The point of home robotization is to give enhanced accommodation, comfort, vitality effectiveness and security. Vitality checking and protection holds prime significance in this day and age in view of the irregularity between control age and request observing frameworks accessible in the market. Ordinarily, customers are disappointed with the power charge as it doesn't demonstrate the power devoured at the gadget level. This paper shows the outline and execution of a vitality meter utilizing Arduino microcontroller which can be utilized to gauge the power devoured by any individual electrical apparatus. The primary expectation of the proposed vitality meter is to screen the power utilization at the gadget level, transfer it to the server and build up remote control of any apparatus. So we can screen the power utilization remotely and close down gadgets if vital. The car segment is additionally one of the application spaces where vehicle can be made keen by utilizing "IOT". So a vehicle following framework is additionally executed to screen development of vehicles remotely.
Thermal Radiation and Viscous Dissipation Effects on an Oscillatory Heat and ...rahulmonikasharma
An anticipated outcome that is intended chapter is to investigate effects of magnetic field on an oscillatory flow of a viscoelastic fluid with thermal radiation, viscous dissipation with Ohmic heating which bounded by a vertical plane surface, have been studied. Analytical solutions for the quasi – linear hyperbolic partial differential equations are obtained by perturbation technique. Solutions for velocity and temperature distributions are discussed for various values of physical parameters involving in the problem. The effects of cooling and heating of a viscoelastic fluid compared to the Newtonian fluid have been discussed.
Advance Approach towards Key Feature Extraction Using Designed Filters on Dif...rahulmonikasharma
In fast growing database repository system, image as data is one of the important concern despite text or numeric. Still we can’t replace test on any cost but for advancement, information may be managed with images. Therefore image processing is a wide area for the researcher. Many stages of processing of image provide researchers with new ideas to keep information safe with better way. Feature extraction, segmentation, recognition are the key areas of the image processing which helps to enhance the quality of working with images. Paper presents the comparison between image formats like .jpg, .png, .bmp, .gif. This paper is focused on the feature extraction and segmentation stages with background removal process. There are two filters, one is integer filter and second one is floating point Filter, which is used for the key feature extraction from image. These filters applied on the different images of different formats and visually compare the results.
Alamouti-STBC based Channel Estimation Technique over MIMO OFDM Systemrahulmonikasharma
The examination on various looks into on MIMO STBC framework in order to accomplish the higher framework execution is standard that the execution of the remote correspondence frameworks can be improved by usage numerous transmit and get radio wires, that is normally gathered on the grounds that the MIMO procedure, and has been incorporated. The Alamouti STBC might be a promising because of notice the pick up inside the remote interchanges framework misuse MIMO. To broaden the code rate and furthermore the yield of the symmetrical zone time square code for more than 4 transmit reception apparatuses is examined. The outlined framework is beated once forced with M-PSK (i.e upto 32-PSK) regulation. The channel estimation examine in these conditions.
Empirical Mode Decomposition Based Signal Analysis of Gear Fault Diagnosisrahulmonikasharma
A vibration investigation is about the specialty of searching for changes in the vibration example, and after that relating those progressions back to the machines mechanical outline. The level of vibration and the example of the vibration reveal to us something about the interior state of the turning segment. The vibration example can let us know whether the machine is out of adjust or twisted. Al-so blames with the moving components and coupling issues can be distinguished. This paper shows an approach for equip blame investigation utilizing signal handling plans. The information has been taken from college of ohio, joined states. The investigation has done utilizing MATLAB software.
This paper discusses a new algorithm of a univariate method, which is vitally important to develop a short-term load forecasting module for planning and operation of distribution system. It has many applications including purchasing of energy, generation and infrastructure development etc. We have discussed different time series forecasting approaches in this paper. But ARIMA has proved itself as the most appropriate method in forecasting of the load profile for West Bengal using the historical data of the year of 2017. Auto Regressive Integrated Moving Average model gives more accuracy level of load forecast than any other techniques. Mean Absolute Percentage Error (MAPE) has been calculated for the mentioned forecasted model.
Impact of Coupling Coefficient on Coupled Line Couplerrahulmonikasharma
The coupled line coupler is a type of directional coupler which finds practical utility. It is mainly used for sampling the microwave power. In this paper, 3 couplers A,B & C are designed with different values of coupling coefficient 6dB,10dB & 18dB respectively at a frequency of 2.5GHz using ADS tool. The return loss, isolation loss & transmission loss are determined. The design & simulation is done using microstrip line technology.
Design Evaluation and Temperature Rise Test of Flameproof Induction Motorrahulmonikasharma
The ignition of flammable gases, vapours or dust in presence of oxygen contained in the surrounding atmosphere may lead to explosion. Flameproof three phase induction motors are the most common and frequently used in the process industries such as oil refineries, oil rigs, petrochemicals, fertilizers, etc. The design of flameproof motor is such that it allows and sustain explosion within the enclosure caused by ignition of hazardous gases without transmitting it to the external flammable atmosphere. The enclosure is mechanically strong enough to withstand the explosion pressure developed inside it. To prevent an explosion due to hot spot on the surface of the motor, flameproof induction motors are subjected to heat run test to determine the maximum surface temperature and temperature class with respect to the ignition temperature of the surrounding flammable gas atmosphere. This paper highlights the design features of flameproof motors and their surface temperature classification for different sizes.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
#vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore#blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #blackmagicforlove #blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #Amilbabainuk #amilbabainspain #amilbabaindubai #Amilbabainnorway #amilbabainkrachi #amilbabainlahore #amilbabaingujranwalan #amilbabainislamabad
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Power Efficient and High Speed Carry Skip Adder using Binary to Excess One Converter
1. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 637 – 641
_______________________________________________________________________________________________
637
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Power Efficient and High Speed Carry Skip Adder using Binary to Excess One
Converter
Sanyukta Vijaykumar Chahande
Research Scholar (M.tech), Dept of ECE
Anjuman College of Engineering and Technology
Nagpur, India
sanyuktavchahande@gmail.com
Prof. Mohammad Nasiruddin
Associate. Professor & Head of Dept. of ECE
Anjuman College Of Engineering and Technology
Nagpur, India
mn151819@gmail.com
Abstract— The design of high-speed and low-power VLSI architectures need efficient arithmetic processing units, which are optimized for the
performance parameters, namely, speed and power consumption. Adders are the key components in general purpose microprocessors and digital
signal processors. As a result, it is very pertinent that its performance augers well for their speed performance. Additionally, the area is an
essential factor which is to be taken into account in the design of fast adders. Towards this end, high-speed, low power and area efficient
addition and multiplication have always been a fundamental requirement of high-performance processors and systems. The major speed
limitation of adders arises from the huge carry propagation delay encountered in the conventional adder circuits, such as ripple carry adder and
carry save adder. Observing that a carry may skip any addition stages on certain addend and augend bit values, researchers developed the carry-
skip technique to speed up addition in the carry-ripple adder. Using a multilevel structure, carry-skip logic determines whether a carry entering
one block may skip the next group of blocks. Because multilevel skip logic introduces longer delays, Therefore, in this paper we examine The
basic idea of this work is to use Binary to Excess- 1 converter (BEC) instead of RCA with Cin=1 in conventional CSkA in order to reduce the
area and power. BEC uses less number of logic gates than N-bit full adder.
Key Words: Carry Skip Adder, Carry Skip Logic, Binary to Excess-1 converter
__________________________________________________*****_________________________________________________
I. INTRODUCTION
High speed and low power adder circuits have become very
important in VLSI industry. Adder circuit is one of the most
important building block in DSP processor. Adder is the a vital
component in most of the arithmetic unit. Addition is a
fundamental operation for any digital system, DSP or control
system. The fast operation of a digital system is having great
influenced by the performance of the resident adders. Adders
plays important Component in digital systems because of the
more number for use in other basic digital operations such as
subtraction, multiplication and division. Hence, the improving
performance of the digital adder increases the execution of
various binary operations in a circuit consisting of different
blocks. The appearance of the digital circuit block is gauged
by analyzing its power dissipation, layout area and its
operating speed. There are many works on the subject of
optimizing the speed and power of these units, which has been
reported. Obviously, it is extremely possible to achieve higher
speeds at low-power and energy consumptions, which is one
of the challenges for the designers of general purpose
processors. The carry skip adder is one of the fastest adders
used in many digital processors to perform arithmetic
operations. A carry-skip adder consists of a simple ripple
carry-adder with a special speed up carry chain called a skip
chain. This chain defines the distribution of ripple carry
blocks, which compose the skip adder. The carry skip adder
comes under the category of a by-pass adder and it uses a
ripple carry adder for an adder implementation. The formation
of carry skip adder block is attained by improving a worst-case
delay. The carry skip adder has a critical path, that passes
through all adders and stops at the sum bit but actually it starts
at first full adder. This adder is an efficient one according to its
area usage and power consumption. The structure of 4 bit
carry skip adder is shown in fig.1.
1.1 Basic mechanism of CSkA
The addition of two binary digits at stage i, where i not equal
to 0, of the ripple carry adder depends on the carry in, Ci ,
which in reality is the carry out, Ci-1, of the previous stage.
Therefore, in order to calculate the sum and the carry out,
2. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 637 – 641
_______________________________________________________________________________________________
638
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Ci+1 , of stage i, it is imperative that the carry in, Ci, be
known in advance.
Pi = Ai XOr Bi Equ. 1 --carry propagate of ith stage
Si = Pi XOr Ci Equ. 2 --sum of ith stage
Ci+1 = AiBi + PiCi Equ. 3 --carry out of ith stage
Supposing that Ai = Bi, then Pi in equation 1 would become
zero (equation 4). This would make Ci+1 to depend only on
the inputs Ai and Bi, without needing to know the value of Ci.
Ai = Bi then Pi = 0 Equ. 4 --from #Equation 1
If Ai = Bi = 0 then Ci+1 = AiBi = 0 --from equation 3
If Ai = Bi = 1 then Ci+1 = AiBi = 1 --from equation 3
Therefore, if Equation 4 is true then the carry out, Ci+1, will
be one if Ai = Bi = 1 or zero if Ai = Bi = 0. Hence we can
compute the carry out at any stage of the addition provided
equation 4 holds. These findings would enable us to build an
adder whose average time of computation would be
proportional to the longest chains of zeros and of different
digits of A and B.
Alternatively, given two binary strings of numbers, such as the
example below, it is very likely that we may encounter large
chains of consecutive bits (block 2) where Ai not equal to Bi.
In order to deal with this scenario we must reanalyze equation
3 carefully.
Ai not equal to Bi then Pi = 1 Equ. 5 --from Equation 1
If Ai not equal to Bi then Ci+1 = Ci --from Equation 3
In the case of comparing two bits of opposite value, the carry
out at that particular stage, will simply be equivalent to the
carry in. Hence we can simply propagate the carry to the next
stage without having to wait for the sum to be calculated.
Two Random Bit Strings:
A 10100 01011 10100 01011
B 01101 10100 01010 01100
block 3 block 2 block 1 block 0
1.2 Chain Mechanism
In order to take advantage of the last property, we can design
an adder that is divided into blocks, as shown in Fig. 2, where
a special purpose circuit can compare the two binary strings
inside each block and determine if they are equal or not. In the
latter case the carry entering the block will simply be
propagated to the next block and if this is the case all the carry
inputs to the bit positions in that block are all either 0’s or 1’s
depending on the carry in into the block. Should only one pair
of bits (Ai and Bi) inside a block be equal then the carry skip
mechanism would be unable to skip the block. In the extreme
case, although still likely, that there exist one such case, where
Ai = Bi, in each block, then no block is skipped but a carry
would be generated in each block instead. Two strings of
binary numbers to be added are divided into blocks of equal
length. In each cell within a block both bits are compared for
un-equivalence. This is done by Exclusive ORing each
individual cell (parallel operation and already present in the
full adder) producing a comparison string. Next the
comparison string is ANDed within itself in a domino fashion.
This process ensures that the comparison of each and all cells
was indeed unequal and we can therefore proceed to propagate
the carry to the next block. A MUX is responsible for selecting
a generated carry or a propagated (previous) carry with its
selection line being the output of the comparison circuit just
described. If for each cell in the block Ai ≠ Bi then we say that
a carry can skip over the block otherwise if Ai = Bi we shall
say that the carry must be generated in the block.
Fig 2: Carry Chain Skip Mechanism
II. PRIOR WORK
As this paper is on the CSKA structure, first the related work
to this adder are reviewed and then carry skip adder using
Binary to Excess-1 converter structures are discussed.
The conventional structure of the CSKA consists of stages
containing chain of full adders (FAs) (RCA block) and 2:1
multiplexer (carry skip logic). The RCA blocks are
connected to each other through 2:1 multiplexers, which can
be placed into one or more level structures. Many methods
have been suggested for finding the optimum number of the
FAs [18]–[26]. The techniques presented in [19]–[24] make
use of VSSs to minimize the delay of adders based on a single
level carry skip logic. In [25], some methods to increase the
speed of the multilevel CSKAs are proposed. The techniques,
however, cause area and power increase considerably and less
regular layout. In addition, to lower the propagation delay of
the adder, in each stage, the carry look-ahead logics were
utilized. Again, it had a complex layout as well as large power
consumption and area usage. In addition, the design approach,
which was presented only for the 32-bit adder, was not general
to be applied for structures with different bits lengths. Based
on the discussion presented above, it is concluded that by
reducing the delay of the skip logic, one may lower the
propagation delay of the CSKA significantly[28].Hence, a new
CSkA structure was presented in which the multiplexers were
replaced by AOI/OAI logic in this structure as logic gates
3. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 637 – 641
_______________________________________________________________________________________________
639
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
were used instead of MUX which results into less power
consumption and there by increasing the speed of the adder.
III. PROPOSED STRUCTURE
This structure is based on a concept of using Binary to Excess
on Converter. The basic idea of this of this work is to use BEC
instead of AOI/OAI logic in order to reduce the power
consumption and thereby increase the speed of adder as it
requires less number of gates. Excess-3 binary coded decimal
or Stibitz code, also called biased representation of Excess-N,
is a complementary BCD cod and numeral system. It is a way
to represent values with a balanced number of positive and
negative numbers using a pre-specified number N as a biasing
value. It is a non- weighted code. XS-3, numbers are
represented as decimal digits, and each digit is represented by
four bits as the digit value plus 3 (the "excess" amount):
1. The smallest binary number represents the smallest value.
(i.e. 0 − Excess Value).
2. The greatest binary number represents the largest value. (i.e.
2 N+1 − Excess Value − 1).
The primary advantage of XS-3 coding over non-biased
coding is that a decimal number can be nines' complemented
(for subtraction) as easily as a binary number can be ones'
complemented (to invert all bits)[19] As stated earlier the main
idea of this work is to use BEC instead of the RCA with in
order to reduce the area and power consumption of the regular
CSLA. To replace the n-bit RCA, an n+1 bit BEC is required.
A structure and the function table of a 4-b BEC are shown in
Fig. 3 respectively.
Fig 3: 4 bit BEC
Table -1: Truth Table of 4 bit binary to Excess One Converter
4. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 637 – 641
_______________________________________________________________________________________________
640
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Fig 4:CSkA using BEC
IV. CONCLUSIONS
A simple approach is proposed in this project to increase the
speed and reduce the power consumption of CSkA
architecture. The reduced number of gates of this project
offers the great advantage in the reduction of power
consumption and also the increase the speed. The compared
results show that the modified CSkA has a slightly larger area,
but the power consumption of the modified CSkA are
significantly reduced. The modified CSLA architecture is
therefore, low power, high speed simple and efficient for VLSI
hardware implementation.. It can be observed that for the
modified CSkA is 79% power efficient when compared to the
regular CSkA.
Design Area Power Delay
Normal 64
bit CSkA
112 0.00084 1.48 ns
CSkA with
BEC 64 bit
212 0.00017 1.48ns
REFERENCES
[1] I. Koren, Computer Arithmetic Algorithms, 2nd ed. Natick,
MA, USA: A K Peters, Ltd., 2002.
[2] R. Zlatanovici, S. Kao, and B. Nikolic, ―Energy–delay
optimization of 64-bit carry-lookahead adders with a 240 ps
90 nm CMOS design example,‖ IEEE J. Solid-State
Circuits, vol. 44, no. 2, pp. 569–583, Feb. 2009.
[3] S. K. Mathew, M. A. Anders, B. Bloechel, T. Nguyen, R.
K. Krishnamurthy, and S. Borkar, ―A 4-GHz 300-mW 64-
bit integer execution ALU with dual supply voltages in 90-
nm CMOS,‖ IEEE J. Solid-State Circuits, vol. 40, no. 1, pp.
44–51, Jan. 2005.
[4] V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, and
R. Krishnamurthy, ―Comparison of high-performance VLSI
adders in the energy-delay space,‖ IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 754–758, Jun.
2005.
[5] B. Ramkumar and H. M. Kittur, ―Low-power and area-
efficient carry select adder,‖ IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 20, no. 2, pp. 371–375, Feb. 2012.
[6] M. Vratonjic, B. R. Zeydel, and V. G. Oklobdzija, ―Low-
and ultra low-power arithmetic units: Design and
comparison,‖ in Proc. IEEE Int. Conf. Comput. Design,
VLSI Comput. Process. (ICCD), Oct. 2005, pp. 249–252.
[7] C. Nagendra, M. J. Irwin, and R. M. Owens, ―Area-time-
power tradeoffs in parallel adders,‖ IEEE Trans. Circuits
Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp.
689–702, Oct. 1996.
[8] Y. He and C.-H. Chang, ―A power-delay efficient hybrid
carrylookahead/ carry-select based redundant binary to
two’s complement converter,‖ IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 55, no. 1, pp. 336–346, Feb. 2008.
[9] C.-H. Chang, J. Gu, and M. Zhang, ―A review of 0.18 μm
full adder performances for tree structured arithmetic
circuits,‖ IEEE Trans. Very Large Scale Integr. (VLSI)
Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
[10] D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, and J.
M. Rabaey, ―Ultralow-power design in near-threshold
region,‖ Proc. IEEE, vol. 98, no. 2, pp. 237–252, Feb.
2010.
[11] R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester,
and T. Mudge, ―Near-threshold computing: Reclaiming
Moore’s law through energy efficient integrated circuits,‖
Proc. IEEE, vol. 98, no. 2,pp. 253–266, Feb. 2010.
[12] S. Jain et al., ―A 280 mV-to-1.2 V wide-operating-range
IA-32 processor in 32 nm CMOS,‖ in IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2012, pp.
66–68.
[13] R. Zimmermann, ―Binary adder architectures for cell-based
VLSI and their synthesis,‖ Ph.D. dissertation, Dept. Inf.
Technol. Elect. Eng., Swiss Federal Inst. Technol. (ETH),
Zürich, Switzerland, 1998.
[14] D. Harris, ―A taxonomy of parallel prefix networks,‖ in
Proc. IEEE Conf. Rec. 37th Asilomar Conf. Signals, Syst.,
Comput., vol. 2. Nov. 2003, pp. 2213–2217.
[15] P. M. Kogge and H. S. Stone, ―A parallel algorithm for the
efficient solution of a general class of recurrence
equations,‖ IEEE Trans. Comput., vol. C-22, no. 8, pp.
786–793, Aug. 1973.
[16] V. G. Oklobdzija, B. R. Zeydel, H. Dao, S. Mathew, and R.
Krishnamurthy, ―Energy-delay estimation technique for
high performance microprocessor VLSI adders,‖ in Proc.
16th IEEE Symp. Comput. Arithmetic, Jun. 2003, pp. 272–
279.
[17] M. Lehman and N. Burla, ―Skip techniques for high-speed
carrypropagation in binary arithmetic units,‖ IRE Trans.
Electron. Comput., vol. EC-10, no. 4, pp. 691–698, Dec.
1961.