79.4dB/100MHz/23mW SNDR/BW/Power 7th order opampless multibit sigma delta modulator Takashi Miki Abstract: A novel opampless multibit continuous-time (CT) sigma delta modulator is designed. Newly designed resonators without opamps are used for the modulator in order to suppress power consumption. Averaging multibit quantization technique is used for the internal quantizer of the modulator in order to compensate for the loss of the loop gain because of eliminating opamps from the loop filter. Averaging multibit quantization technique also enables to obtain a high signal-to-noise-distortion-ratio (SNDR) without dynamic element matching (ELD) in feedback DACs. The modulator is studied in transistor level simulations with 45nm process model files, and the result shows that it can achieve 79.4dB SNDR, 100MHz band width (BW), and 23mW power consumption.

1. 1
79.4dB/100MHz/23mW SNDR/BW/Power 7th order opampless multibit sigma delta
modulator
Takashi Miki
Abstract
A novel opampless multibit continuous-time (CT) sigma delta modulator is designed. Newly designed resonators
without opamps are used for the modulator in order to suppress power consumption. Averaging multibit quantization technique
is used for the internal quantizer of the modulator in order to compensate for the loss of the loop gain because of eliminating
opamps from the loop filter. Averaging multibit quantization technique also enables to obtain a high signal-to-noise-distortion-
ratio (SNDR) without dynamic element matching (ELD) in feedback DACs. The modulator is studied in transistor level simulations
with 45nm process model files, and the result shows that it can achieve 79.4dB SNDR, 100MHz band width (BW), and 23mW
power consumption.
Background
Sigma delta modulators have an advantage in achieving high SNDR particularly when they are designed for low
frequencies applications. When it comes to high frequency applications, sigma delta modulators are not necessarily the best
architecture as an analog-to-digital convertor (ADC) because it consumes considerable power as they work at high frequencies.
Large part of the power consumption of a high-speed sigma delta modulator is occupied by opamps in the loop filter of the
modulator. This is the reason why an opampless loop filter is preferable for a high-speed sigma delta modulator, and there have
been some researches concerned with opampless sigma delta architectures. Passive filters are used in some studies [1] to fully
or partially eliminate opamps form loop filter, but the performance of the modulator needs to be sacrificed because passive
filters cannot perfectly replace the function of opamps. VCO based integrators are another possible candidate for the
replacement for opamps [2], but still they do not work exactly in the same way as opamps do. As those preexisting studies show,
opampless sigma delta modulator is a subject which has not been well developed yet. In this study, a method for designing an
opampless sigma delta modulator which has the equivalent loop filter designed using opamps is presented.
Design overview
The entire diagram of the proposed sigma delta modulator in single-end description is shown in Fig.1. The modulator
has an input stage made of first order low-pass filter, three resonators, 64 single-bit comparators, a global DAC for feedbacking
signals to the input stage, and a fast-path DAC for feedbacking signals to the arrays of the comparators. The comparators are
divided into four units, each of which is indicated as “x16 CMP” in Fig.1 and composed of 16 single-bit comparators as shown in
Fig.2. In the unit of sixteen comparators, the output signal form one single-bit comparetor is fed back to the input of another
single-bit quantizer after being multiplied by a factor of a certain coefficient (k1, k2, … kN). The comparators form an averaging
multibit quantizer [3]. Averaging multibit quantization is a sort of stochastic quantization [4], and the basic concepts of stochastic
quantization is shown in Fig.3. The main idea is that dethering signals (DS1, DS2, … DSN) added at the inputs of the single-bit
quantizers help to make the quantiation noises uncorrelated and that the power of the quantization noise is reduced by the
factor of 1 𝑁⁄ , where 𝑁 is the number of single-bit quantizers, when the quatnized signals are averaged. In the proposed
modulator, the dethring signals are not added externally, but they are produed internerly and added to the input of the
comparators. Specifically, signals that are fead back along the local feedback paths in Fig.2 work as ditheing signals.

2. 2
Opampless resonator
The transistor level design of the proposed resonator is shown in Fig.4. The resonator has four copies of the same
differential pairs and common-mode feedback circuits. Positive feedback in the resonator make it possible to satisfy a condition
for resonance. The small-signal equivalent of the proposed resonator is shown in Fig.5, and its transfer functions are written as
follows.
𝑉𝑂𝑃 − 𝑉𝑂𝑁
𝑉𝐼𝑃 − 𝑉𝐼𝑁
=
𝑔 (𝑔 − 𝑔 + 𝑠𝐶 )
𝐶 𝐶 𝑠 + (𝛽𝑔 𝐶 − 𝑔 𝐶 ) + 𝛽𝑔 (𝑔 − 𝑔 )
𝑉𝑀𝑃 − 𝑉𝑀𝑁
𝑉𝐼𝑃 − 𝑉𝐼𝑁
=
−𝑠𝑔 𝐶
𝐶 𝐶 𝑠 + (𝛽𝑔 𝐶 − 𝑔 𝐶 ) + 𝛽𝑔 (𝑔 − 𝑔 )
The resonance condition is
𝑔
𝑔
= 𝛽
𝐶
𝐶
, where β is a feedback factor. The resonator produces a gain larger than 0 dB when β is less than one.
Comparators
The transistor level design of one of the clocked comparators is shown in Fig.6. The clocked comparator has seven
positive inputs and the same number of negative inputs. The input signals come from the resonators, fast-path DAC, and local
feedback path. VMP1, VOP1, VMN1, and VON1 are provided by the first resonators. VMP2, VOP2, VMN2, and VON2 are provided
by the second resonators. VMP3, VOP3, VMN3, and VON3 are provided by the third resonators. VLFP and VLFN are provided by
the local feedback path. VFFP and VFFN are provided by the fast feedback path. Summation of the input signals is carried out at
the clocked comparators, and the sign of the summed signal is determined at the comparators too [5]. Time interleaving is used
for controlling clocked comparators. Two clocked comparators are paired as in Fig.7, and they are clocked alternately. Two
clocked comparators are needed for one quantized signal, and thus 128 clocked comparators are used for the proposed
modulator even though the number of the quantized signals is still 64.
DAC
The diagram of the global DAC is shown in Fig.8. The global DAC consists of 64 current steering DACs with their outputs
shorted. The positive output IAP and negative output IAN are connected to the input stage shown in Fig.9. The digital output
signals from the quantizers are converted to currents by the global DAC, and the current flows the input resistor Rin of the input
stage. The global DAC combined with the input stage carries out averaging the digitized output signals and feedback operation
at a time. The fast-path DAC in Fig.10 has the same topology as the global DAC and the positive and negative outputs VFFP and
VFFN are connected through the output resistors which convert output currents into voltages. The output voltages are fed back
to the comparators. The local DACs consists of one current steering DAC as shown in Fig.11. A local DAC converts a digital output
form the nth single-bit comparator into a voltage signal, and the voltage signal is fed back to the n+1st single-bit comparator. The
supply voltage for the global, fast-path, and local DACs is 1.4V while that for other parts of the modulator is 1.2V.
Simulation results
The proposed sigma delta modulator is designed with PTM model files of 45 nm process [6]. The specification of the
proposed modulator is shown in Table.1. The plot of SNR and SNDR is shown in Fig.12. The spectral plot for a sinusoidal signal
of -3dB magnitude is shown in Fig.13. The breakdown of the power consumption is shown in Fig.14. Mismatch for the global
DAC is taken into consideration at the simulation by making the currents of the current sources in the DAC mismatched according
to a Gaussian distribution of 0.2% sigma. The harmonics at the spectral plot is mainly caused by the mismatch in the global DAC,
but a SNDR of 79.4dB is obtained without dynamic-element matching (DEM). It should be noted that mismatch for the clocked

3. 3
comparators is not considered at the simulation because no mismatch model is not available for the PTM model files. The
performance of the proposed modulator is compared with the performances of other recent ADCs in Table.2. Those works picked
out for comparison are ones which provide a FOMS larger than 165dB and BW larger than 40MHz. The simulation results, when
compared with other works, show that the proposed modulator has a potential to achieve high performances as good as the
state of art modulators.
Fig.1 Diagram of the proposed sigma delta modulator
Fig.2 Diagram of x16 comparator
1+207 s
2
1+2.06 s
1+207 s2
-2.06 s
1+45.1 s
2
1+2.24 s
1+45.1 s2
-2.24 s
1+25.3 s
2
1+2.90 s
1+25.3 s2
-2.90 s
25 5 2
1+40 s
1
0.8
-0.1
-0.4
0.4
-1
1
-1
+
+
Vin
-1 0.013
16
16
16
16
64
Vout
INPUT
STAGE
Global
DAC
Fast-
path
DAC
x16 CMP
x16 CMP
x16 CMP
x16 CMP
AVE-
RAGING
1st
RESONATOR
2nd
RESONATOR
3rd
RESONATOR
COMPARATORS
-1
VST
VM1
VO1
VO2
VM2
VM3
VO3
VFF
U Y
+
+
U
Y
+
DAC-1
DAC-1
DAC-1
+
+
DAC-1
DAC-1
km-1
Z
-1
Z
-1
Z
-1
Z
-1
Z
-1
k1
km
km+1
k16
16

4. 4
Fig.3 Conceptual diagram of an averaging multibit sigma delta modulator
Fig.4 Proposed opampless resonator
Fig.5 Macro model of the proposed resonator
+
Vin
Vout
+
+
+
LF
kN
DACZ
-1
DACZ
-1
DACZ
-1
DACZ
-1
DS
+
kNDS
+
kNDS
+
kNDS
1/N
1/N
+
N
3
2
1
-1-1
Loop filter
Single-bit
quantizer
Dethering
signal
CMFB
CMFB
VIN
VIP
VOP
VON
VMP
VMN
VBNC
VBN
VBPC
VDD
VSS
To comparators
From previous stage
β β
VIP
VOP
VMP VMN
VIN
VON
+
-
gm3
+
-gm2
C2 C2
+
-
gm3
+
-
gm1
+
-
gm1
+
-
gm2C1 C1

5. 5
Fig.6 Clocked comparator
Fig.7 Diagram of time-interleaving
Fig.8 Diagram of global DAC
DSP
DSN
VMP1 VOP1 VMP2 VMP3 VFFPVLFP VP0 VOP2 VOP3 VFFN VON3 VMN3 VON2 VMN2 VON1 VMN1 VN0 VLFN
CLK
VSS
VSS VSS
VDD
VDD
VSS
To SR latches
Clocked
Comparator
SR
Latch
Q
Q
SR
Latch
Q
Q
Mux
Mux
CLK
CLK
1
0
CLK
1
0
CLK
DOP
DON
VLFP
VP0
VMP1
VOP1
VMP2
VOP2
VMP3
VOP3
VGFP
VLFN
VN0
VMN1
VON1
VMN2
VON2
VMN3
VON3
VGFN
Clocked
Comparator
DSP1
DSN1
DSP2
DSN2
To DACs
IAP
IAN
DOP1 DOP2 DOP64
DON1 DON2 DON64
To input stage
From Comparators

6. 6
Fig.9 Input stage
Fig.10 Diagram of the fast-path DAC
Fig.11 Diagram of a local DAC
VIN_P
VIN_N
IAP IAN
Rin
Rin
Cin
Cin
VP0
VN0
Input To comparators
From global DAC
VFFP
VFFN
DOP1 DOP2 DOP64
DON1 DON2 DON64
From comparators
To comparators
VLFP
VLFN
DOPn
DONn
From nth comparator
To n+1 th comparator

7. 7
Fig.12 Plots of SNR and SNDR
Fig.13 Spectral plot for a sinusoidal input
Fig.14 Power consumption breakdown
0
10
20
30
40
50
60
70
80
90
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
SNDR,SNR(dB)
Input (dB)
SNDR
SNR
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1.0E+06 1.0E+07 1.0E+08 1.0E+09
Magnitude(dB)
Freq (Hz)
Input: -3dB
Resonators,
1.7mW
DACs, 6.3mW
Comparators,
15.0mW

8. 8
Tech 45nm
Fs 3.2GHz
Supply 1.2V/1.4V
Fin 28.9MHz
BW 100MHz
SNDR 79.4dB
SNR 82.8dB
DR 84dB
PW 23mW
Table.1 Specification of the proposed modulator
Architecture Tech [nm] SNDR [dB] P [mW] BW [MHz] FOMS [dB]
VLSI '17 Lim [7] Pipe, SAR 40 73.2 2.30 50 176.6
ISSCC '16 Liu [8] Single-slope, SAR 28 64.4 0.35 50 176.0
VLSI '15 Mathew [9] SAR, VCO 45 68.0 3.40 100 172.7
VLSI '14 Verbruggen [10] Pipe, SAR, TI 28 65.0 2.30 100 171.4
ISSCC '14 Goes [11] Pipe, SAR, TI 28 66.0 1.50 40 170.3
VLSI '17 Martens [12] Pipe, SAR, TI 16 64.0 3.60 151.5 170.2
ISSCC '18 He [13] SDCT 28 79.8 64.30 50 168.7
VLSI '16 Nam [14] SAR, TI 65 65.0 37.70 800 168.3
ISSCC '16 Wu [15] SDCT 65 75.3 24.70 45 167.9
ISSCC '17 Huang [16] Pipe, SAR 65 63.5 6.23 165 167.7
VLSI '14 Zhou [17] Pipe, SAR 40 65.3 4.96 80 167.4
ISSCC '17 Yoshioka [18] Pipe, SAR 28 61.1 1.90 80 167.3
VLSI '17 Luu [19] SAR 14 60.5 3.30 150 167.0
VLSI '15 Loeda [20] SDCT 40 66.9 5.25 40 165.7
ISSCC '17 Huang [21] SDCT, VCO 16 71.9 54.00 125 165.5
VLSI '16 Lien [22] Pipe, SAR, TI 28 60.8 14.60 400 165.2
VLSI '14 Inerfield [23] SAR 28 67.1 8.00 50 165.1
This work SDCT 45 79.4 23.00 100 175.8
FOMS=SNDR+10*log10(BW/P)
Table.2 Performance comparison

9. 9
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