This document discusses a technique to mitigate oscillator pulling in an EDGE transmitter integrated circuit. Injection pulling occurs when the power amplifier modulates the oscillator frequency due to parasitic coupling. The proposed solution uses a digitally controlled delay to optimize the phase relationship between the aggressor and victim signals, minimizing the injection pulling effect. Measurement results show that the optimum delay is constant within a GSM frequency band. The technique was implemented in a 65nm CMOS EDGE transmitter chip to compensate for self-interference and improve transmitter performance across process and temperature variations.
On Chip Calibration And Compensation Techniques (11 03 08)imranbashir
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The advent of CMOS technology in RF integrated circuits has lead to integration. A practical manifestation of such SoC is DRP, a solution engineered at Texas Instruments Inc. in which digital baseband has been integrated with a RF transceiver all in CMOS technology. A logical step forward in use of such technology is to harness the power of the digital architecture and the baseband in implementing innovative solutions to enhance radio performance over corner conditions and mitigate interferences arising as a result of integration. This research focuses on five practical examples of software solutions for common challenges in DRP.
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Averaging noise frequency is a quick way that requires to be "added-in" or "multiplied by a factor". As for Industrial Standards/Regulations, it is based on Sound Intensity Level IL. This .pdf provides the values (to be interpolated for in between figures) as well as the formula used in the industry.
This presentation covers noise performance of Continuous wave modulation systems; It explains modelling of white noise , noise figure of DSB-SC, SSB, AM, FM system
Noise reduction in ECG Signals for Bio-telemetrybIJECEIAES
In Biotelemetry, Biomedical signal such as ECG is extremely important in the diagnosis of patients in remote location and is recorded commonly with noise. Considered attention is required for analysis of ECG signal to find the patho-physiology and status of patient. In this paper, LMS and RLS algorithm are implemented on adaptive FIR filter for reducing power line interference (50Hz) and (AWGN) noise on ECG signals .The ECG signals are randomly chosen from MIT_BIH data base and de-noising using algorithms. The peaks and heart rate of the ECG signal are estimated. The measurements are taken in terms of Signal Power, Noise Power and Mean Square Error.
This presentation covers types of noise in communication system, noise modelling, thermal noise, shot noise, experimental determination of noise figure, noise figure, friss formula with numerical.
Noise Error Calculation : Averaging and Industrial Standards (Formula)Gan Chun Chet
Averaging noise frequency is a quick way that requires to be "added-in" or "multiplied by a factor". As for Industrial Standards/Regulations, it is based on Sound Intensity Level IL. This .pdf provides the values (to be interpolated for in between figures) as well as the formula used in the industry.
This presentation covers noise performance of Continuous wave modulation systems; It explains modelling of white noise , noise figure of DSB-SC, SSB, AM, FM system
Mitigation of Noise in OFDM Based Plc System Using Filter Kernel DesignIJERA Editor
Power line communication is a technology that transforms power line in to pathway for conveyance of
broadband data. It is cost less than other communication approach and for better bandwidth efficiency OFDM
based PLC system is used. In real PLC environment some electrical appliances will produce noise. To mitigate
this noise filter kernel design is used, so periodic impulsive noise and Gaussian noises are removed from PLC
communication system by using this filter kernel design. MATLAB is used for the simulation and the result
shows that filter kernel is simple and effective noise mitigation technique. Further in future, interference due to
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DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERSIJMEJournal1
In this paper, we are present design and analysis of PLL, which is simulated in CMOS 0.18μm technology.The digital phase locked loop achieves locking within about 100 reference clock cycles. The pure digital
phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog
counterpart.In this PLL circuit successfully achieved 1.55GHz frequency. Jitter is 1.09ns achieved is very
less. Also achieve low phase noise -98.5827 at 1MHz Frequency
Low Peak to Average Power Ratio and High Spectral Efficiency Using Selective ...theijes
A low complexity peak to average power ratio (PAPR) reduction scheme for orthogonal frequency division multiplexing (OFDM) systems is proposed. All pass filters technique used PAPR is reduction but small amount of reduction, So use Selective Mapping (SLM) technique reduce PAPR and SNR increases.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
Double feedback technique for reduction of Noise LNA with gain enhancementijceronline
In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW-1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFBLNA included in a receiver frontend for biomedical applications (ISM and WMTS).
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
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7. Impairment Modeling 1. FREF 2. TDC 3. DCO + Composite ADPLL spectrum S AM (dBc/Hz) f L TDC (dBc/Hz) f 4. Coupled AM Signal 3 L FREF (dBc/Hz) f 3 L DCO (dBc/Hz) f 2
In this presentation we will talk about Motivation behind this work, injection pulling mechanism, impairment modeling, characteristics of impairment, our proposed solution verified by measurement and finally conclusions.
The environment we are working under presents many unique challenges when building a performance complaint 2.5G radio. The key constraints driving the system design is #1. The design is highly integrated. All critical analog blocks are in close proximity to each other especially the RF oscillator and the power amplifier. The radio shares the substrate with the digital baseband. #2. The product cost is kept low by using plain vanilla CMOS process which implies we cannot use special layer like burried n-well to improve isolation between the critical analog blocks. There-fore the result is that we end up with self interference among these blocks that limits the radio performance.
1. Now lets look at the injection pulling mechanism. The figure to the left shows the polar transmitter. The IQ signal is processed by the cordic block which outputs the frequency control word and the amplitude control word. The FCW is input to the DFC which performs the FM modulation and the ACW is input to the DRAC which performs the AM modulation. The best way to analyze the extent of injection pulling during EDGE modulation is to monitor the ADPLL output while the EDGE-FM component is turned off and the EDGE-AM component is turned on. 2. The figure to the right shows various signals. Trace ‘c’ is the ADPLL output without any AM applied. Trace ‘b’ is the ADPLL output with AM applied such that the average output power is -10dBm. Trace ‘a’ is the ADPLL output with AM applied such that the average output power is 0dBm. In order to illustrate the concept of AM-FM, we have added another trace which is the AM spectrum of EDGE modulation. Notice the similarities between the EDGE-AM spectrum and the noise on the ADPLL spectrum. The 280-kHz spur which roughly the EDGE-AM modulation rate is present on both spectra. Also notice that the attenuation on ADPLL spectrum at close-in and far-out offsets. The ADPLL spectrum looks like a band-pass filtered version of the AM spectrum. In this way, you have the AM converted into FM.
Looking at the figure to the right, in the absence of interferer, the oscillator and the error vector VT are in phase and consequently there is no additional phase in the tank and therefore no pulling. But when the oscillator output is amplified by the power amplifier that generates an appreciable 2 nd harmonic which finds its way back to the oscillator core through transfer function H(s), then an additional phase phi is observed in the system as shown in figure (a). The time varying AM on the interferer Vinj in figure (b) results in time varying phi in figure c. Now due to this additional phase means that Barkhausen criteria can no longer be satisfied at wo and in order to satisfy this criteria, the frequency has to move to another point along this curve shown in figure (d). Since phi is time varying, the result is a time varying frequency defined by this equation. At this point, it is important to discuss the difference between the conventional case stated in Adler’s Paper and the special case we have here. In the case described in Adler’s paper, the interferer is not AM modulated. The interference in the special case is time varying. Wo which is defined as the resonant frequency of the LC tank in the absence of pulling is constant in Adler’s case while it is varying because of FM in the special case. The third difference is that the interferer in Adler’s case is an independent source while the interferer in the special case shares the same FM as the victim oscillator. The similarity between the two cases which is the important point here is the fact that the angle between the victim (Vinj) and aggressor (Vosc) alpha is constant in steady state and that the oscillator vector Vosc, the error vector Vt and Vinj are all moving at the same rate defined by this equation.
One other key difference is the fact that the oscillator is under the influence of a phase lock loop therefore we need to analyze the injection pulling on an oscillator in a close loop PLL operation. To do that we come up with a linear model for the ADPLL as shown in the figure. There are four noise sources in the system. We have the reference, the TDC, the DCO and added in the same path is phi,pulling which is the parasitic phase due to injection pulling given by this equation. Now in a close loop operation, the composite phase due to injection pulling will be simply the multiplication of phi,pulling with Hcl,p which is the injection pulling transfer function.
Now we combine all the noise sources, to determine the composite ADPLL spectrum. The FREF noise is multiplied with Hcl,R which is low pass, TDC quantization noise is multiplied with Hcl,TDC which is low pass, DCO noise is multiplied by Hcl,V which is high pass. The injection pulling noise is obtained by multiplying the coupled AM spectrum with Hcl,p which has two components. One is the same as Hcl,V which is high pass and the 1/s component is from the equation in the previous slide which is low pass. Therefore the overall transfer function is bandpass.
Now we look at the comparison between the model and measurements. The left figure shows phase noise plot with contributions from the reference, TDC, DCO and injection pulling (magenta curve). The composite response is dominated by the noise due to injection pulling at close in offsets. The DCO dominates at far out offsets. The figure on the right shows the simulated (red) and measured (black) ADPLL spectrum. There is discrepency between measurement and simulation at far-out offsets is due to the imperfections in the injection pulling transfer function modeling.
Next we look at some important characteristics of injection pulling impairment. Of particular importance is the effect of ADPLL loop bandwidth on injection pulling. It is common understanding that increasing the loop bandwidth will reduce the extent of injection pulling. We will try to understand this mathematically and graphically. In order to do that the most prudent thing to do is to measure the injection pulling transfer function. The figure to the left shows the setup used to do that. The FM modulation is disabled while the power amplifier is modulated with a sine-wave with frequency varying from 100 Hz to 10 MHz. So the AM spectrum is going to look like this and due to the AM-FM conversion, the PLL spectrum is going to look like this. As the AM modulation rate is increased, the spur moves away from the carrier and its amplitude varies. Now we plot the level of this spur as a function of frequency offset for three different loop bandwidth which gives us the figure to the right. To determine the composite phase noise due to injection pulling we multiply this transfer function with the coupled AM spectrum. Notice the narrow loop bandwidth has excess noise at close in offsets and therefore will perform worst in terms modulation accuracy. The center frequency of the band-pass filter increases as the loop bandwidth is increases. For wide-loop bandwidth, the Hcl,p filter provides high attenuation at close in offsets. One important thing to remember Hcl,P is half the picture. The other half is the AM spectrum it self. One must not rush to judgement when comparing different cellular standards and how what the extent of injection pulling will be. If I have a low frequency AM, then according to this figure, I will see more injection pulling than I would high frequency signal which at lets say 1-MHz AM. Therefore when-ever comparing the impact of injection pulling between different standards, always break the signal down into AM and FM, look at the AM spectrum with Hcl,P before passing a judgement.
Another important trend which is obvious from the equation is that as the oscillator peak voltage is increases, the extent of injection pulling decreases as shown by the curve on this figure. However, there is a limit to how much improvement you can get because of DCO reliability concerns.
The most important trend that is exploited in the solution to this impairment, which will be discussed in a later slide, is the effect of phase alpha between the aggressor and victim. As alpha approaches zero, the parasitic phase due to injection pulling, also goes to zero as shown in the curve on this figure.
In this slide we present the solution based on the trend discussed in the last slide. The solution as shown in the left figure consists of a digitally controlled delay that is designed to adjust the phase between the aggressor and the victim to an optimum point. This will require a calibration step that is executed by software running on digital baseband which samples the ADPLL digital phase error signal PHE. Any useful statistic such as variance on the PHE signal can be used to estimate the extent of noise due to injection pulling present in the system as shown in the figure to the right. If the given delay of the buffers is 30ps, then 5 stages can give a phase shift of 180 deg at 3.4GHz which would be sufficient in order to adjust alpha close to zero. The buffers must be sized properly to avoid thermal noise floor degradation. The 1/f noise is not a big issue since the transistors are switching rail to rail and the 1/f corner is very low.
This slide shows the measurement results on silicon fabricated in 65nm. The x-axis is delay setting and y-axis is EVM. The solid trace is DCS1800 band frequency of 1740MHz and dot trace is PCS1900 band frequency of 1850. There is a slight shift in optimum point with frequency and temperature. The frequency variation can be compensated by calibrating per GSM band however for optimum performance temperature compensation is also required which can be done with equation based empirical model.
An additional approach that is not discussed in the paper, is to add an additional stimulus in the ADPLL to cancel the parasitic phase due to injection pulling. The ADPLL utilizes two point modulation scheme in which data is directly applied to the DCO. The feedback signal from the DCO contains this modulation which is cancels by applying an opposite stimulus at the frequency detector. In ideal case, the output of the detector will be zero and hence no error is seen by the ADPLL and hence no additional stimulus is generated. But DCO experiences injection pulling, the modulation part in the feedback signal is canceled but the parasitic modulation due to injection pulling is not. But if we input the data into a LUT and apply an opposite stimulus of Phi,pulling, we can negate the effect of injection pulling real time. The challenge obviously is to calibrate the magnitude of compensating stimulus against the interference which would depend on the parasitic coupling between the amplifier and the DCO.