On-Chip Calibration and Compensation Techniques for  Wireless SoCs Imran Bashir Nov 5 th , 2008
Presentation Outline <ul><li>Motivation: The need for Calibration & Compensation </li></ul><ul><li>Definition of Calibrati...
Motivation 1. Variation Due to Corner Conditions 40% Variation over Process & 15% Variation over Temperature
Motivation 1. Variation Due to Corner Conditions Without calibration and compensation, the phase error of the transmitter ...
Motivation 2. Mitigation of an Impairment <ul><li>Strategies of addressing impairments in SoC: </li></ul><ul><ul><li>Reduc...
Motivation 3. Integration  -> Miniaturization <ul><li>Digital Baseband is shrinking  -> Challenge for RF Transceiver desig...
Motivation 4. Built-In Self Test 1 <ul><li>Some calibration and compensation schemes can also serve as a means for screeni...
Characteristics of Calibration & Compensation Processes <ul><li>Calibration: </li></ul><ul><ul><li>Sometimes performed in ...
DRP Fundamentals: TX Conventional vs. DRP  <ul><li>Analog PLL: Charge pumps, loop filter </li></ul><ul><li>Analog control ...
DRP Fundamentals: DCO <ul><li>Cross coupled NMOS pair </li></ul><ul><li>Three banks of capacitors: PB(MIM), AB(MOS), TB(MO...
DRP Fundamentals: DPA <ul><li>NMOS transistors drain tied to a common node </li></ul><ul><li>Digital control on amplitude ...
DRP Fundamentals: DPA <ul><li>DPA transfer function is non-linear at high ACW  -> Requires amplitude and phase predistorti...
DRP Fundamentals: PHE <ul><li>The phase error signal PHE is the output of the loop’s phase detector </li></ul><ul><li>Comp...
Mitigation of RF Oscillator Pulling Using Phase Adjustment <ul><li>Issue: </li></ul><ul><ul><li>PPA AM creates parasitic m...
Mitigation of RF Oscillator Pulling  Problem Statement <ul><li>The DCO is suffering from parasitic modulation caused by AM...
Mitigation of RF Oscillator Pulling  Measurement of Pulling <ul><li>The PPA is modulated with EDGE or sinusoid while the F...
Mitigation of RF Oscillator Pulling  Root Cause: Injection Pulling 1  of DCO <ul><li>The aggressor  I agg  signal finds it...
Mitigation of RF Oscillator Pulling  Root Cause: Injection Pulling of DCO <ul><li>Ideal MOSCAP </li></ul><ul><li>2 nd  LC ...
Mitigation of RF Oscillator Pulling  Root Cause: Injection Pulling of DCO Worst case pulling with -60dB aggressor ~10kHz a...
Mitigation of RF Oscillator Pulling  Root Cause: MOSCAP C-V Asymmetry <ul><li>The aggressor  I agg  signal finds its way i...
Mitigation of RF Oscillator Pulling  Root Cause: MOSCAP C-V Asymmetry <ul><li>A step increase in DCO amplitude will change...
Mitigation of RF Oscillator Pulling  Root Cause: MOSCAP C-V Asymmetry Estimate of pulling with -60dB aggressor MOSCAP mode...
Mitigation of RF Oscillator Pulling Effect of Oscillator Current Increasing victim amplitude  will reduce  γ  and pulling....
Mitigation of RF Oscillator Pulling Effect of Loop bandwidth Increase loop bandwidth improves EVM but degrades spectrum.
Mitigation of RF Oscillator Pulling Effect of Delay b/w DCO & DPA <ul><li>In this experiment, the delay is changed by adju...
Mitigation of RF Oscillator Pulling Effect of Delay between DCO and DPA <ul><li>The DCO is injection locked to the signal ...
Mitigation of RF Oscillator Pulling  Conventional Solutions <ul><li>Reduce Coupling Path </li></ul><ul><ul><li>Improve lay...
Mitigation of RF Oscillator Pulling Proposed Solution <ul><li>The proposed solution is to establish an optimum phase relat...
Mitigation of RF Oscillator Pulling Calibration Results <ul><li>PHE estimation is performed on various delay settings (VDD...
Mitigation of RF Oscillator Pulling Issues with proposal <ul><li>Thermal noise degradation in signal path </li></ul><ul><l...
Calibration of DCO Current Problem Statement <ul><li>The oscillator noise performance varies over process and temperature....
Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability....
Calibration of DCO Current Effect on Radio Performance R. Santucci, Waleed Khalil, and Dmitry Petrov, “Accurate Tuning and...
Calibration of DCO Current Effect on Radio Performance Excessive DCO phase noise effects RMS Phase Error and spectrum perf...
Calibration of DCO Current Proposed Solution <ul><li>Digital processing of ADPLL’s phase error signal  </li></ul><ul><li>N...
Calibration of DCO Current Validation of Proposed Solution Optimum DCO current   using PHE based estimation PHE based esti...
Calibration of DCO Current Issues with Proposed Solution <ul><li>Requires averaging over large number of samples ->  Calib...
Mitigation of  ΣΔ  Noise on DCO Problem Statement <ul><li>Spectral growth at offsets between 300kHz – 5MHz from the carrie...
Mitigation of  ΣΔ  Noise on DCO Problem Statement <ul><li>Periodic behavior of RMS phase error and 400kHz modulated spectr...
Mitigation of  ΣΔ  Noise on DCO Effect of DCO Frequency & Temp For a calibrated delay, a change in DCO frequency or temper...
Mitigation of  ΣΔ  Noise on DCO Calibration Process <ul><li>Find the worst phase/delay setting out of all possible flyback...
Mitigation of  ΣΔ  Noise on DCO Compensation Process <ul><li>Read target frequency and inverter delay to compensate for ef...
Mitigation of  ΣΔ  Noise on DCO Lab Results <ul><li>Baseline vs. calibrated & compensated flyback delay performance </li><...
Mitigation of  ΣΔ  Noise on DCO Issues <ul><li>Too complex (to engineers) </li></ul><ul><li>Challenges in calibration on A...
Predistortion Calibration of DPA Problem Statement <ul><li>Built-In Self-Calibration of AM-AM and AM-PM distortion of DPA ...
Predistortion Calibration of DPA Conventional Approach <ul><li>Conventional approach: use expensive external RF test equip...
Predistortion Calibration of DPA Proposed Solution <ul><li>The proposed solution couples the DPA output into the reference...
Predistortion Calibration of DPA Lab Validation Higher DPA Power  ->  More AM on FREF signal ->   Higher the extent of PHE.
Predistortion Calibration of DPA Lab Validation
Predistortion Calibration of DPA Issues <ul><li>PHE is not sensitive enough at low DPA codes. Therefore, AM-AM and AM-PM d...
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On Chip Calibration And Compensation Techniques (11 03 08)

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The advent of CMOS technology in RF integrated circuits has lead to integration. A practical manifestation of such SoC is DRP, a solution engineered at Texas Instruments Inc. in which digital baseband has been integrated with a RF transceiver all in CMOS technology. A logical step forward in use of such technology is to harness the power of the digital architecture and the baseband in implementing innovative solutions to enhance radio performance over corner conditions and mitigate interferences arising as a result of integration. This research focuses on five practical examples of software solutions for common challenges in DRP.

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  • On Chip Calibration And Compensation Techniques (11 03 08)

    1. 1. On-Chip Calibration and Compensation Techniques for Wireless SoCs Imran Bashir Nov 5 th , 2008
    2. 2. Presentation Outline <ul><li>Motivation: The need for Calibration & Compensation </li></ul><ul><li>Definition of Calibration & Compensation </li></ul><ul><li>DRP Fundamentals </li></ul><ul><li>Examples: </li></ul><ul><ul><li>Mitigation of RF Oscillator Pulling Using Phase Adjustment </li></ul></ul><ul><ul><li>Calibration of Oscillator Current </li></ul></ul><ul><ul><li>Adaptive Mitigation of Noise Induced to a Digitally-Controlled Oscillator by ΣΔ </li></ul></ul><ul><ul><li>Predistortion Calibration of an RF Power Amplifier </li></ul></ul><ul><li>Summary/ Conclusions </li></ul><ul><li>Appendix </li></ul>
    3. 3. Motivation 1. Variation Due to Corner Conditions 40% Variation over Process & 15% Variation over Temperature
    4. 4. Motivation 1. Variation Due to Corner Conditions Without calibration and compensation, the phase error of the transmitter will fail 3GPP GSM specification. GSM 3GPP limit (5 degrees) Measured Simulated Target specification (3 degrees)
    5. 5. Motivation 2. Mitigation of an Impairment <ul><li>Strategies of addressing impairments in SoC: </li></ul><ul><ul><li>Reduce the magnitude of aggressor </li></ul></ul><ul><ul><li>Eliminate ‘means’ i.e. coupling path </li></ul></ul><ul><ul><li>Increase the robustness of victim </li></ul></ul><ul><ul><li>Manipulate the aggressor to reduce the impact on the victim. Examples: </li></ul></ul><ul><ul><ul><li>Mitigation of RF Oscillator Pulling Using Phase Adjustment </li></ul></ul></ul><ul><ul><ul><li>Adaptive Mitigation of Noise Induced to a Digitally-Controlled Oscillator by ΣΔ </li></ul></ul></ul><ul><ul><ul><li>DCO Capacitor Mismatch Compensation </li></ul></ul></ul>
    6. 6. Motivation 3. Integration -> Miniaturization <ul><li>Digital Baseband is shrinking -> Challenge for RF Transceiver design </li></ul>130nm CMOS 15mm 2 S. F. Chen, Y. B. Lee, Bosen Tzeng, C. C. Tang, Charles Chiu, Rickey Yu, Ovid Lin, L. W. Ke, C. P. Wu, C. W. Yeh, P. Y. Chen, G. K. Dehng, “A GSM/EDGE Transmitter in 0.13-μm CMOS Using Offset Phase Locked Loop and Direct Conversion Architecture”, Proc. of IEEE RFIC Symposium pp. 581-584, June 2008. Cannot afford overhead in design to compensate for performance variations and mitigation of an impairment
    7. 7. Motivation 4. Built-In Self Test 1 <ul><li>Some calibration and compensation schemes can also serve as a means for screening defective parts. Examples: </li></ul><ul><ul><li>Calibration of oscillator current </li></ul></ul><ul><ul><li>Predistortion c alibration of an RF p ower a mplifier </li></ul></ul>1 O. Eliezer, I. Bashir, R. B. Staszewski, and P. T. Balsara, “Built-in Self Testing of a DRP-Based GSM Transmitter”, Proc. of IEEE RFIC Symposium pp. 339-342, June 2007.
    8. 8. Characteristics of Calibration & Compensation Processes <ul><li>Calibration: </li></ul><ul><ul><li>Sometimes performed in factory after assembly (when external measurements needed) </li></ul></ul><ul><ul><li>Certain calibrations are done at power-up (internal measurements) </li></ul></ul><ul><ul><li>Typically performed using on-chip digital logic and/or software </li></ul></ul><ul><ul><li>Primary purpose is to account for process variations </li></ul></ul><ul><ul><li>Sometimes done only once in a lifetime of the system </li></ul></ul><ul><ul><li>Results are stored in memory to be used for compensation </li></ul></ul><ul><li>Compensation: </li></ul><ul><ul><li>Performed before or while signal is transmitted or received </li></ul></ul><ul><ul><li>Performed using hardware and/or software </li></ul></ul><ul><ul><li>Primary focus is to account for environmental variations such as temperature changes etc. </li></ul></ul><ul><ul><li>Process is invoked for each packet transmitted/received or periodically </li></ul></ul>
    9. 9. DRP Fundamentals: TX Conventional vs. DRP <ul><li>Analog PLL: Charge pumps, loop filter </li></ul><ul><li>Analog control on oscillator </li></ul><ul><ul><li>Coarse control: Digital </li></ul></ul><ul><ul><li>Fine control: MOS varactor </li></ul></ul><ul><li>Loop used for frequency acquisition only </li></ul><ul><li>IQ (contains AM and PM) mixed with LO </li></ul><ul><li>Digital PLL: accumulator, sampler, loop filter, TDC </li></ul><ul><li>Digital control on oscillator </li></ul><ul><ul><li>Coarse control: Digital </li></ul></ul><ul><ul><li>Fine control: ΣΔ dithering on MOSCAP </li></ul></ul><ul><li>Loop used for frequency acquisition and PM </li></ul><ul><li>DPA used for AM modulation </li></ul>CONVENTIONAL DRP
    10. 10. DRP Fundamentals: DCO <ul><li>Cross coupled NMOS pair </li></ul><ul><li>Three banks of capacitors: PB(MIM), AB(MOS), TB(MOS) </li></ul><ul><ul><li>Coarse Tuning: PB, AB </li></ul></ul><ul><ul><li>Fine Tuning/Modulation: TB, TB operated by ΣΔ </li></ul></ul><ul><li>Operates on current limiting scheme. </li></ul>The voltage at the gate of the MOSCAP is not constant. OSCM OSCP
    11. 11. DRP Fundamentals: DPA <ul><li>NMOS transistors drain tied to a common node </li></ul><ul><li>Digital control on amplitude ACW (10-bit word) -> 1024 possible combinations </li></ul><ul><li>Fine control: </li></ul><ul><ul><li>1 1x transistor controlled by ΣΔ </li></ul></ul><ul><li>Coarse control: </li></ul><ul><ul><li>256 4x transistors </li></ul></ul><ul><ul><li>3 1x transistors </li></ul></ul>
    12. 12. DRP Fundamentals: DPA <ul><li>DPA transfer function is non-linear at high ACW -> Requires amplitude and phase predistortion </li></ul><ul><li>Predistortion calibration is done by the receiver. </li></ul>Envelope of RF Signal Higher the average power, more PPA transistors need to be engaged.
    13. 13. DRP Fundamentals: PHE <ul><li>The phase error signal PHE is the output of the loop’s phase detector </li></ul><ul><li>Computed and captured digitally </li></ul><ul><li>The processing (rms calculation) is software based. </li></ul>PHE serves as a ‘noise meter’ in DRP.
    14. 14. Mitigation of RF Oscillator Pulling Using Phase Adjustment <ul><li>Issue: </li></ul><ul><ul><li>PPA AM creates parasitic modulation on the DCO -> Degrades EVM and MODSPEC at high average power operation </li></ul></ul><ul><li>Root Cause: </li></ul><ul><ul><li>DCO Injection Pulling Theory </li></ul></ul><ul><ul><li>MOS Varactor C-V Theory </li></ul></ul><ul><li>Solution: </li></ul><ul><ul><li>Programmable control delay </li></ul></ul>
    15. 15. Mitigation of RF Oscillator Pulling Problem Statement <ul><li>The DCO is suffering from parasitic modulation caused by AM on PPA. </li></ul><ul><li>As a result most of the transmitter performance parameters including EVM and spectrum are degraded. </li></ul>Pulling is a function of process, temperature, and frequency.
    16. 16. Mitigation of RF Oscillator Pulling Measurement of Pulling <ul><li>The PPA is modulated with EDGE or sinusoid while the FM from DTX is turned off. </li></ul><ul><li>The DCO divided output (CKVD4) is routed out to a spectrum analyzer from test port. </li></ul><ul><li>In case of sinusoidal AM, the level of sideband from the carrier on CKVD4 spectrum determines the extent of FM. </li></ul>The characteristic of FM is on DCO is defined by the characteristic of AM on PPA.
    17. 17. Mitigation of RF Oscillator Pulling Root Cause: Injection Pulling 1 of DCO <ul><li>The aggressor I agg signal finds its way into the LC tank and pulls the oscillator I osc phase by γ . </li></ul><ul><li>γ is a function of magnitude of I agg and the angle between I osc and I agg Φ and determines the extent of pulling. </li></ul>1 Behzad Razavi, ”A Study of Injection Locking and Pulling in Oscillators,” IEEE Journal of Solid State Circuits, Vol 39, No. 9, pp. 1415-1424, September 2004. The focus of this theory is on the phase of the composite vector w.r.t. DCO γ . Worst pulling is when γ is maximum @ Φ = 90 ˚ .
    18. 18. Mitigation of RF Oscillator Pulling Root Cause: Injection Pulling of DCO <ul><li>Ideal MOSCAP </li></ul><ul><li>2 nd LC Tank tuned to 2 ∙f DCO . </li></ul><ul><li>BSIM3 0.18 μ m CMOS </li></ul><ul><li>AC coupling RC network </li></ul><ul><li>Dynamic FF </li></ul><ul><li>Attenuator to adjust ρ </li></ul><ul><li>Delay to adjust Φ </li></ul><ul><li>AM modulator, source: 10MHz sine-wave </li></ul><ul><li>VCVS for coupling voltage on the ground. </li></ul><ul><li>250pF bypass cap with Q of 50. </li></ul><ul><li>4.7 μ F external cap </li></ul><ul><li>Transient simulation up-to 350ns with 1ps step time. </li></ul>The simulation assumes an ideal MOSCAP . 1 2 3 4 5 7 8 9 10 11 12 6
    19. 19. Mitigation of RF Oscillator Pulling Root Cause: Injection Pulling of DCO Worst case pulling with -60dB aggressor ~10kHz at DCO/5kHz at div-2 output.
    20. 20. Mitigation of RF Oscillator Pulling Root Cause: MOSCAP C-V Asymmetry <ul><li>The aggressor I agg signal finds its way into the LC tank and changes the magnitude of composite vector I t to I t’ . </li></ul><ul><li>Magnitude of I t is a function of magnitude of I agg and the angle between I osc and I agg Φ and determines the extent of pulling. </li></ul>The focus of this theory is on the amplitude of the composite vector I t . Worst pulling is when γ is maximum @ Φ = 0 ˚ .
    21. 21. Mitigation of RF Oscillator Pulling Root Cause: MOSCAP C-V Asymmetry <ul><li>A step increase in DCO amplitude will change the average capacitance seen by the DCO that will in turn change the DCO frequency. </li></ul><ul><li>A periodically varying envelope (AM) on the DCO signal will create FM. </li></ul>The extent of AM on DCO will be maximum when the victim and aggressor are in phase @ Φ = 0 ˚ .
    22. 22. Mitigation of RF Oscillator Pulling Root Cause: MOSCAP C-V Asymmetry Estimate of pulling with -60dB aggressor MOSCAP model 1 1 From Chih-Ming Hung and process qualification team. Change in capacitance 4.1aF
    23. 23. Mitigation of RF Oscillator Pulling Effect of Oscillator Current Increasing victim amplitude will reduce γ and pulling. Increasing victim amplitude reduces the sensitivity of DCO frequency to AM on DCO -> less pulling .
    24. 24. Mitigation of RF Oscillator Pulling Effect of Loop bandwidth Increase loop bandwidth improves EVM but degrades spectrum.
    25. 25. Mitigation of RF Oscillator Pulling Effect of Delay b/w DCO & DPA <ul><li>In this experiment, the delay is changed by adjusting the supply of buffer. </li></ul><ul><li>The supply is varied from 1.2V to 2.0V in 100mV steps. The radio performance is measured from 1.6GHz to 2.1GHz in 10MHz steps. </li></ul>
    26. 26. Mitigation of RF Oscillator Pulling Effect of Delay between DCO and DPA <ul><li>The DCO is injection locked to the signal transmitter by port 1. The phase of the signal propagating throughout the network which includes the DCO and the PPA is received at port 2. The change in phase of S21 is recorded as VDDTRX supply varied from 1.2V to 2V while the differential buffer is turned on and off. </li></ul><ul><li>The phase of S21 suffers a 4˚ phase shift as the differential buffer is disabled. By lowering VDDTRX voltage by 100mV, the same S21 phase can be retained that results in optimum EVM performance. </li></ul>15 ˚ phase difference between worst and best EVM.
    27. 27. Mitigation of RF Oscillator Pulling Conventional Solutions <ul><li>Reduce Coupling Path </li></ul><ul><ul><li>Improve layout of DCO and PPA </li></ul></ul><ul><ul><li>Improve package design </li></ul></ul><ul><ul><li>Isolate VDD/GND/back-gate connections </li></ul></ul><ul><ul><li>Increase the substrate resistance </li></ul></ul><ul><li>Improve the robustness of victim against aggressor </li></ul><ul><ul><li>Increasing oscillator current </li></ul></ul><ul><ul><li>Reducing Q of LC tank </li></ul></ul><ul><ul><li>Increasing PLL loop bandwidth </li></ul></ul>
    28. 28. Mitigation of RF Oscillator Pulling Proposed Solution <ul><li>The proposed solution is to establish an optimum phase relationship between the RF oscillator and the PPA by using a programmable delay that is calibrated using ADPLL hardware. By delaying the phase of the DCO signal as it propagates to the PPA, the phase of the signal returning back to the DCO is increased to a point where the composite signal (as a result of adding the aggressor signal to the victim) results in the least parasitic modulation on the DCO. </li></ul>
    29. 29. Mitigation of RF Oscillator Pulling Calibration Results <ul><li>PHE estimation is performed on various delay settings (VDDTRX) and correlated with EVM. </li></ul>PHE can be used to sense degradation in EVM due to AM-FM.
    30. 30. Mitigation of RF Oscillator Pulling Issues with proposal <ul><li>Thermal noise degradation in signal path </li></ul><ul><li>Increased current consumption </li></ul><ul><li>Temperature compensation is complex </li></ul>
    31. 31. Calibration of DCO Current Problem Statement <ul><li>The oscillator noise performance varies over process and temperature. </li></ul><ul><li>These variations can be compensated by adjusting the bias setting. </li></ul><ul><li>Strong process -> ibias ↓ </li></ul><ul><li>Temperature ↑ -> ibias ↑ </li></ul><ul><li>Need a sensor for estimating DCO noise in order to calibrate bias setting </li></ul>
    32. 32. Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability. 400kHz Offset
    33. 33. Calibration of DCO Current Effect on Radio Performance R. Santucci, Waleed Khalil, and Dmitry Petrov, “Accurate Tuning and Calibration of Fractional-N Frequency Synthesizers,” Proc. of IEEE RFIC Symposium, “On-Chip Calibration, Compensation, and Filtering Techniques for Wireless SoCs,” Workshop, Session WSL-2, June 2008. The impact of DCO phase noise on system performance is more severe for dense modulation schemes.
    34. 34. Calibration of DCO Current Effect on Radio Performance Excessive DCO phase noise effects RMS Phase Error and spectrum performance of a GSM radio.
    35. 35. Calibration of DCO Current Proposed Solution <ul><li>Digital processing of ADPLL’s phase error signal </li></ul><ul><li>Noise of DCO is digitized </li></ul><ul><li>ADPLL operation in closed loop with narrow loop bandwidth. </li></ul>
    36. 36. Calibration of DCO Current Validation of Proposed Solution Optimum DCO current using PHE based estimation PHE based estimation of DCO noise correlates with the measured DCO integrated noise.
    37. 37. Calibration of DCO Current Issues with Proposed Solution <ul><li>Requires averaging over large number of samples -> Calibration time </li></ul><ul><li>The solution only covers calibration. Compensation is not possible. </li></ul><ul><li>PHE sensitivity is limited only to close in offsets < 1MHz -> cannot sense 20MHz DCO phase noise. </li></ul>
    38. 38. Mitigation of ΣΔ Noise on DCO Problem Statement <ul><li>Spectral growth at offsets between 300kHz – 5MHz from the carrier -> Marginal or failing spectrum performance </li></ul><ul><li>The extent of degradation is a function of the phase of ΣΔ clock adjusted by flyback delay circuit. </li></ul>
    39. 39. Mitigation of ΣΔ Noise on DCO Problem Statement <ul><li>Periodic behavior of RMS phase error and 400kHz modulated spectrum with delay. </li></ul><ul><li>Rate of periodicity (distance b/w peaks) is called Modulo. m fine =42. </li></ul>Once the modulo and worst ΣΔ clock phase is established, the optimum delay code would be half the modulo.
    40. 40. Mitigation of ΣΔ Noise on DCO Effect of DCO Frequency & Temp For a calibrated delay, a change in DCO frequency or temperature, requires a change in delay code to return to best phase for ΣΔ clock.
    41. 41. Mitigation of ΣΔ Noise on DCO Calibration Process <ul><li>Find the worst phase/delay setting out of all possible flyback codes using PHE x cal </li></ul><ul><li>Store x cal for each GSM band </li></ul>
    42. 42. Mitigation of ΣΔ Noise on DCO Compensation Process <ul><li>Read target frequency and inverter delay to compensate for effect of DCO frequency and temperature based on characterized empirical model. </li></ul>
    43. 43. Mitigation of ΣΔ Noise on DCO Lab Results <ul><li>Baseline vs. calibrated & compensated flyback delay performance </li></ul>
    44. 44. Mitigation of ΣΔ Noise on DCO Issues <ul><li>Too complex (to engineers) </li></ul><ul><li>Challenges in calibration on ATE in MMST due to coupling b/w sites </li></ul>
    45. 45. Predistortion Calibration of DPA Problem Statement <ul><li>Built-In Self-Calibration of AM-AM and AM-PM distortion of DPA for DRPe TM is a challenge </li></ul><ul><ul><li>On-chip DPA is much more non-linear than the external PA </li></ul></ul><ul><li>The proposed solution has to conform with VLCT environment with no RF generation and capture and minimum over-head. </li></ul>
    46. 46. Predistortion Calibration of DPA Conventional Approach <ul><li>Conventional approach: use expensive external RF test equipment to demodulate the output and analyze for the phase shift and amplitude linearity. </li></ul><ul><li>DRP-conventional approach: Couple TX into RX directly or indirectly (thru bond-wire) </li></ul><ul><li>Challenges in DRP-conventional approach: </li></ul><ul><ul><li>Calibration environment ≠ Application environment for </li></ul></ul><ul><ul><ul><li>Half-duplex systems -> An added uncertainty due to changes in LDO voltage </li></ul></ul></ul><ul><ul><ul><li>Systems sharing TX/RX port -> An added uncertainty due to changes in PPA load </li></ul></ul></ul><ul><ul><li>Requires 2x current: Strain on LDO design in future processes due to decreasing power supply voltages and transistor pitch. </li></ul></ul><ul><ul><li>Indirect Coupling -> Package dependent </li></ul></ul><ul><ul><li>Direct Coupling -> An added uncertainty due to phase response of SAW </li></ul></ul>
    47. 47. Predistortion Calibration of DPA Proposed Solution <ul><li>The proposed solution couples the DPA output into the reference input (FREF). </li></ul><ul><li>The transmitter is locked to the integer channel frequency with a 67-kHz offset. </li></ul><ul><li>The AM-PM conversion in the FREF slicer gives rise to a 67-kHz tone at PHE. </li></ul><ul><li>The amplitude and phase distortion from the DPA is estimated through this 67-kHz tone at PHE. </li></ul><ul><li>This method is also applicable when an external PA is coupled into FREF. </li></ul>Slicer converts AM on FREF signal to PM visible at PHE.
    48. 48. Predistortion Calibration of DPA Lab Validation Higher DPA Power -> More AM on FREF signal -> Higher the extent of PHE.
    49. 49. Predistortion Calibration of DPA Lab Validation
    50. 50. Predistortion Calibration of DPA Issues <ul><li>PHE is not sensitive enough at low DPA codes. Therefore, AM-AM and AM-PM distortion cannot be estimated in this region. </li></ul><ul><li>Excess Calibration time: Requires many samples and complex computations </li></ul>
    51. 51. Summary

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