Logic families- Propagation Delay, Fan - In and Fan - Out - Noise Margin - RTL ,TTL,ECL, CMOS - Comparison of Logic families - Implementation of combinational logic/sequential logic design using standard ICs, PROM, PLA and PAL, basic memory, static ROM,PROM,EPROM,EEPROM EAPROM.

1. Dr.C.Helen Sulochana
Prof/ECE
SXCCE
MEMORY DEVICES AND DIGITAL
INTEGRATED CIRCUITS

2. • UNIT V MEMORY DEVICES AND DIGITAL INTEGRATED
CIRCUITS
• Logic families- Propagation Delay, Fan - In and Fan - Out -
Noise Margin - RTL ,TTL,ECL, CMOS - Comparison of Logic
families - Implementation of combinational
logic/sequential logic design using standard ICs, PROM,
PLA and PAL, basic memory, static
ROM,PROM,EPROM,EEPROM EAPROM.

3. • Construct logic gates and use programmable
devices for digital applications
Course Outcomes

4. Digital integrated circuits
RTL-Resistor-transistor logic
DTL-Diode-transistor logic
TTL-Transistor-transistor logic
ECL-Emitter-coupled logic
MOS-Metal-oxide semiconductor
CMOS-Complementary metal-oxide semiconductor
IC digital logic families
IC - integrated circuit
 Assembly of electronic components, fabricated as a single unit
 combination of diodes, and transistors in a minimized form
Types of IC
1. Analog IC- Circuits deals with continuous analog signals
2. Digital IC-l Circuits deals with discrete digital signals

5. NAND and NOR implementation
Positive logic NAND gate
Positive logic NOR gate

6. Characteristics of digital IC
Used for the comparison of digital logic families
1. Fan-Out(loading)
 number of standard loads that can be connected to the
output of the gate without degrading its normal operation
 maximum number of inputs that can be connected to the
output of a gate
fan-out of the gate =
current source
current sink
High-level output
Low-level output

7. Example
fan-out of standard TTL is 10.
TTL gate can be connected to maximum of ten inputs of other gates in
the same logic family
Fan-in is a term that defines the maximum number of digital
inputs that a single logic gate can accept.
1. Fan-in

8. 2. Power Dissipation
amount of power needed by the gate
power delivered to the gate from the power supply
Vcc - supply voltage
Icc - current drawn by the circuit
IccH- current drawn when output of the gate is in high-voltage level
IccL- current drawn when output of the gate is in low-voltage level
average current =
average power dissipation =
TTL NAND gate average power dissipation = 10 mW
four NAND gates dissipates a total of 10 x 4 = 40 mW.

9. 3. Propagation Delay
total propagation delay of the circuit is =propagation delay of a gate x
number of logic levels in the circuit.
Amount of time required for a signal to propagate from the inputs to the output
The average propagation delay of the TTL gate is (tPHL+ tPLH)/2
For TTL NAND gate

10. Noise margin is the maximum noise voltage(undesirable voltages on
the connecting wires between logic circuits) added to an input signal
that does not cause an undesirable change in the circuit output.
Noise margin
noise margin is the difference VOH - V/H or VlL - VOL
VOL is the maximum voltage that the output can be in the low-level state
example
In TTL NAND gate VOH = 2.4 V, VOL = 0.4 V,
VlH = 2 V, and VlL = 0.8 V.
The high-state noise margin is
2.4 - 2 = 0.4 V,
low-state noise margin is 0.8 - 0.4 = 0.4 V.

11. RTL Basic Gate
basic circuit of RTL family is NOR gate
0.2 V for the low level
1 to 3.6 V for the high level.
 If any one of the input(A or B or C) is high, the corresponding
transistor output will be low
 If all inputs are low, all transistors are cut off (VBE< 0.6 V). The
output of the circuit is high(VCC)
noise margin for low input
signal is 0.6 - 0.2 = 0.4 V
power dissipation-- 12 mW
propagation delay - 25 ns.

12. 2. TRANSISTOR-TRANSISTOR LOGIC (TTL)
 most widely used family in the design of digital system(74 series)
 For comparing the various TTL series
speed-power product= propagation delay x power dissipation
types of output configuration
a. Open -collector output
b. Totem-pole output
c. Three-state (or tristate) output
designed with different resistor values to lower power dissipation and
higher speed
propagation delay decreases with decrease in storage time and RC time
constants
For lower resistances higher power dissipation

13. a. Open-Collector Output Gate
output
inputs
output high when Q 3 is off,
0.2 V for low level
2.4 to 5 V for high level.
Vcc is external to the IC package to pull the output to high voltage level when Q3 is off
otherwise, the output acts as an open circuit (output –low).
NAND gate
Used to drive a lamp or
relay
performing wired logic,
and for the construction of
a common-bus system.
Operation
If any one of the input is low, i.e A=0 or B=0 or C=0
Q1 is forward biased, The voltage across the base of Q2 is 0.9V
voltage need for Q3 to conduct is 1.8V.
Therefore Q3 is OFF, the voltage at the output Y is High

14. 2. increases the propagation delay (total load capacitance, charges
exponentially from low to high when output transistor goes from
saturation(output low) to cutoff (output high))
Disadvantage
1. low noise immunity (without the external resistor )
If all inputs are high i.e A = B = C= 1
base emitter junction of Q1 is reverse biased, The voltage across the
base of Q3 is greater than 1.2V
Therefore Q2 and Q3 conduct and saturate,
When output transistor Q3 saturates, the output voltage Y goes low to 0.2 V.
the voltage at the output Y is Low
This confirms the conditions of a NAND operation
The open-collector TTL gate will operate without the external resistor when connected
to inputs of other TTL gates
outputs of several open-collector TTL gates
are tied together with a single external
resistor, a wired AND logic is performed.
Wired-AND of two open-collector (oc) gates

15. totem-pole output is the same as open-collector gate, except output
transistor Q4 and the diode DI.
B .Totem-pole output
Active pull-up circuit replacing the
passive pull-up resistor RL ,to reduce the
propagation delay .
totem-pole output - transistor Q4 "sits"
upon Q3.
Operation
If any one of the input is low, i.e A=0 or B=0 or C=0
Q1 is forward biased, The voltage across
the base of Q2 is 0.9V
voltage need for Q3 to conduct is 1.8V.
Therefore Q3 is OFF,
 . Q4 conducts because its base is connected to Vcc
 voltage at the output Y is High
 The reason for placing the diode in the circuit is to provide a diode drop in the
output path and thus ensure that Q4 is cut off when Q 3 is saturated

16. Disadvantage
1.wired-logic connection is not allowed with totem-pole output
circuits.
2. excessive amount of current drawn when two totem-poles are
wired together with the output of one gate high and the output of
the second gate low
If all inputs are high i.e A = B = C= 1
base emitter junction of Q1 is reverse biased,
The voltage across the base of Q3 is greater than 1.2V
Therefore Q2 and Q3 conduct and saturate,
The voltage in the collector of Q2 is 0.9 V. Transistor Q4 is
cutoff because its base need 1.2 V, to start conducting
When output transistor Q3 saturates, the output voltage Y goes l
low to 0.2 V.
the voltage at the output Y is Low

17. a special type of totem-pole gate that allows the wired
connection of outputs for the purpose of forming a common-bus
system
C. Three-state (or tristate) gate
three output states:
(1)a low-level state when the lower transistor in the totem-pole is on
and the upper transistor is off,
(2)a high-level state when the upper transistor in the totem-pole is on
and the lower transistor is off
(3) third state when both transistors in the totem-pole are off.

18. control input C is high,
the gate is enabled and behaves like a normal buffer with the output equal to
the input binary value.
When the control input is low,
the output is an open circuit, which gives a high impedance (the third state)
regardless of the value of input A.
Three-state buffer gate
Three-state inverter gate
two small circles, one for the inverter output and the other to indicate
that the gate is enabled when C is low

19. Three-state TTL gate

20. Transistors Q6, Q7, and Q8 associated with the control input form a circuit similar to the
open collector gate.
Transistors Q I-Q5, associated with the data input, form a totem-pole TTL circuit.
The two circuits are connected together through diode D 1.
When control input C is low , transistor Q8 turns off
diode DI is non- conducting,
transistor Q 8 has no effect on the operation of the gate
output Y depends only on the data input at A
When the control input is high, transistor Q 8 turns on,
current flowing from Vcc through diode D I causes transistor Q8 to
saturate.
The voltage at the base of Q 5 is equal to 0.9 V, turns off Q5 and Q4
low input to one of the emitters of Q I forces transistor Q3 and Q2 to
turn off.
both Q3 and Q4 in the totem-pole are turned off and the output of the
circuit behaves like an open circuit with a very high output

21. Emitter Coupled Logic (ECL)
 fastest of all digital logic families
 high-speed operation is achieved By preventing the transistor from entering
into saturation.
 Very small voltage swing is necessary to switch between the two different
voltage levels. This cannot be achieved in TTL, as the transistors enter into
saturation mode, while in operation.
2-input ECL circuit
-0.8 V for high
-1.8 V for low state
Advantages

22. Outputs provide both the OR and NOR functions
Each input is connected to the base of a transistor.
circuit consists of a differential amplifier,
a temperature· and voltage· compensated bias network,
and an emitter follower output.
emitter outputs require a pull·down resistor(input resistor) for current to flow
If any input is high, the corresponding transistor is turned on and Q 5 is
turned off
. The current in resistor RC2 flows into the base of Q8 (provided there is
a load resistor).
This current is so small that only a negligible voltage drop occurs across
RC2
The OR output of the gate is high state.
The current flowing through RCI and the conducting transistor causes a
low state at the NOR output
Operation

23. If all inputs are at low level, the corresponding transistor is turned OFF
and Q 5 is turned ON
RC2 draws current through Q 5 that make the OR output to
low level
current in RCI is negligible and the NOR output is at high level.
 It has noise immunity worst compare to both TTL and CMOS.
 It has power per gate of about 4 to 55 mW. This power consumption
figure is higher compare to both TTL and CMOS
Disadvantages

24. CMOS(COMPLEMENTARY METAL OXIDE SEMICONDUCTOR)
 both n-channel and p-channel devices can be fabricated on the
same substrate
 basic circuit is the inverter - consists of one p-channel transistor and
one n -channel transistor
Inverter
n-channel MOS conducts when its gate-to-source voltage is positive
The p-channel MOS conducts when its gate-to-source voltage is
negative.
Either type of device is turned off if its gate-to-source voltage is
zero
When the input is low, both gates arc at zero potential.
p-channel device is turned on and the n-channel device is turned off.
a low-impedance path from VDD to the output and a very high-impedance
path from output to ground.
output voltage approaches the high level
When the input is high, both gates are at VDD
The p-channel device is off and the n-channel device is on.
The output approaches the low level of 0 V.

25.  NAND gate consists of two p-type units in parallel
and two n-type units in series,
 If all inputs are high, both p-channel transistors
turn off and both n-channel transistors turn on.
 The output has a low impedance to ground and
produces a low state.
 If any input is low, the associated n-channel
transistor is turned off and the associated p-
channel transistor is turned on.
 The output is coupled to VDD and goes to the high
state.
NAND gate
NOR gate
NOR gate consists of two n-type units in parallel
and two p-type units in series
 When all inputs are low, both p-channel units
are on and both n-channel units are off.
 The output is coupled to VDD and goes to the
high state.
 If any input is high, the associated p-channel
transistor is turned off and the associated n-
channel transistor turns on.
 This connects the output to ground, causing a
low level output.

26. power dissipation is very low(always an off transistor in the current
path when the state of the circuit is not changing.)
reduces the propagation delay time and improves the noise margin,
The fan-out decreases with increase in frequency of operation
fabrication process is simpler than TTL
provides a greater packing density. more circuits can be placed on a
given area of silicon
Advantages

27. Basic memory structure
Primary memory(RAM and ROM)
Secondary memory(hard drive,CD,etc.).
Types of memory in Digital system
Memory unit: A device to which binary information is stored(write), and
from which information is retrieved(read) when needed for processing.
 memory unit is a collection of cells capable of storing a large
quantity of binary information
1. Read‐Only Memory (ROM).
2. Random‐Access Memory (RAM)

29. Read-only memory (ROM)
ROM block diagram k - input lines(address), decoded into 2k - address.
If 2n distinct addresses in a ROM, there are 2k
distinct words are stored in the unit.
n - output lines,.
m - number of bits in each word
total number of bits stored – 2k x n.
An output word can be selected by a unique address
32 x 8 ROM
32 words of 8 bits each
25 = 32, 5 –address lines
each address input, there is a unique selected word.
 ROM is a nonvolatile memory used in computers and other electronic devices.
 Data is permanently stored cannot be electronically modified once programmed
 Read the data, but cannot write again and again
Example
Function of a ROM
1. implements any combinational circuit
2. Store fixed pattern of bit strings called words

30. 32 x 8 ROM
The blowing of the fuses is referred to as programming the ROM
Construction of ROM
 ROM includes both decoder and the OR gates within a single IC
package.
 k address lines are decoded in to 2k words. Each word is connected to
n output lines through OR gate and fuses

31. 32 x 4 ROM

32. Types of ROMs
Programming ways of ROM
 Mask programming
-done by the manufacturer during fabrication process
- makes the corresponding mask for the paths to produce the I's and 0's
according to the customer's truth table.
- economical only if large quantities are to be manufactured.
 Programmable read-only memory
- allows the user to program the unit in the laboratory after
manufacturing
-more economical
1.Programmable read-only memory
2. EPROM (Erasable Programmable read only
memory)
3. EEPROM (Electrically erasable
programmable read only memory)

33. 1. Programmable read-only memory
 fuses in the PROM are blown by application of current pulses through
the output terminals.
 A blown fuse defines one binary state and an unbroken link
represents the other state.
 It can be programmed by user. Once programmed, the data and
instructions in it cannot be changed.
The process of programming the PROM is called as burning the
PROM
 procedures for programming ROMs are hardware procedures, which
is irreversible

34.  non-volatile memory(retain the data even if there is no power)
 The data can be erased and reprogrammed by ultra violet light exposure for a
given length of time.
 The data on EPROM can be erased a limited number of times because excessive
erasing damages the silicon dioxide layer
2. EPROM (Erasable Programmable read only memory)
 previously programmed connections can be erased with an electrical signal
without removing it from its socket
3.EEPROM (Electrically erasable programmable read only memory)
S.NO PROM EPROM
1
Programmable read only
memory
Erasable Programmable read
only memory
2.
Non volatile
not reusable.
Non volatile
reusable multiple times.
3. inexpensive. costlier than PROM.
4.
irreversible, it’s memory is
permanent.
processes can be reversed.
5.
flexibility and scalable than
EPROM.
less flexibility and scalability.

35. Programmable Logic Devices
1.SPLDs (Simple Programmable Logic Devices)
ROM (Read-Only Memory)
PLA (Programmable Logic Array)
PAL (Programmable Array Logic)
2. HCPLD (High Capacity Programmable Logic Device)
FPGA (Field-Programmable Gate Array)
electronic component used to
build reconfigurable digital circuits.
classification

36. Combinational Logic Implementation using ROM
1.Implement the following Boolean function using ROM
Example . 1
solution
1.Write the Boolean
expression for output
2. ROM programming
ROM with AND-OR gates
8 x 2 ROM

37. ROM with AND-OR-INVERT gates
(product of sum)
ROM with AND-OR gates
(sum of product )
4 x 2 ROM

38. 2.Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and
generates an output binary number equal to the square of the input number
Example . 2
solution 1.Write the Truth & Boolean expression for output
B0 = A0
B1 = 0
Need 4 output lines
B2 to B5
ROM size 8 x 4
ROM truth table
ROM implementation

39. PROGRAMMABLE LOGIC ARRAY (PLA)
 PAL is similar to PROM(OR array –programmed) except
decoder(array of AND gates) can be programmed to generate the
required Boolean functions(minterms)
 AND and OR gates inside the PLA are initially fabricated with fuses
 Boolean functions are implemented in sum of products form by
blowing appropriate fuses and leaving the desired connections
PLA block diagram
size of the PLA =number of inputs, the number of product terms, and
the number of outputs
size =n x k x m

40. Internal structure of PLA
size =3 x 3 x 2

41. Both the true value and the complement of each function should be
simplified
Simplified function is expressed with fewer product terms and which
one provides product terms that are common to other functions
The output is inverted when the complement of the function is
implemented
The output does not complemented when true value of the function is
connected
Procedure for Boolean function implementation
Each input and its complement are connected through fuses to the
inputs of all AND gates.
outputs of the AND gates are connected through fuses to each input
of the OR gates.
Boolean functions are programmed by blowing selected fuses and
leaving others(unbroken)
Two more fuses are provided with the output inverters.

42. Implement the following two Boolean functions with a PLA
Example . 1
Step. 1- true value and the complement of the functions are simplified into
sum‐of‐products form.
solution
combination that gives minimum
number of product terms
Step. 2
𝐹1 ′ and 𝐹2
Form PLA programming table
Step. 3
PLA programming table

43. Form PLA programming table
Step. 3
F2
F1’ F1

44. PROGRAMMABLE ARRAY LOGIC(array logic)(PAL)
Device with a fixed OR array and a programmable AND array
easier to program, but not flexible as PLA
array logic symbols for a multiple-input AND gate
Conventional symbol
Array logic symbol
Three wide, indicate there are three programmable AND gates in each
section
 PAL integrated circuit may have eight inputs, eight outputs, and eight
sections, each consisting of an eight‐wide AND–OR array.
 The output terminals are sometimes connected to inverters.

45. typical PAL with four inputs and four outputs
Three wide

46. Implement the following Boolean functions with a PAL
Example . 1
solution
Simplifying the four functions to a minimum number of terms
Step. 1
Form the PAL programming table
Step. 2

49. Comparison between PLA and PAL