This document describes a thesis submitted by Pushpak Dagade for the degree of Master of Technology in Integrated Electronics & Circuits. The thesis proposes a new successive approximation pipelined (SAP) ADC architecture to overcome speed limitations of traditional SAR ADCs. It presents the design of a 8-bit SAP ADC including components like a D flip-flop, comparator, and DAC. Simulation results demonstrating the SAP ADC's operation are also included. The thesis concludes with proposals for further work on the schematic, layout, and post-fabrication testing.

1. A High Speed Successive
Approximation Pipelined ADC
A thesis submitted in partial fulfilment
of the requirements for the degree of
MASTER OF TECHNOLOGY
IN
INTEGRATED ELECTRONICS & CIRCUITS
By Pushpak Dagade
Under the guidance of:
Prof. G. S. Visweswaran
June 2014
Department of Electrical Engineering,
Indian Institute of Technology, Delhi.

2. Certificate
This is to certify that the thesis titled A High Speed Succes-
sive Approximation Pipelined ADC being submitted by the
student Pushpak Dagade for the award of Master of Technol-
ogy in Integrated Electronics & Circuits is a record of bonafide
work carried out by him under my guidance and supervision at the
Department of Electrical Engineering, IIT Delhi. The work
presented in this thesis has not been submitted elsewhere either in
part or full, for the award of any other degree or diploma.
Prof. G. S. Visweswaran,
Department of Electrical Engineering,
Indian Institute of Technology, Delhi

3. Acknowledgements
I would like to express my sincere gratitude to my supervisor and
guide, Prof. G. S. Visweswaran. He has always been patient and
believed in my work, even though I have my bachelors degree from a
non electrical engineering department. His guidance and suggestions
throughout the development of my project have been invaluable.
I would like to thank my parents for their constant moral support,
without which this project would have not been possible.
I would also like to thank my friend, Akshat Agrawal, for helping
me complete my thesis on time and for reviewing the same. His help
and suggestions were priceless.
Lastly, I would like to thank my other friends and other family mem-
bers who have directly or indirectly helped me with my project.
Pushpak Dagade

4. Acronyms
ˆ ADC: Analog to Digital Converter
ˆ DAC: Digital to Analog Converter
ˆ SAR ADC: Successive Approximation Register Analog to Dig-
ital Converter
ˆ SAP ADC: Successive Approximation Pipelined Analog to
Digital Converter
ˆ TI ADC: Time Interleaved Analog to Digital converter
ˆ LSB: Least Significant Bit
ˆ MSB: Most Significant Bit
i

5. Contents
List of Figures iv
1 Introduction 1
1.1 Successive Approximation Algorithm . . . . . . . . . 2
1.2 Successive Approximation ADCs . . . . . . . . . . . 3
1.2.1 SAR ADC . . . . . . . . . . . . . . . . . . . . 3
1.2.2 TI SAR ADC . . . . . . . . . . . . . . . . . . 5
1.2.3 SAP ADC . . . . . . . . . . . . . . . . . . . . 6
1.3 Aim of the Project . . . . . . . . . . . . . . . . . . . 6
1.4 Organization of this thesis . . . . . . . . . . . . . . . 6
2 SAP ADC Architecture 8
2.1 Design of 1-bit stage . . . . . . . . . . . . . . . . . . 8
2.2 SAP ADC architecture . . . . . . . . . . . . . . . . . 11
2.3 Comparison: TI SAR ADC vs. SAP ADC . . . . . . 13
2.4 Critical path for delay . . . . . . . . . . . . . . . . . 15
3 SAP ADC Design 16
3.1 D flip flop . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Design . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2 Simulation Results . . . . . . . . . . . . . . . 17
3.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Design . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Simulation Results . . . . . . . . . . . . . . . 26
3.3 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.1 Design . . . . . . . . . . . . . . . . . . . . . . 30
3.3.2 Simulation Results . . . . . . . . . . . . . . . 33
ii

6. 4 SAP ADC Simulation Results 39
4.1 Specifications . . . . . . . . . . . . . . . . . . . . . . 39
4.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3 Simulation Results . . . . . . . . . . . . . . . . . . . 40
4.4 Corner Analysis . . . . . . . . . . . . . . . . . . . . . 40
4.5 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Conclusions 43
6 Future Work 44
6.1 Schematic Work . . . . . . . . . . . . . . . . . . . . . 44
6.2 Layout Work . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Post Tapeout Work . . . . . . . . . . . . . . . . . . . 45
Appendices 46
A Optimization 47
B Softwares 49
References 50
iii

7. List of Figures
1.2.1 8-bit SAR ADC Architecture . . . . . . . . . . . . . 4
1.2.2 8-bit TI SAR ADC Architecture . . . . . . . . . . . 5
2.0.1 8-bit SAP ADC architecture with a generic 8 stage
pipeline . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 kth
1-bit stage of Figure 2.0.1 . . . . . . . . . . . . 10
2.2.1 8-bit SAP ADC complete architecture . . . . . . . . 12
3.1.1 Clock skew insensitive D flip flop . . . . . . . . . . 17
3.1.2 Demonstrating setup time & propagation delay of
D flip flop . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 High speed, high gain comparator block diagram . . 19
3.2.2 NMOS input pre-amplifier . . . . . . . . . . . . . . 20
3.2.3 Latch Stage for NMOS input comparator . . . . . . 21
3.2.4 Post-amplifier stage . . . . . . . . . . . . . . . . . . 21
3.2.5 NMOS input comparator . . . . . . . . . . . . . . . 22
3.2.6 PMOS input comparator . . . . . . . . . . . . . . . 24
3.2.7 Comparator with rail-to-rail ICMR . . . . . . . . . 25
3.2.8 Comparator Symbol . . . . . . . . . . . . . . . . . . 26
3.2.9 Comparator DC characteristics . . . . . . . . . . . 27
3.2.10 Comparator transient characteristics . . . . . . . . 29
3.3.1 n-bit current steering DAC topology . . . . . . . . 30
3.3.2 2-stage differential opamp with feedback . . . . . . 31
3.3.3 Current steering circuit for n-bit DAC . . . . . . . . 32
3.3.4 Frequency responses of opamp in open & closed loop 34
3.3.5 2-bit, 3-bit, 4-bit & 5-bit DAC DC characteristics . 35
3.3.6 6-bit & 7-bit DAC DC characteristics . . . . . . . . 36
3.3.7 8-bit DAC DC characteristics . . . . . . . . . . . . 37
3.3.8 DAC transient characteristics . . . . . . . . . . . . 38
iv

8. 4.2.1 The SAP ADC testbench . . . . . . . . . . . . . . . 40
4.3.1 Example of output waveform generated by SAP ADC
for a sinusoidal input. . . . . . . . . . . . . . . . . . 41
A.0.1 Circuit optimization flowchart . . . . . . . . . . . . 48
v

9. Abstract
SAR ADCs are commonly used data converters but their usage is
limited to low speed applications. This is due to a fundamental
limitation in the implementation of SAR ADCs. Its internal com-
ponents have to work at a much higher frequency than the sampling
frequency. This limits the maximum sampling speed at which they
can be operated. This thesis discusses a new architecture based on
SAR ADCs which overcomes this implementation limitation. We
call it as Successive Approximations Pipelined ADC (SAP ADC).
This ADC can be used for very high speed data conversion appli-
cations, while still using the successive approximations algorithm.
A 8-bit SAP ADC architecture is designed to establish the valid-
ity of this architecture and demonstrate its potential in high speed
conversion applications.
vi

10. 1
Chapter 1
Introduction
An analog signal can take any value from a continuous set of infinite
possible values. Efficiently processing such an infinite set of signals is
very difficult, and is practically impossible. Moreover, analog signals
are prone to noise, i.e. it is difficult to isolate noise from original
signal since an analog signal can assume any value. Digital signals
on the other hand can assume a value from a set of only 2 elements,
0 and 1. Hence, they are much easier to process and less susceptible
to noise. Besides these, there are many other reasons why digital
signals are preferred over analog signals.
However, since all signals in the real world are analog in nature,
it is very important to accurately convert these analog signals into
their equivalent digital representations. This conversion task is done
by class of devices called as ADCs or Analog-to-Digital converters.
Often ADCs are a bottleneck in the performance of practical appli-
cations due to their limited speed and accuracy.
Successive Approximation is a one of various algorithms used to
realise an ADC, and it would be the algorithm of concern in this
thesis.

11. 1.1. Successive Approximation Algorithm 2
1.1 Successive Approximation Algorithm
This is an iterative algorithm based on binary search. It works as
follows -
ˆ The input analog signal to be converted to its corresponding
digital output is first compared with the analog equivalent of a
digital signal with MSB as 1 (high) and all other bits as 0 (low)
ˆ If the input analog signal is larger in magnitude, the MSB of
the output digital signal is set as 1 (high), otherwise is set as
0 (low). Thus, in the first step, the MSB of the output digital
signal gets decided.
ˆ In the next step, the same input analog signal is compared with
the analog equivalent of a digital signal whose MSB is set to
the same value as the MSB of the output digital signal (decided
in the previous step), the 2nd
MSB set as 1 (high) and all other
bits set as 0 (low).
ˆ If the input analog signal is larger in magnitude, the 2nd
MSB
of the output digital signal is set as 1 (high), otherwise is set as
0 (low). In the second step, the 2nd
MSB of the output digital
signal now gets decided.
ˆ Likewise, the above steps are repeated until all the bits of the
output digital signal have been found.
As many steps are required for the algorithm to complete as the
resolution of the ADC. Optionally, 1 more step might be required
for the algorithm to complete, depending on how it is implemented.

12. 1.2. Successive Approximation ADCs 3
1.2 Successive Approximation ADCs
From the algorithm outlined in the previous section, 1.1, it can be
observed that we atleast need the following components to realise
an ADC based on successive approximation algorithm:
ˆ A Comparator: For comparing two analog signals at a time
ˆ A Digital-to-Analog converter (DAC): For converting a digital
signal to its analog equivalent for comparison
ˆ A Sample & Hold: For holding the input analog signal still
while the conversion process gets completed
1.2.1 SAR ADC
An ADC, commonly available in the literature, based on this al-
gorithm is the Successive Approximation Register ADC, commonly
called as SAR ADC. Figure 1.2.1 shows the block diagram of a typ-
ical SAR ADC. Besides the above mentioned components, a SAR
ADC additionally requires a control logic, to guide the conversion
process, and a clock generator.
Since the successive approximation algorithm (Section 1.1) is it-
erative in nature, the internal components need to operate at a much
higher frequency than the frequency of the input clock signal. This
higher frequency is as much as (resolution + 1) times higher and is
generated by the clock generator. This is a major problem. Con-
sequently, the use of SAR ADCs is restricted to medium
speed and medium resolution conversion operations.

13. 1.2. Successive Approximation ADCs 4
CMP.
SAR Control Logic
DAC
Clock
Generator
Sample
and
Hold
VinCLK
Digital
Output8
Figure 1.2.1: 8-bit SAR ADC Architecture

14. 1.2. Successive Approximation ADCs 5
1.2.2 TI SAR ADC
To get over the speed limitations of SAR ADC (while still using
successive approximation algorithm), multiple SAR ADCs can be
used in parallel, wherein each SAR ADC operates at a phase shifted
sampling clock. This new ADC, commonly known as the Time In-
terleaved SAR ADC or TI SAR ADC, can offer higher sampling
speeds 1
. Figure 1.2.2 shows the block diagram of a TI SAR ADC.
8:1
8-bit
MUX
High
Speed
S&H
Digital
Output
Vin
CLK
Select
Line
8-bit SAR ADC
CLK5
.
8-bit SAR ADC
CLK4
.
8-bit SAR ADC
CLK3
.
8-bit SAR ADC
CLK8
8-bit SAR ADC
CLK7
.
8-bit SAR ADC
CLK6
.
8-bit SAR ADC
CLK2
.
8-bit SAR ADC
CLK1
.
Figure 1.2.2: 8-bit TI SAR ADC Architecture. CLK1, CLK2, ..., CLK8 operate
at the same frequency, but are delayed with respect to each other and have a
duty cycle of 12.5%. CLK operates at 8 times the frequency of CLK1, CLK2, ...,
CLK8. [3]
1
higher by a factor of the number of SAR ADCs used in parallel

15. 1.3. Aim of the Project 6
1.2.3 SAP ADC
Instead of blindly repeating multiple SAR ADCs to get higher sam-
pling speed, as done in TI SAR ADC, we can achieve higher sampling
speed using lesser number of resources if pipelining is introduced in
the control logic of SAR ADC. This ADC architecture is new and
is not available in literature. We call it as Successive Approxima-
tion Pipelined ADC, or SAP ADC. This architecture is main topic of
concern for this thesis and has been explained in detail in the next
chapter, Chapter 2.
Note that a SAP ADC is not the same as Pipelined ADC,
which is commonly encountered in literature. Pipelined
ADCs employ multiplying DACs (MDACs), whereas no
MDACs are used in SAP ADC. This is a new architecture
and is not available in the current literature.
1.3 Aim of the Project
The aim of this project is to design a 8-bit Successive Approximation
Pipelined (SAP) ADC and demonstrate that this new architecture
is capable of supporting higher sampling speeds. The design is done
in UMC 130nm technology.
1.4 Organization of this thesis
This thesis is organized as follows:
ˆ Chapter 2 explains the architecture of SAP ADC in detail.
ˆ Chapter 3 discusses the design of each designed component
alongwith their individual simulation results.

16. 1.4. Organization of this thesis 7
ˆ Chapter 4 shows simulation results for the complete SAP ADC
after putting all the designed components together.
ˆ Chapter 5 concludes this thesis.
ˆ Chapter 6 gives an ordered list of possible future work.
ˆ Appendices A & B give some information on circuit optimiza-
tion and softwares used.

17. 8
Chapter 2
Successive Approximation
Pipelined ADC Architecture
As discussed briefly in Section 1.2.3, SAP ADC has a pipelined ar-
chitecture. Figure 2.0.1 shows block diagram of a SAP ADC with
a generic 8-stage pipeline. This block diagram is common for any
pipelined architecture, but the novelty here comes in the design of
the 1-bit stages.
2.1 Design of 1-bit stage
Figure 2.1.1 shows the design of the kth
1-bit stage (where 1 ≤ k ≤
8). It consists of a comparator, a sample & hold and a k-bit DAC.
The connections of the kth
1-bit stage with the rest of the SAP ADC
architecture are as follows:
ˆ The output of the comparator goes to the kth
group of shift
registers, which eventually forms the digital output bk of the
SAP ADC.
ˆ For 2 ≤ k ≤ 8, (k-1) MSBs of total k inputs to the DAC come
from the shift registers at the stages 1 to (k-1) respectively.

18. 2.1. Design of 1-bit stage 9
Dff
Dff
Dff
Dff
Dff
Dff
1-bit
Stage
1-bit
Stage
1-bit
Stage
1-bit
Stage
Vin
b1
b2
b7
b8
8-bit
shift
register
7-bit
shift
register
Digital
Output
DffDff
Figure2.0.1:8-bitSAPADCarchitecturewithageneric8stagepipeline

19. 2.1. Design of 1-bit stage 10
CMP.
Sample
and
Hold
(8-k) times
delayed CLK
+ -
8
To shift registers
above this stage
To next
stage S&H
From previous
stage S&H
From shift registers
of previous stages
k-bit DAC
Figure 2.1.1: kth
1-bit stage of Figure 2.0.1 (1 ≤ k ≤ 8)

20. 2.2. SAP ADC architecture 11
The last remaining input to the DAC, the LSB, is held as high
(logic 1) always.
ˆ The DAC of the first 1-bit stage (k = 0) is a special case and
reduces to a much simpler circuit. The only input to the 1-bit
DAC, which is also its LSB, has to be kept high (logic 1) as
mentioned in previous point. Consequently, this DAC always
has its output as V dd
2 and can be simply replaced with a resistive
divider.
ˆ For 2 ≤ k ≤ 8, the sample & hold takes its input from the
output of the sample & hold in the (k − 1)th
stage. Its output
acts as an input for the sample & hold in the next stage. The
input to sample & hold in the first stage (k = 0) is the analog
input to the SAP ADC.
ˆ The clock input given to the sample & hold needs to delayed
(8 − k) times. For the 8th
stage, the delay is 0, i.e. it directly
takes the main clock input.
2.2 SAP ADC architecture
Using the above rules, when the 1-bit stages in Figure 2.0.1 are
replaced by their designs of Figure 2.1.1, a complete architecture
of SAP ADC is obtained. This is shown in Figure 2.2.1. A few
interesting points can be noted:
ˆ All the DACs have their LSBs as high (logic 1). So, a k-bit
DAC behaves like a (k-1)-bit DAC with an offset in its output.
ˆ The group of 8 sample & hold circuits behave as an 8-bit analog
shift register. This is because the output of the sample & hold

21. 2.2. SAP ADC architecture 12
VrefVin
Vout
Cmp
Vout
DAC−1bit
b0
b0
DCLK
QQ_bar
CLK_bar
Dff
VoutVinDigitalDelay
CLK
Vin
CLK_bar
Vout
S&H
CLK
Vin
CLK_bar
Vout
S&H
VoutVinDigitalDelay
CLK
Vin
CLK_bar
Vout
S&H
VrefVin
Vout
Cmp
VoutVinDigitalDelay
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
Vout
DAC−2bit
b0
b0
b1
b1
CLK
Vin
CLK_bar
Vout
S&H
VrefVin
Vout
Cmp
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
VoutVinDigitalDelay
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
Vout
DAC−3bit
b0
b0
b1
b1
b2
b2
CLK
Vin
CLK_bar
Vout
S&H
VrefVin
Vout
Cmp
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
VoutVinDigitalDelay
CLK
Vin
CLK_bar
Vout
S&H
VrefVin
Vout
Cmp
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
VoutVinDigitalDelay
CLK
Vin
CLK_bar
Vout
S&H
VrefVin
Vout
Cmp
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
VoutVinDigitalDelay
CLK
Vin
CLK_bar
Vout
S&H
VrefVin
Vout
Cmp
DCLK
QQ_bar
CLK_bar
Dff
DCLK
QQ_bar
CLK_bar
Dff
Vout
DAC−4bit
b0
b0
b1
b1
b2
b2
b3
b3
Vout
DAC−5bit b0
b0
b1
b1
b2
b2
b3
b3
b4
b4
Vout
DAC−6bit
b0
b0
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
Vout
DAC−7bit
b0
b0
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
b6
b6
b0
Vout
DAC−8bit
b0
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
b6
b6
b7
b7
VrefVin
Vout
Cmp
DCLK
QQ_bar
CLK_bar
Dff
b1
b2
b3
b4
b5
b6
b7
b8
Vin
CLK
Figure2.2.1:8-bitSAPADCcompletearchitecture.TheconnectionstotheclockinputsandcomplementaryoutputsoftheD
flipflopshavenotbeenshowntoavoidcongestionofwiresintheimage.

22. 2.3. Comparison: TI SAR ADC vs. SAP ADC 13
circuit in the kth
stage in a given clock cycle becomes the output
of the following sample & hold circuit in the next clock cycle,
just like in a digital shift register. However, note that the input
being shifted is analog in nature and hence it is not a regular
digital shift register.
ˆ The delays in the input clocks given to the sample & hold are
required so that the group of sample & hold circuits behave
correctly as an analog shift register. If all of them are given
the same clock input, without any delay, all the sample & hold
circuits would become transparent at the same time. This is
not desirable.
ˆ The smallest non zero delay in the clock inputs of sample & hold
circuits (which comes for the sample & hold in the 7th
stage)
should be as small as possible. Infact, if one simply introduces
the clock from the last stage in the layout, the interconnect
delays would automatically account for this delay. No clock
tree synthesis should be required for the clock inputs of the
sample & hold circuits.
2.3 Comparison: TI SAR ADC vs. SAP ADC
It was briefly mentioned in section 1.2.3 that a SAP ADC can offer
as high sampling speeds as TI SAR ADC does, but with the use of
lesser number of resources. As the SAP ADC architecture has been
explained, this statement can now be verified. Table 2.1 compares
the quantities of various components required for a 8-bit TI SAR
and a 8-bit SAP ADC. (Refer to Figures 1.2.1, 1.2.2 and 2.2.1)
From the table, it can observed that a 8-bit TI SAR ADC requires
8 8-bit DACs, whereas a 8-bit SAP ADC requires only 7 DACs,

23. 2.3. Comparison: TI SAR ADC vs. SAP ADC 14
Major Components
Quantity
TI SAR ADC SAP ADC
8-bit DAC 8 1
7-bit DAC 0 1
6-bit DAC 0 1
5-bit DAC 0 1
4-bit DAC 0 1
3-bit DAC 0 1
2-bit DAC 0 1
8-bit MUX 1 0
Comparator 8 8
Control Logic 8 0
Table 2.1: Comparison among quantities of major components required in TI
SAR and SAP ADC respectively. The common components operate at the same
frequency
of which there is only 1 8-bit DAC and the rest are smaller ones.
Moreover, no control logic is required in the SAP ADC, while as
many as 8 such components are required in TI SAR ADC. Also
remember that the common components operate at same frequency
in both cases.
Thus, as lesser1
number of resources are required, while still op-
erating at the same frequency in both cases, the SAP ADC is
better in terms of both area and power consumption than
the SAR ADC, while still giving higher sampling speeds.
1
Shift registers (D flip flops) are required in SAP ADC unlike in TI SAR ADC. But the area
and power consumed by them would be much smaller than those by the control logic. So the
above statement in bold holds true.

24. 2.4. Critical path for delay 15
2.4 Critical path for delay
Before starting the design, it is important to analyze the critical path
for delay of the SAP ADC architecture. This would help understand
the maximum sampling speed achievable and accordingly decide the
specifications for the design of the individual components.
From 2.2.1, it can be seen that the critical path for delay
consists of a D flip flop, followed by a DAC, followed by a
comparator, followed by another D flip-flop. This is assum-
ing the sample & hold is faster than the ‘D flip flop followed
by DAC ’combination.
The equation for deciding the clock period T is then given by -
T < DffPropagation Delay + DACSettling Time
+ ComparatorSettling Time + DffSetup Time
(2.4.1)
In the above equation, hold time of the D flip flop and skew &
jitter of the clock have been ignored.

25. 16
Chapter 3
Successive Approximation
Pipelined ADC Design
A 8-bit SAP ADC is to be designed in UMC 130nm. Since the
aim of this thesis is to show that the SAP ADC architecture can
work at high sampling speeds, the components are designed with as
better specifications as possible. Equation 2.4.1 is kept handy while
designing.
3.1 D flip flop
3.1.1 Design
A D flip flop with setup time < 50ps and propagation delay
< 50ps is designed.
The topology used is modified C2
MOS, as shown in Figure 3.1.1.
This topology is chosen since its working is not affected by presence
of skew in clock signal. Also, its response is very quick. These factors
make it a better choice as compared to other commonly used D flip
flop topologies.
C2
MOS registers are prone to charge leakage [1] i.e. the out-
put signals Q and ¯Q do not get pulled to full VDD or full ground.

26. 3.1. D flip flop 17
Vdd Vdd Vdd Vdd
Vin
CLK
CLK
CLK
CLK
Q Q
Vdd Vdd
Figure 3.1.1: Clock skew insensitive D flip flop
Hence, the conventional C2
MOS structure (given in [1]) is modified
by cascading it with inverters to get full rail-to-rail output swing.
3.1.2 Simulation Results
Figure 3.1.2 demonstrates the setup time and propagation delay
specifications of the flip flop. The input D is chosen such that it
changes exactly 50ps before the rising edges of the clock. The output
Q changes correctly after the rising clock edge, which demonstrates
that the setup time is less than 50ps. Also, the outputs Q and ¯Q
appear within 50ps after the clock edge, which demonstrates that
the propagation delay of the D flip flop is less than 50ps.

27. 3.1. D flip flop 18
0.0 0.5 1.0 1.5
0.0
0.3
0.6
0.9
1.2
CLK(V)
0.0 0.5 1.0 1.5
0.0
0.3
0.6
0.9
1.2
D(V)
0.0 0.5 1.0 1.5
0.0
0.3
0.6
0.9
1.2
Q(V)
0.0 0.5 1.0 1.5
Time (ns)
0.0
0.3
0.6
0.9
1.2
¯Q(V)
Figure 3.1.2: Demonstrating setup time & propagation delay of D flip flop. Input
D changes 50ps before the rising clock edges, but is still picked up correctly by the
flip flop (setup time). Q & ¯Q appear within 50ps after the clock edge (propagation
delay).

28. 3.2. Comparator 19
3.2 Comparator
3.2.1 Design
A comparator with resolution 1 LSB, delay < 500ps and
rail-to-rail ICMR is designed.
ˆ The high resolution and small delay specifications demand a
high speed & high gain comparator topology, as shown in Figure
3.2.1. It consists of a pre-amplifier, followed by a latch, followed
by a post-amplifier [2], [3].
LatchPreamp Postamp
Vin
Vref
Vout
Figure 3.2.1: High speed, high gain comparator block diagram
ˆ To satisfy the rail-to-rail ICMR specification, 2 comparators are
designed - one with NMOS input and other with PMOS input.
Both comparators are connected together by keeping a common
post-amplifier stage (explained later).
NMOS input comparator
NMOS input comparator satisfies the resolution and delay specifi-
cations of the overall comparator. Its ICMR is ≈ 0.3V to 1.2V .
The pre-amplifier used is a fully-differential 2-stage amplifier, as
shown in Figure 3.2.2. Since the NMOS transistors used (N 12 HSL130E)
have a VTh of 0.22V , Vin & Vref have to be atleast 0.3V above
ground, otherwise transistor X9 enters triode region and loses its
current mirroring action. For Vin/Vref below 0.22V , X1/X2 would

29. 3.2. Comparator 20
Vdd Vdd Vdd VddVdd
Vgn+
Vgn−
X1 X2
X9X10 X7 X8
X3
X4
X5
X6
Vin Vref
Figure 3.2.2: NMOS input pre-amplifier
go into cutoff and stop conducting, which is even worse. The pre-
amplifier stage thus decides the ICMR of the comparator. This gain
of this stage is low.
The pre-amplifier stage is followed by a latch stage, which is
shown in Figure 3.2.3. The latch stage used is a source coupled
differential amplifier loaded with a latch. The latch uses positive
feedback to quickly reach the desired output. It also provides high
gain.
The post-amplifier stage used is a self-biased differential amplifier
followed by an inverter, as shown in Figure 3.2.4. The self-biased
differential amplifier works in the large signal region. It quickly gen-
erates large amounts of current and enables a full rail-to-rail swing.
The inverter acts as a output driver.
The NMOS input comparator is obtained by putting all the 3
stages together. It is shown in Figure 3.2.5.

30. 3.2. Comparator 21
Vbiasn
X18X15 X17 X16
Vdd
X21
X19 X20
Vgn+
Vgn−
Vlo−
Vlo+
Figure 3.2.3: Latch Stage for NMOS input comparator
X22 X23
X27
X24 X25
X26
Vdd Vdd
Vdd Vdd
Vout
X29
X28
vlo+
vlo−
Figure 3.2.4: Post-amplifier stage

31. 3.2. Comparator 22
VddVddVddVddVddVdd
VddVdd
VddVdd
Vout
VinVref
Figure3.2.5:NMOSinputcomparator.ICMR≈0.3Vto1.2V.

32. 3.2. Comparator 23
PMOS input comparator
The PMOS input comparator satisfies the resolution and delay spec-
ifications of the overall comparator. Its ICMR is ≈ 0V to 0.8V .
Since the PMOS transistors used (P 12 HSL130E) have a VTh of
≈ 0.25V , Vin & Vref have to be below 0.8V , otherwise the current
mirror transistor at the source of the input differential pair enters
triode region and loses its current mirroring action. For Vin/Vref
above 0.95V , one of the PMOS input differential pair transistors
would stop conducting, which, again, is not desirable.
This comparator is created along similar lines as the NMOS input
comparator. The circuit for the former is simply the complimentary
of the circuit for the latter. (Complimentary circuit here means cir-
cuit obtained by replacing NMOS transistors with PMOS transistors
and vice-versa.) It is shown in Figure 3.2.6.
Rail-to-rail ICMR comparator
It can be noted from Figure 3.2.5 and Figure 3.2.6 that the post-
amplifier stage is common for both. This gives a hint on how to
connect the two comparators - use a common post-amplifier stage.
When both the NMOS input and PMOS input comparators are con-
nected together by keeping a common post-amplifier stage, we get
a comparator which satisfies the desired rail-to-rail ICMR specifica-
tion. The complete circuit is shown in Figure 3.2.7.

33. 3.2. Comparator 24
VddVdd
VddVdd
Vout
VddVdd
VddVdd
VddVddVdd
VddVdd
VinVref
Figure3.2.6:PMOSinputcomparator.ICMR≈0Vto0.8V.

34. 3.2. Comparator 25
VddVddVddVddVddVdd
VddVdd
VddVdd
Vout
VddVdd
VddVdd
VddVddVdd
VddVdd
VinVref
VinVref
Figure3.2.7:Comparatorwithrail-to-railICMR

35. 3.2. Comparator 26
3.2.2 Simulation Results
For interpreting the simulation results given ahead, refer to the com-
parator symbol, shown in Figure 3.2.8.
Vref
Vin
Vout
Cmp
Figure 3.2.8: Comparator Symbol
DC
Figures 3.2.9(a), 3.2.9(b), 3.2.9(c) & 3.2.9(d) demonstrate the DC
characteristics of comparator for various reference signal values. From
the figures the following can be noted -
ˆ The output signal, Vout, rises very sharply around the refer-
ence signal, Vref . This shows that the comparator has a high
resolution.
ˆ Figures 3.2.9(c) & 3.2.9(d) show that the comparator works as
expected even when the reference signal, Vref , is close to either
ground or power rails. This demonstrates that the comparator
has rail-to-rail ICMR.
Transient
A comparator has the slowest transient response when one of its two
inputs, say Vin, varies as closely as possible around its other input,
Vref (unless the comparator is slewing) [2]. “As close as possible
”here means within 1 LSB.

36. 3.2. Comparator 27
0.00.20.40.60.81.01.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vin(V)
Vref=VDD/2=600mV
Vin(V)
Vout(V)
(a)
0.00.20.40.60.81.01.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2Vin(V)
Vout(V)
Vin(V)
Vref=800mV
(b)
0.00.20.40.60.81.01.2
Vin(V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vref=1LSB=2.34mV
Vin(V)
Vout(V)
(c)
0.00.20.40.60.81.01.2
Vin(V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vref=VDD-1LSB=1197.66mV
Vin(V)
Vout(V)
(d)
Figure3.2.9:ComparatorDCcharacteristics

37. 3.2. Comparator 28
Figures 3.2.10(a), 3.2.10(b), 3.2.10(c) & 3.2.10(d) demonstrate
the transient characteristics of comparator for the slowest case for
various reference signal values.
The mathematical equation for signal Vin in sub-figures of Figure
3.2.10 is:
Vin =
Vref − 1LSB if t < 1ns or t > 2.5ns
Vref + 1LSB if t > 1ns or t < 2.5ns
It can be noted from the sub-figures in Figure 3.2.10 and that
even the slowest response of the comparator is within 500ps. And
this is true for all the cases of reference voltages, even when it is
close to either ground or power rails (which again demonstrates the
rail-to-rail ICMR property of the comparator).
Frequency
Frequency analysis of the comparator is not required since it is op-
erated in open-loop mode. As there is no feedback, there is no
question of instability. The DC and transient simulations suffice to
characterize the behaviour of the comparator.

38. 3.2. Comparator 29
0.00.51.01.52.02.53.03.54.0
Time(ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vref=VDD/2=600mV
1
0.5977
0.6023
2.5
0.6023
0.5977
Vin(V)
Vout(V)
(a)
0.00.51.01.52.02.53.03.54.0
Time(ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vref=800mV
1
0.7977
0.8023
2.5
0.8023
0.7977
Vin(V)
Vout(V)
(b)
0.00.51.01.52.02.53.03.54.0
Time(ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1
0.0000
0.0047
2.5
0.0047
0.0000
Vin(V)
Vout(V)
Vref=1LSB=2.34mV
(c)
0.00.51.01.52.02.53.03.54.0
Time(ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vref=VDD-1LSB=1197.66mV
1
1.1540
1.2000
2.5
1.2000
1.1540
Vin(V)
Vout(V)
(d)
Figure3.2.10:Comparatortransientcharacteristics.Forclarity,theinsetsshowamagnifiedviewofVinsignal.

39. 3.3. DAC 30
3.3 DAC
3.3.1 Design
2-bit, 3-bit, 4-bit, 5-bit, 6-bit, 7-bit and 8-bit DACs are
designed with settling time < 2.9ns, output swing of 0.3V
- 0.9V.
The topology chosen is current-steering, as shown in Figure 3.3.1.
The current steering part generates current in powers of 2, times the
least current, ILSB. According to the digital inputs (either Vdd or
ground) at the switches b1, b2, ..., b8, the generated current is either
passed around the opamp or into the ground. The current which
flows around the opamp through its feedback path is converted into
appropriate voltage by the feedback resistor. This voltage is the
required analog equivalent of the digital input given at the switches.
. . . . . .
b0
2ILSB
0
Vout
. . . .
2ILSB
1
2ILSB
n−2
2ILSB
n−1
b1 bn−2 bn−1
+−
0.3V
Figure 3.3.1: n-bit current steering DAC topology
The input to the switches is guaranteed to be digital in nature,
since it comes from the outputs of the flip flops, as mentioned in
Section 2.1. This is the reason charge leakage is not tolerated in D
flip flops and they are designed with full rail-to-rail output swing,
as mentioned in Section 3.1.1
The opamp used is a 2-stage PMOS input differential amplifier

40. 3.3. DAC 31
+−
0.3V
Vdd
Current
VddVdd
from
switches
Vdd Vdd
Vin Vref
R
Vout
Figure 3.3.2: 2-stage differential opamp with feedback
with a current mirror (active) load, as shown in Figure 3.3.2. One
of the inputs is held at 0.3V always, since the required output swing
is from 0.3V to 0.9V. Assuming that the opamp is nearly ideal, the
output signall Vout, in volts, is given as
Vout = 0.3 + I.R (3.3.1)
where I is current from the switches (current steering part) and R
is the value of the feedback resistor. I and R are chosen accordingly
to get the required output swing from 0.3V to 0.9V.
The current steering part is designed using cascode current mir-
rors alongwith transmission gates as the switches, as shown in Figure
3.3.3. Cascode current mirrors are chosen since they provide very
good current matching, almost independent of their overdrive volt-
age (Vds), as long as they are in saturation. Recall, from Section
2.1, that the LSBs of the DACs are always high (logic 1) for the
SAP ADC. Hence the switch b0 (transmission gate) is absent for the

41. 3.3. DAC 32
Vdd
VddVdd
Vdd
VddVdd
Vdd
+−
Vref=0.3V
Toopamp(Vin)
bn-1b1
20 ILSB
21 ILSB
2n-1 ILSB
Figure3.3.3:Currentsteeringcircuitforn-bitDAC

42. 3.3. DAC 33
branch supplying the ILSB current in Figure 3.3.3.
3.3.2 Simulation Results
Frequency
Figure 3.3.4(a) shows the frequency response (both magnitude and
phase) of the opamp in open loop. Figure 3.3.4(b) shows the same
of the opamp in closed loop.
DC
Figures 3.3.5, 3.3.6 and 3.3.7 show the DC characteristics of 2-bit,
3-bit, 4-bit, 5-bit, 6-bit, 7-bit and 8-bit DACs respectively. Both
ideal and actual plots are shown. In the regions where only one of
them can be seen, the matching is almost perfect (as the other plot
overlaps with it).
Transient
The speed of the DAC is determined by the speed of the opamp.
The output of the opamp takes significant time to settle due to the
feedback nature. The current steering circuit has negligible delay
as compared to the opamp. The opamp reacts the slowest when
the input current step is the largest. The largest input current step
comes when the MSB switches 1
, which accounts for half of the total
maximum current. Figure 3.3.8(a) shows the transient response for
this worst case delay scenario. Figures 3.3.8(b), 3.3.8(c) and 3.3.8(d)
demonstrate the transient response of other cases with smaller input
current step size.
1
Here, it is assumed the input signal given to the SAP ADC is a slowly varying signal (i.e.
it is assumed to not change significantly between 2 consecutive sampling clock cycles). So it is
assumed that when the MSB switches, no other current branch switches simultaneously. Two
or more smaller current branches may switch simultaneously, as long as the total current being
switched is less than half the maximum current. This is a reasonable assumption.

43. 3.3. DAC 34
12345678910
Frequency(logscale,Hz)
10
0
10
20
30
40
50
60
Gain(magnitude,dB)
12345678910
Frequency(logscale,Hz)
180
160
140
120
100
80
60
40
20
0
Gain(phase,deg)
(a)Openloopresponse
12345678910
Frequency(logscale,Hz)
10
0
10
20
30
40
50
60
Gain(magnitude,dB)
12345678910
Frequency(logscale,Hz)
180
160
140
120
100
80
60
40
20
0
Gain(phase,deg)
(b)Closedloopresponse
Figure3.3.4:Frequencyresponsesofopampinopen&closedloop

44. 3.3. DAC 35
01234
DigitalInput(0to4)
0.30
0.45
0.60
0.75
0.90
2bitDACoutput(V)
Idealoutput
Actualoutput
(a)2-bitDACDCcharacteristics
012345678
DigitalInput(0to8)
0.300
0.375
0.450
0.525
0.600
0.675
0.750
0.825
0.900
3bitDACoutput(V)
Idealoutput
Actualoutput
(b)3-bitDACDCcharacteristics
012345678910111213141516
DigitalInput(0to16)
0.3000
0.3375
0.3750
0.4125
0.4500
0.4875
0.5250
0.5625
0.6000
0.6375
0.6750
0.7125
0.7500
0.7875
0.8250
0.8625
0.9000
4bitDACoutput(V)
Idealoutput
Actualoutput
(c)4-bitDACDCcharacteristics
02468101214161820222426283032
DigitalInput(0to32)
0.3000
0.3375
0.3750
0.4125
0.4500
0.4875
0.5250
0.5625
0.6000
0.6375
0.6750
0.7125
0.7500
0.7875
0.8250
0.8625
0.9000
5bitDACoutput(V)
Idealoutput
Actualoutput
(d)5-bitDACDCcharacteristics
Figure3.3.5

45. 3.3. DAC 36
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
Digital Input (0 to 64)
0.3000
0.3375
0.3750
0.4125
0.4500
0.4875
0.5250
0.5625
0.6000
0.6375
0.6750
0.7125
0.7500
0.7875
0.8250
0.8625
0.9000
6bitDACoutput(V) Ideal output
Actual output
(a) 6-bit DAC DC characteristics
0 8 16 24 32 40 48 56 64 72 80 88 96 104112120128
Digital Input (0 to 128)
0.3000
0.3375
0.3750
0.4125
0.4500
0.4875
0.5250
0.5625
0.6000
0.6375
0.6750
0.7125
0.7500
0.7875
0.8250
0.8625
0.9000
7bitDACoutput(V)
Ideal output
Actual output
(b) 7-bit DAC DC characteristics
Figure 3.3.6

46. 3.3. DAC 37
Figure3.3.7:8-bitDACDCcharacteristics.Forclarity,theinsetsshowsamagnifiedviewoftheidealandactualDACoutputs.

47. 3.3. DAC 38
0123456789101112131415
Time(ns)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
DACOutput(V)
Inputstep=30.72µA(WorstCase)
(a)
0123456789101112131415
Time(ns)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
DACOutput(V)
Inputstep=15.36µA
(b)
0123456789101112131415
Time(ns)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
DACOutput(V)
Inputstep=7.68µA
(c)
0123456789101112131415
Time(ns)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
DACOutput(V)
Inputstep=3.84µA
(d)
Figure3.3.8:DACtransientcharacteristics

48. 39
Chapter 4
Successive Approximation
Pipelined ADC Simulation
Results
After all the designed components are tested individually, they are
integrated together to create the SAP ADC. An ideal sample & hold
circuit is used.
4.1 Specifications
ˆ Technology: UMC 130nm
ˆ Supply voltage: 0V - 1.2V
ˆ Resolution 8-bit
ˆ Input voltage range: 0.3V - 0.9V
4.2 Testbench
The SAP ADC was tested by creating a standard testbench, as
shown in Figure 4.2.1. The input signal, Vin is assumed to vary
slowly, i.e. Vin is assumed to not change by a large amount between

49. 4.3. Simulation Results 40
2 consecutive clock cycles of the sampling clock. This is a reasonable
assumption.
b7
b6
b5
b4
b3
b2
b1
b0
SAP
ADC
Vi n CLK
DigitalOutput
b0
b1
b2
b3
b4
b5
b6
b7
Ideal8bitDAC
Vdd
Vout
Figure 4.2.1: The SAP ADC testbench
4.3 Simulation Results
After integration of all the components together, the SAP
ADC works as expected. This demonstrates that this new
SAP ADC architecture is a valid ADC architecture.
An example of output waveform generated by the SAP ADC for
a sinusoidal input is shown in Figure 4.3.1. It can be noted that
the output waveform lags the input waveform by 8 clock cycles, as
expected for an architecture with 8-stage pipeline.
4.4 Corner Analysis
All the components were designed to match the required specifica-
tions for the “tt” corner of UMC 130nm technology. For this corner,
the maximum achievable sampling frequency was 285 MHz, with

50. 4.4. Corner Analysis 41
050100150200250300350400
Time(ns)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
CLK,Vin(V)
CLK
Vin
050100150200250300350400
Time(ns)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
CLK,Vout(V)
CLK
Vout
Figure4.3.1:ExampleofoutputwaveformgeneratedbySAPADCforasinusoidalinput.

51. 4.5. Remarks 42
an offset error ≈ 0.
For the worst corner, the “ss” corner, the maximum achievable
frequency was 180 MHz, but with a large offset error of ≈ 36 LSB.
4.5 Remarks
ˆ The designed D flip flop and comparator work well for all cor-
ners.
ˆ The designed DAC is a bottleneck in the overall performance
of the SAP ADC.
– A faster DAC will increase the maximum sampling fre-
quency of the SAP ADC.
– DAC has offset errors for the slower corners, resulting in
offset errors of the overall ADC. A DAC with high linearity
can help overcome this problem.

52. 43
Chapter 5
Conclusions
The design of a new architecture based on successive approximation
algorithm is discussed in detail (Chapter 2). Its potential for running
at very high sampling speeds is explored. A 8-bit SAP ADC is
designed to verify the validity of this architecture (Chapter 4). A
maximum sampling speed of 285 MHz is achieved for the “tt”corner
of UMC 130nm technology. This is just the beginning and further
improvement is possible. Further directions for exploiting the full
capability of this new architecture to achieve 1GS/s sampling rate
are given (Chapter 6).

53. 44
Chapter 6
Future Work
A working SAP ADC has been designed. A lot of work still needs
to be done to convert this into a working chip. An ordered list of
future work to be done is given in the following sections.
6.1 Schematic Work
ˆ Improving DAC performance: It is concluded in Section 4.5
that the DAC performance limits the performance of the overall
ADC. Therefore, the existing DAC needs to be improved. The
DAC gain should be improved to overcome non-linearity errors.
The DAC should also be made faster to increase the maximum
sampling speed. A maximum sampling speed of 1GS/s can
be achieved if a DAC with a settling time of < 500ps can be
designed. This target is not very difficult to achieve.
ˆ Design of the Sample & Hold circuit: For my SAP ADC sim-
ulations (Section 4.3), an ideal sample & hold circuit is used.
The actual circuit needs to be designed.
ˆ Noise Analysis: This is not yet done. This cannot be ignored.
ˆ Power optimization: The components can be improved/redesigned

54. 6.2. Layout Work 45
for optimal use of power, if required.
ˆ Corner Analysis: All the simulations done so far and those men-
tioned above should work well for all the corners. Some circuit
components would need redesigning to fit the slower corners.
ˆ Monte Carlo simulations: This is required to simulate the effect
of transistor parameters mismatch on the overall performance
of SAP ADC. Some components might require redesigning.
6.2 Layout Work
ˆ Layout: This is a big task.
ˆ Post layout analysis (PEX, etc.): The functionality of the layout
matches that of the schematic needs to be verified.
6.3 Post Tapeout Work
ˆ Testing
ˆ Characterization: INL, DNL, SNR, SNDR, SNFR, THD, SINAD,
ENOB, etc.

55. Appendices
46

56. Appendix A
Optimization
One often faces the problem of finding the correct transistor sizing
for a given circuit topology. The circuit analyses equations given in
circuit-design books are very useful for rough calculations. However,
at times, they are of not much use quantitatively. This is because
calculations in books are based on simplistic transistors models for
mathematical ease of hand calculations. Practical transistors be-
have far different from these ideal equations, and hence the textbook
analyses equations may not always help. For example, if a current
mirror is to be designed with, say exact1
2:1 current matching, text-
book equations would state using the mirroring transistors with 2:1
sizing ratio. Practically this equation would never give the exact
current matching. Another such example, where textbook formulae
are not useful, would be nulling the offset of a comparator within a
high accuracy.
For such problems, it is important to use some form of optimiza-
tion algorithm which would automatically find the correct sizing for
a given circuit which would give the desired functionality. This field
of optimization is a separate branch in itself and cannot be explained
here. Figure A.0.1 shows the flowchart of an optimization procedure
1
exact matching here means matching upto a very high accuracy
47

57. 48
I have used to optimize transistor sizings for various circuits while
designing the SAP ADC components. The optimization algorithm
used was based on differential evolution optimization (see Appendix
B).
Create controller script
with variable ranges
and cost function
Create netlist with
random values
for variables
Simulate using
circuit simulator
Create netlist from
template with the
new parameter
values
Generate new values
for variable from the
past history
(using optimization algorithm)
Read output &
calculate cost
function value
Is cost
function value
desirable?
Create netlist
template
Done
YES
NO
Figure A.0.1: Circuit optimization flowchart

58. Appendix B
Softwares
List of softwares used for circuit designing and circuit optimization:
ˆ Circuit simulator: ngspice
http://ngspice.sourceforge.net/
ˆ Optimization algorithm: Python script
http://www.h-renrew.de/h/python_spice/optimisation.html
ˆ Controller: Python script
This has to be made as per requirement.
Some examples are available here:
http://www.h-renrew.de/h/python_spice/optimisation.html
Only open source softwares have been used for circuit
simulation and optimization!
49

59. References
[1] Borivoje Nikolic Jan M. Rabaey, Anantha Chandrakasan. Digital
Integrated Circuits - A Design Perspective. Prentice Hall India,
2011.
[2] Douglas R. Holberg Phillip E. Allen. CMOS Analog circuit De-
sign. Oxford University Press, 2002.
[3] Kenneth W. Martin Tony Chan Carusone, David A. Johns. Ana-
log Integrated Circuit Design. John Wiley & Sons, Inc., 2012.
50