It contains carbon nano tube based field effect transistor.

1. CNTFET for memory design
Presented by:-
Abisha Angral (23204101)
Mayank Pratap (23204111)
Rishabh Kapoor (23204118)
Submitted to:-
Dr. Balwinder Raj
Assistant Professor
NIT Jalandhar

2. Contents
• Motivation
• Introduction to CNTFET
• Classification of CNTFET on the basis of structure
• Working of CNTFET
• CNTFET for memory design
• SRAM using CNTFET
• Read and Write delay in SRAM cells
• Static noise margin of SRAM
• Power Consumption in SRAM
• Conclusion
• References

3. Motivation
• In recent research, some challenges like short channel effect, higher
power consumption, and low switching speed occur due to
submicron scaling of conventional CMOS and thus degrading the
performance of the circuit.
• In order to overcome these issues, Carbon nanotube field-effect
transistors (CNTFET) are considered to be one of the suitable
alternatives of conventional CMOS technology.
• The major advantage of considering CNTFET is due to low power,
high mobility, and high carrier velocity for faster switching over
CMOS technology.

4. Introduction to CNTFET
• A Carbon Nanotube Field Effect Transistor (CNTFET) refers to a FET that utilizes a
single Carbon Nanotube or an array of CNTs as the channel material instead of
bulk silicon in the traditional MOSFET structure. The core of a CNTFET is a carbon
nanotube.
• A carbon nanotube (CNT) is a graphene sheet (with carbon atoms appearing in
a hexagonal pattern) rolled up to form a hollow cylinder.
Single-wall Carbon nanotube Multi-wall Carbon nanotube

5. Introduction to CNTFET (contd.)
• In the generic CNTFET which could be single wall (SWCNTs) or multi wall (MWCNTs), a
carbon nanotube is placed between two electrodes while a separate gate electrode
controls the flow of current in the channel.
• The physical structure of CNTFETs is very similar to that of MOSFETs and their I-V
characteristics and transfer characteristics are also very promising and they suggest
that CNTFETs have the potential to be a successful replacement of MOSFETs in
nanoscale electronics.
• CNTs have extremely low electrical resistance because electrons can travel for large
distances without scattering (ballistic transport). This is partly due to their very small
diameter and huge ratio of length to diameter. Also, because of their low resistance,
CNTs dissipate very little energy.

6. Classification of CNTFET on the basis
of structure
❑ Back gate CNTFET
The earliest techniques for fabricating carbon nanotube (CNT) field-effect transistors
involved pre-patterning parallel strips of metal across a silicon dioxide substrate, and
then depositing the CNTs on top in a random pattern.
One metal strip is the “source” contact while the other is the “drain” contact. The silicon
oxide substrate can be used as the gate oxide and adding a metal contact on the back
makes the semiconducting CNT gateable.
Back gated CNTFET

7. Structure of Top-Gated CNTFET
❑Top gate CNTFET
• The "top gate" in the name refers to the gate electrode's
position on top of the carbon nanotube channel.
• The gate electrode is a metal layer (e.g., aluminum or
another suitable conductor) deposited on top of the gate
insulator. The gate electrode is used to control the flow of
electrons through the carbon nanotube channel.
• By applying a voltage to the gate electrode, the electrical
properties of the carbon nanotube can be modified,
allowing for the transistor to be turned on or off.
• Better architecture of the top gate CNTFET than back gate
CNTFET gave us better subthreshold slope, higher
transconductance, and negligible hysteresis in terms of
threshold voltage shift.
Classification of CNTFET on the basis
of structure (contd.)

8. Working of CNTFET
The working of a Carbon Nanotube Field-Effect Transistor (CNTFET) is similar to that of a
traditional Field-Effect Transistor (FET). In a CNTFET, a carbon nanotube serves as the channel
through which electrical current flows, and the flow of current is controlled by the application
of a gate voltage. Here's how a CNTFET typically operates:
1. Initialization: The CNTFET starts in an off-state. This means that, by default, there is no electrical
current flowing between the source and drain electrodes.
2. Gate Voltage Application: To turn the CNTFET on or off, a gate voltage is applied to the gate
electrode, which is located on top of the carbon nanotube channel.
3. Controlling the Conductance: The gate voltage creates an electric field in the vicinity of the
carbon nanotube. This field influences the electrical conductance of the carbon nanotube
channel. The exact effect depends on whether the nanotube is a metallic or semiconducting
nanotube.
- For Metallic CNTs: Applying a positive gate voltage decreases the conductance, turning
the CNTFET off. Conversely, applying a negative gate voltage increases the conductance,
turning the CNTFET on.

9. Working of CNTFET
- For Semiconducting CNTs: The conductance of a semiconducting CNT depends on
the polarity of the gate voltage. A positive gate voltage (gate-source voltage, Vgs) turns
the CNTFET on, while a negative Vgs turns it off. This is due to the bandgap nature of
semiconducting CNTs, where the bandgap can be modulated by the gate voltage.
4. Source-Drain Current Control: When the CNTFET is turned on (by the appropriate gate
voltage), an electrical current can flow from the source electrode to the drain electrode
through the carbon nanotube channel.
5. Turn-off State: To turn the CNTFET off, the gate voltage is adjusted accordingly, which
reduces or completely inhibits the flow of current through the carbon nanotube channel.

10. SRAM using CNTFET
• First CNTFET based SRAM was demonstrated in
2001. Because of good electrical and
mechanical properties of CNTFET, SRAM gives
better performance. CNTFET based SRAM gives
most promising characteristics but because of
drawbacks of CNTFET for its bulk fabrication
currently it’s an area of interest of researchers.
• With the aggressive scaling in CMOS technology,
at ultra-low power supply ,the use of 6T SRAM cell
leads to numerous critical problems like poor
stability, high power consumption etc. In this
case CNTFETs could be a good alternative with
high stability and high density for high density
memories.
CNTFETs based 6T- SRAM
BISTABLE MULTIVIBRATOR
BISTABLE

11. SRAM using CNTFET (contd.)
• During the SRAM operations, three different stable
states can see: Standby state (idle condition),
Read state (requesting data) and write state
(updating content).
❑ Hold operation:
There is no hold operation considered in the memory
cell, WL is not connected to Vdd. Due to this, driver
transistors (M5, M6) do not remain in connection with
the circuit and those transistors formed cross coupled
design are present internal circuitry holds the stored
value if it is connected by power supply.
Both of bit lines (BL and BLB) are not already charged
by column pre-charged circuit .

12. SRAM using CNTFET (contd.)
❑ Read operation:
The read operation in a 6T SRAM cell involves
activating the wordline, enabling one of the access
transistors to connect the storage node to a bitline,
detecting the voltage change on the bitline with a
sense amplifier, and providing the output data for
external circuitry.
This read operation is fast and non-destructive,
allowing the SRAM cell to maintain its data as long
as power is supplied.
Read ‘1’ Operation

13. SRAM using CNTFET (contd.)
❑ Write operation:
The write operation in a 6T SRAM cell involves activating
the wordline, propagating the desired data value from
the bitline to the storage nodes, and storing the data in
the cross-coupled inverters. Once the operation is
complete, the wordline is deactivated, and the data
remains stable in the SRAM cell as long as power is
maintained.

14. CNTFET for memory design
Carbon Nanotube Field-Effect Transistors (CNTFETs) have garnered significant interest for memory
applications due to their unique properties, such as high carrier mobility, low power consumption,
and potential scalability to extremely small dimensions. Here are a few memory design concepts
where CNTFETs may be applied:
1. Static Random-Access Memory (SRAM):
- CNTFETs can be used in SRAM cells to create high-speed, low-power, and high-density memory.
SRAM cells store data as long as power is applied and are used as cache memory in processors.
- CNTFETs' fast switching speeds and low leakage current make them suitable for SRAM
applications where high performance is crucial.
2. Dynamic Random-Access Memory (DRAM) :
- CNTFETs have the potential to create more energy-efficient DRAM cells due to their low power
consumption characteristics. DRAM is used in main memory in computers.
- The high electron mobility of CNTs can lead to faster refresh rates and improved data retention.
3. Non-Volatile Memory:
- CNTFETs can enable low-power, high-speed, and high-density non-volatile memory.

15. CNTFET for memory design (contd.)
4. Flash Memory:
- Flash memory, commonly used in USB drives and SSDs, can benefit from CNTFETs in
terms of read/write speed and power consumption.
- The fast switching of CNTFETs may lead to quicker programming and erasing of flash
memory cells.
5. 3D Memory Stacking:
- CNTFETs can be integrated into three-dimensional memory designs, where multiple
memory layers are stacked on top of each other.
- The small size of CNTFETs makes them suitable for densely packed 3D memory
structures.

16. Static noise margin of SRAM
Noise margin is a crucial parameter in digital circuit design, including SRAM (Static Random-Access
Memory) cells. It represents the tolerance of a digital circuit to variations in input voltage levels and
noise on the power supply or signal lines
There are two main types of noise margins in SRAM cells:
1. Read Noise Margin (RNM):
- Read Noise Margin measures the tolerance of an SRAM cell to variations in the data read from
it. It ensures that even if there's some noise on the bitlines, the cell can still correctly determine the
stored data.
- RNM is usually defined as the voltage difference between the voltage level on the true (Q) and
complementary (Q-bar) bitlines that still results in the correct output from the SRAM cell.
- A higher RNM indicates greater noise tolerance during read operations.
2. Write Noise Margin (WNM):
- Write Noise Margin assesses the cell's ability to accept data during a write operation correctly. It
accounts for the potential variation in the write operation voltage levels.
- WNM is defined as the minimum difference between the voltage levels on the wordline and the
bitline necessary to correctly write a '0' or '1' into the cell.
- A larger WNM indicates a more robust SRAM cell for write operations.

17. Read and Write delay in SRAM cells
• The value of time taken to read data from SRAM
cell is called read delay. When cell hold a data of
logic ‘0’ then the time taken to read that logic ‘0’
state by access transistors is called Read delay for
reading logic ‘0’.
• The value of time taken to write data in SRAM cell
is called write delay. Write delay is more when
compared to read delay.
• The value of read delay and write delay are
1.22ns and 2.7ns for CMOS SRAM cell and 4.72ps
and 7.21ps for CNTFET 6T SRAM cell respectively at
0.9V.

18. Power Consumption in SRAM
It can be estimated from static power consumption
value of 0.01127nW for CNTFET based SRAM cell
and 0.3522nW for CMOS based 6T SRAM cell i.e.
CNTFET consumes much less standby power than
CMOS.
The reason behind is very small amount of leakage
current passes through CNTFET SRAM cell. From this,
it can be proved that SRAM cell is designed for low
power applications are possible

19. CONCLUSION
• CNTFET gives better device characteristics than MOSFET in terms of high
ON current, low leakage current.
• At fixed value of reference current higher stability giving lower power
consumption.
• Because of top gate structure Standard CNTFET gives better result. The
stability or SNM of the CNTFET SRAM cell are about 27.55% higher than
the CMOS 6T cell.
• Write ability on the CNTFET SRAM cell is comparably higher than CMOS
based SRAM cells. The CNTFET SRAM cells show a 37.44% improvement in
the power consumption and at least 13% reduction in the delays.
• Therefore, CNTFET SRAM cell is desirable for low power with a
considerable margin.

20. References
1. Srinivasu, B., & Sridharan, K. (2021). Low-Power and High-Performance Ternary SRAM designs with
application to CNTFET technology. IEEE Transactions on Nanotechnology, 20, 562–566.
https://doi.org/10.1109/tnano.2021.3096123
2. Shrivastava, A., Damahe, P., Kumbhare, V. R., & Majumder, M. K. (2019). Designing SRAM Using CMOS and
CNTFET at 32 nm Technology. IEEE Xplore. https://doi.org/10.1109/ises47678.2019.00070
3. Syed, H., Khanday, F. A., Zahoor, F., & Hussin, F. A. (2021). Performance Analysis of CNTFET-ReRAM based
Crossbar Network for In-Memory Computing. IEEE Xplore. https://doi.org/10.1109/rteict52294.2021.9573900
4. Devi, M. P., Madhu, C., Garg, N., Singh, S., & Singh, P. (2021). Design and Stability analysis of CNTFET based
SRAM cell. IOP Conference Series, 1033(1), 012043. https://doi.org/10.1088/1757-899x/1033/1/012043
5. Kumar, H., Srivastava, S., & Singh, B. (2021). Low power, high-performance reversible logic enabled CNTFET
SRAM cell with improved stability. Materials Today: Proceedings, 42, 1617–1623.
https://doi.org/10.1016/j.matpr.2020.06.475
6. Elangovan, M., Abbasian, E., Gunasegeran, M., & Sofimowloodi, S. (2022). Design of high stability, low power
and high speed 12 T SRAM cell in 32-nm CNTFET technology. AEU - International Journal of Electronics and
Communications, 154, 154308. https://doi.org/10.1016/j.aeue.2022.154308