40120140502003

International Journal of Electronics and JOURNALEngineering & Technology (IJECET), ISSN 0976 –
INTERNATIONAL Communication OF ELECTRONICS AND
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 2, February (2014), pp. 21-29 © IAEME

COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 2, February (2014), pp. 21-29
© IAEME: www.iaeme.com/ijecet.asp
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IJECET
©IAEME

GENERATION OF CRYPTOGRAPHICALLY SECURED PSEUDO RANDOM
NUMBERS USING FPGA
Thottempudi Pardhu(1), Thottempudi Naga Teja(2),

K.N.Bhushan(3),

N.Usha Rani(4)

1

Dept of E.C.E, Marri Laxman Reddy Institute of Technology & Management, Hyderabad, India
2
Dept of E.C.E, Vignan University, Vadlamudi, Guntur (Dist), Andhrapradesh, India
3
Dept of E.C.E, Marri Laxman Reddy Institute of Technology & Management, Hyderabad, India
4
Dept of E.C.E, Vignan University, Vadlamudi, Guntur (Dist), Andhrapradesh, India

ABSTRACT
Random numbers are used for many purposes like generating data encryption keys,
simulating and modeling complex phenomena and for selecting samples randomly from larger
datasets. They can also used in literature, music and popular for games and gambling. While
discussing about single numbers, a random number is one that is drawn from a set of possible values,
each of which is equally probable, i.e. uniform distribution. When we are discussing a sequence of
random numbers the number drawn must be statistically independent of the others. There are various
methods for the generation of Random numbers. There are two types of Random number generators
they are Pseudo random number Generator (PRNG) and True Random Number Generator (TRNG).
Numbers generated from True Random Number generator will not repeat and are Cryptographically
Secured. These are also known as cryptographically secured Pseudo random Numbers (CSPRNG).
The sources of Randomness in TRNG are physical phenomena like Lightning, Radio Active Decay,
and Thermal Noise etc. In this paper generation of Cryptographically Secured Pseudo Random
Numbers using Blum Blum Shub Generator is explained. It was implemented on Virtex-V FPGA
using VHDL Programming Language and the Simulation was done on XILINX ISE 12.4i.
Key words: CSPRNG, PRNG, Random Numbers, TRNG, XILINX.
1. INTRODUCTION
A random number generator (RNG) is a device designed to generate a sequence of numbers
or symbols that don‘t have any pattern. Hardware-based systems for random number generation are
widely used, but often fall short of this goal, albeit they may meet some of the statistical tests for
randomness for ensuring that they do not have any ―de-cod able‖ patterns. Methods for generating
21

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –

random results have existed since ancient times, including dice, coin flipping, the shuffling of
playing cards, the use of yarrow stalks and many other techniques. [2], [3].
The many applications of randomness have led to many different methods for generating
random data. These methods may vary as to how unpredictable or random they are, and how quickly
they can generate random numbers. [2], [3].
There are two principal methods used to generate random numbers. One measures some
physical phenomenon that is expected to be random and then compensates for possible biases in the
measurement process. The other uses mathematical algorithms that produce long sequences of
apparently random numbers, which are in fact completely determined by an initial value, known as a
seed. The former one is known as True Random Number Generator (TRNG). [2]
In comparison with PRNGs, TRNGs extract randomness from physical phenomena and
introduce it into a computer. One can imagine this as a die connected to a computer. The physical
phenomenon can be very simple, like the little variations in mouse movements or in the amount of
time between keystrokes. In practice, however, one has to be careful about which source one
chooses. For example, it can be tricky to use keystrokes in this fashion, because keystrokes are often
buffered by the computer's operating system, meaning that several keystrokes are collected before
they are sent to the program. To a program waiting for the keystrokes, it will seem as though the
keys were pressed almost simultaneously, and there may not be a lot of randomness there after all.
[4]
However, there are many other methods to get true randomness into your computer. A really
good physical phenomenon to use is a radioactive source. The points in time at which a radioactive
source decays are completely unpredictable, and they can easily be detected and fed into a computer,
avoiding any buffering mechanisms in the operating system. The HotBits service at Fourmilab in
Switzerland is an excellent example of a random number generator that uses this technique. Another
suitable physical phenomenon is atmospheric noise, which is quite easy to pick up with a normal
radio. This is the approach used by RANDOM.ORG. we could also use background noise from an
office or disco, but you'll have to watch out for patterns. The fan from the computer can contribute to
the noise, and since the fan is a rotating device, chances are the noise it produces won't be as random
as atmospheric noise. [4]
Undoubtedly one of the effective approaches was the lavarand generator, which was built by
Silicon Graphics and used snapshots of lava lamps to generate true random numbers. [4]
A pseudorandom number generator (PRNG),is an algorithm for generating a sequence of
numbers that approximates the properties of random numbers. The sequence is not truly random.
Although sequences that are closer to truly random can be generated using hardware random number
generators, pseudorandom numbers are important in practice for simulations (e.g., of physical
systems with the Monte Carlo method), and are important in the practice of cryptography. [5]
A PRNG can be started from an arbitrary starting state using a seed s. It will always produce
the same sequence thereafter when initialized with that state. The maximum length of the sequence
before it begins to repeat is determined by the size of the state. However, since the length of the
maximum period doubles with each bit of 'state' added, it is easy to build PRNGs with periods long
enough for many practical applications. [5]
Most pseudorandom generator algorithms produce sequences which are uniformly distributed
by any of several tests. The security of most cryptographic algorithms and protocols using PRNGs is
based on the assumption that it is infeasible to demarcate use of a suitable PRNG from the usage of a
truly random sequence. The simplest examples of this dependency are stream ciphers, which work by
exclusive or-ing the plaintext of a message with the output of a PRNG, producing cipher text. The
design of cryptographically secure PRNGs is extremely difficult; because they must meet additional
criteria .The size of its period is an important factor in the cryptographic suitability of a PRNG, but
not the only one. [5]
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some of the algorithms generate pseudo random numbers [6]. Blum Blum Shub, Inversive
congruential generator, ISAAC (cipher), Lagged Fibonacci generator, Linear congruential generator,
Linear feedback shift register, Mersenne twister, Multiply-with-carry, Well Equidistributed Longperiod Linear, Xorshift
Cipher algorithms and cryptographic hashes can also be used as pseudorandom number
generators. These include [6] Block ciphers in counter mode, Cryptographic hash function in counter
mode, Stream Ciphers.
The organization of Paper is as follows. Section 1 gives introduction about Random numbers,
Section 2 deals with Generation of Random Numbers using LFSR, section 3 gives information about
generation of Random numbers using improved Tausworthe architecture, Section 4 explains the
project Implementation, Section 5 gives the Results, Section 6 concludes the paper.
2.

GENERATION OF RANDOM NUMBER USING LFSR :

Linear Feedback Shift Register (LFSR) as shown in Fig.1 is used to generate a random
number. LFSR is a shift register whose input bit is a linear function of its previous state. Thus, an
LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits
of the overall shift register value. Any long LFSR counter generates a long pseudo-random sequence
of zeros and ones. The sequence is not exactly random since it repeats eventually, and it also follows
a mathematically predictable sequence. But for most practical purposes it can be considered random.
A 63-bit LFSR counter has a repetition time of (263-1) clock periods. Running at 50 MHz, such a
counter repeats after more than five thousand years (5,849 years to be more precise), which is long
enough to be irrelevant for most practical purposes. Based on the LFSR length different XNOR
feedback taps are required to generate a maximum-length random numbers. The XNOR feedback tap
points to some LFSR are shown in Table. 1
Table.1 : XNOR Tap points
No of bits in
LFSR

Bit positions for
XNOR tap points

3

3,2

4

4,3

5

5,3

6

6,5

7

7,6

8

8,6,5,4

9

9,5

10

10,7

16

16,15,13,4

32

32,22,12,1

64

64,63,61,60

128

128,126,101,99

23


Fig. 1: Random number generation using LFSR
Though LFSR is good for different applications for generating various patterns. Speed and
randomness existed with this pattern is less.
3. GENERATION OF RANDOM NUMBERS USING IMPROVED TAUSWORTHE ARCHI
TECTURE
To improve the randomness and the speed of sequence generation Tausworthe architecture is
used as shown in Figure.2. In this one p-bit long shift register with L -bit output somewhere
between the first and pth bit, and a two-input XOR element feeding the result to1 the first bit
would be required. Such architecture would be slow, because L clock cycles are needed to
update completely the output bit position which is as shown in Fig.2 as show below.
Using this improved architecture, the throughput can be increased to L times of the
conventional LFSR, where L indicates the output bit length.

Fig .2: Improved Tausworthe Generator Architecture

24


In this paper Tausworthe architecture is implemented using Xilinx ise 12.4v using VHDL.
The generated output is compared with the existing Box-Muller algorithm which is described below
for two random variables. Let r1and r2 be the uniform random variables belong to interval[0,1), x1
and x2 be the Gaussian distributed sequence with zero mean and unit variance. Then, the
generated sequences are in the form of Gaussian format, which are described by equation 1.
Gin(i) =ඥെ2݈‫ .1ܴ݃݋‬cos 2Π. ܴ2
Gqd(i) =ඥെ2݈‫ .1ܴ݃݋‬sin 2Π. ܴ2 ………………………………..

(1)

r1and r2 can be generated by the architecture illustrated in figure.2 [7]
4.

IMPLEMENTATION

4.1. Random number Generation
Random numbers can be generated by different methods like Linear Feedback Shift Register
(LFSR), Tausworthe architecture, Boxmuller technique etc. In this paper conventional pseudo
random sequence generation is implemented using conventional LFSR, Tausworthe architecture
and Box-Muller techniques are implemented. For proper sequence generation CORDIC IP core
is included with Tausworthe architecture and simulated. In this work Tauswothe architecture
is implemented in Xilinx ise 12.4 v and validated in chipscope pro. Fig.3 shows the VLSI
implementation of Tausworthe architecture.
HDL code is generated, simulated and synthesized using VHDL. Then .Bit file is generated
.It is dumped into FPGA. By adding .cdc file, code code is verified using Chipscope Pro.
4.2. Blum Blum Shub Generator
The Blum Blum Shub Generator is known to be the cryptographically secure pseudo random
number generator (CSPRNG).
The algorithm for BBS generator is as follows:
•

Select two big prime numbers p and q, such that both the numbers leave a remainder
of 3 when divided by 4.

•

Choose n = p * q

•

Choose seed s, such that s is relatively prime to n which means that neither p nor q is
a factor of s.

•

Xo= s2 mod n

•

The consequent values are generated according to the formula Xi = (Xi1)2mod n

•

A sequence of binary digits is produced according to the formula Bi= Ximod2
The output sequence is B1, B2, B3, B4………..

Now the BBS generator is first implemented in Turbo C++ as it is user friendly and easy to
comprehend.

25


start

HDL program

Synthesis

.bit file generation

Download into FPGA

.cdc file generation

Verification in chipscope

End

Fig 3: VLSI implementation of PRNG using Tausworthe Architecture
5. RESULTS
Implemented VHDL code of random number generation on Virtex-V FPGA.We used CODIC
IP and Chip scope Pro to analyze the design. Fig .4, Fig.5 represent the simulation result of CORDIC
IP,Validation Result of Random Number using ChipScope Pro.

Fig.4 : Simulation result of Random number using CORDIC IP
26


Fig.5: Validation result of Random number using Chipscope Pro
Fig.6, Fig.7 represents the Output of BBS Generator from Turbo C++, Technology Schematic
of BBS Generator.

Fig.6: Out put of BBS Generator from Turbo C++
The first column refers to the values of X generated and second column refers to Bi.

27


Fig.7: Technology Schematic of BBS Gennerator.
6. CONCLUSION
Various codes were written for generators like Pseudo Random Number Sequence Generator,
8 bit random generator using LFSR, 16 bit random generator and BlumBlum Shub generator. But
Blum Blum Shub generator was found to be the most cryptographically secure generator. BBS
generator was implemented in Turbo C++ and VHDL. Initially seed‗s‘ and inputs p, q were taken.
The inputs had to be two large prime numbers and relatively prime to s. Then mod function was
used to calculate the remainder and the square of the same was used as the dividend in the next
recursion. The syntax was found to be correct in case of VHDL but due to some hardware constraints
it could not be implemented in FPGA.
7. REFERENCES
[1]

C.Wei, C.He and H.Y.Qiu, “VLSI implementation of universal rand number generator,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 465-470, 2002.
[2] http://en.wikipedia.org/wiki/Random_number_generation#cite_ref-0.
[3] http://en.wikipedia.org/wiki/Hardware_random_number_generator.
[4] http://www.random.org/randomness/.
[5] http://en.wikipedia.org/wiki/Pseudorandom_number_generator#cite_note-0.
[6] http://en.wikipedia.org/wiki/List_of_random_number_generators.
[7] D.U.Lee, J.D.Villasenor, W.Luk, P.H.W.Leong,” A hardware Gaussion noise generator
using Boxmuller method and its error analysis,” IEEE Trans. Com put., vol. 55, no. 6,
pp. 659-671, Jun. 2006.
[8] Thottempudi Pardhu, Usha Rani Nelakuditi, P.Suresh, “Novel Random Sequence Generation
And Validation Using FPGA”, ICCNASP 2013, V1, PP 295-298.
[9] http://en.wikipedia.org/wiki/Blum_Blum_Shub.
[10] Mala Mitra, “A Random Number Generator for RFID Tags”, International Journal of
Electronics and Communication Engineering & Technology (IJECET), Volume 1, Issue 1,
2010, pp. 71 - 87, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.

28


AUTHOR’S PROFILE
T.Pardhu was born in Luxettipet village in Adilabad District. He completed
B.Tech in MLR Institute of Technology in the stream of Electronics and
Communications Engineering in 2011. He has done his Master’s degree
(M.Tech) in Embedded Systems from Vignan University, Vadlamudi in
2013.He has done Project in Research Centre IMARAT, Hyderabad as
Project Intern. He is Working as Assistant Professor in Marri Laxman
Reddy Institute of Technology & Management. His interested fields are
Digital signal processing, RADAR communications, Embedded systems,
implementation of signal processing on applications in FPGA.

T.Naga Teja was Born in Luxettipet village in Adilabad District. He
completed his B.Tech in Malla Reddy Institute of Technology in the stream
of Electronics and Communication Engineering in 2013. He qualified
GATE-2013. He is Pursuing his Master’s Degree (M.Tech) in VLSI in Vigan
University, Vadlamudi. His interested fields are FPGA implementation of
Signal and Image processing applications, VLSI.

K.N.Bhushan was born in Kancheruvu village in Nellore District. He
completed B.Tech in CMR College of Engineering and Technology in
the stream of Electronics and Communication Engineering in 2006. He
has done his Master’s Degree (M.Tech) in Digital Electronics and
Communication Systems in Jagruthi Institute of Engineering and
Technology, Hyderabad in 2011. He is working as HOD of E.C.E Department
in Marri Laxman Reddy Institute of Technology & Management. His
Interested Fields are Digital Signal Processing, Digital Image Processing,
VLSI.

UshaRani.Neelakuditi completed her B.tech in the stream of Electronics
&Instrumentation in KITS Warangal in 1993. She has done her Masters
Degree (M.Tech) in the Digital Electronics and Communication Systems in
2004 From JNTU Anatapur. She completed Her P.hd on Medical image
Registration of Brain with Tomographs. She is working as HOD of E.C.E
Department in Vignan University, Vadlamudi. Her Interested Fields are
implementation of Signal and image processing applications on FPGA.

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