Performance evaluation of efficient structure for fir decimation filters using polyphase decomposition technique

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 5, May (2015), pp. 01-08© IAEME
1
PERFORMANCE EVALUATION OF EFFICIENT
STRUCTURE FOR FIR DECIMATION FILTERS USING
POLYPHASE DECOMPOSITION TECHNIQUE
Gopal S. Gawande1
, Bhavna R. Pawar2
, Dr. K. B. Khanchandani3
1,2,3
Department of Electronics and Telecommunication Engg., S.S.G.M.C.E. Shegaon, India,
ABSTRACT
Multirate signal processing is an enabling technology that brings DSP techniques to
theapplications requiring low-cost and high sample rates. Multirate filtering technique is widely used
for meeting the sampling rates of different systems. This paper provides implementation and
performance comparison ofvarious structures for Decimators usingPolyphase decomposition
technique.Polyphase decomposition technique reduces the computational complexity and adopts
parallelism. The digital FIR decimator is designed using Filter Design and Analysis (FDA) tool.The
structures are synthesized for Spartan6 Field Programmable Gate Array (FPGA) board using Xilinx
System Generator. The performance indices for comparing implemented structures using FPGA
platform are also proposed in this paper. The proposed efficient polyphase structure consumes
249mWpowers and operates at 121 MHz speed. The efficient structure also yields higher throughput
and computation rate compare to other structures used for decimation.The efficient structure shows
promising results over the other decimators.
Keywords: Decimators, Efficient Polyphase Structure, logic area, Polyphase Decomposition, Power
consumption, Speed
1. INTRODUCTION
In today’s Digital Signal Processing (DSP) applications, sampling rate conversion is a
common operation. In most of these applications, very high quality sample rate converter is required.
The sampling rate of a digital signal can be changed using interpolators and decimators
[2][9][10].Multirate systems can perform a processing task with improved performance
characteristics while simultaneously offering that performance at a significantly lower cost than
traditional approaches. A decimation filter is one of the fundamental building blocks of a multirate
INTERNATIONAL JOURNAL OF ELECTRONICS AND
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 6, Issue 5, May (2015), pp. 01-08
© IAEME: http://www.iaeme.com/IJECET.asp
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system when down sampling is employed. The accurate design of a decimation filter is of prime
importance because it governs the attenuation of unwanted aliasing. Multirate system in which a
digital interpolation filter is employed there is a need to reduce imaging by up sampling [4].
Interpolation and decimation (sampling rate conversions) can be performed efficiently by using
polyphase interpolator and decimator structures. Such structures are obtained from the polyphase
representation of the transfer function of the interpolation or decimation filter [1]. In this paper,
decimation structures are implemented and evaluated.
Decimation reduces the sampling rate at the output of a system so that another system with a
lower sampling rate can receive this signal as input. A narrow filter followed by a down sampler is
referred to as a decimator. Decimator can reduce the sampling rate up to the limit called the Nyquist
rate, according to which the sampling rate must be higher than the highest frequency component
present in the input signal to avoid aliasing. Reduction in sampling rate results in a cheaper
implementation. Down sampling by a factor M is implemented by keeping every Mth
sample and
throwing away M-1 samples in between. Polyphase Decimation Filter is a digital filter (FIR/IIR)
which is implemented using a polyphase decomposition technique [6][11]. Simple decimator,
polyphase decimator and efficient polyphase decimators are implemented in this paper and their
performances are compared in terms of speed, logic area occupied, power consumption, throughput
and computation rate.FIR filter is used as an antialiasing filterwhere parallelism can easily be
achieved.
2. STATE OF THE ART
H. Johansson et al. introduced filter structures for interpolation and decimation. The
structures are based on the frequency-response masking approach and make use of periodic (with a
period of 2π/M ) half-band IIR filters composed of two all-pass filters in parallel and linear-phase
FIR filters. This offers a large freedom to choose filter realizations with good properties [1].
S. Emami introduced new methods for computing interpolation and decimation of signals.
Thesemethods are easy to learn and compute and can be incorporated into digital signal processing
(DSP) courses that deal with multirate filters [2].
Kai-Yuan Cheng surveyed several architectures of FIR digital filter, several design methodologies
were adopted to reduce the hardware complexity for low-power applications and also allowable for
the high-speed applications [3].
M. B. Yeary et al. proposed an integerization technique and explores how these integerized
implementations improve performance in embedded systems. He has also introduced a new
algorithm for creating integer transform approximations and hasexplained about an optimal integer
representation. The algorithm creates a fixed integer transforms with computationally optimal
representations and a program was written to implement an optimal approximation algorithm that
finds the lowest length fraction representation within the error bound [4].
N. Onwuchekwa et al. presented Multirate DSP, Noble identities and computationally more
efficient Polyphase decomposition showed results that reduced operation and memory required by a
factor of M and L with less heat dissipation of hardware by using this[5].
A. Mukhtar et al. described a hardware efficient interpolation filter for portable digital audio
applications. The design of the filter is based on Merged Delay Transformation (MDT) [6].
N. Younis et al. presented a novel clock/data distribution technique for polyphase comb
decimation filter input registers. The proposed technique significantly reduces the dynamic power
consumption of the polyphase comb decimation filter and improves the SNR (Signal-to-Noise ratio)
of a second-order sigma-delta modulator [7].

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Dr.K.B.Khanchandani et al. reviewed the multirate approaches for designing low power DSP
systems. Since the data rate in the multirate implementation is M-times slower than the original data
rate while maintaining the same throughput rate and can apply this feature to either the low-power
implementation, or the speed-up of the DSP systems[8].
M. Madheswaran et al. briefed an implementation of different CIC filter architectures for
decimation. The different decimation filter structures are implemented on Field Programmable Gate
Array (FPGA) board and these different architectures are compared using number of used LUTs,
Registers, Power consumption etc [9].
V. Jayaprakasan et al. presented the implementation of two stage FIR (Finite Impulse
Response) decimation filter on Field Programmable Gate Array (FPGA) board using system
generator and it is compared with single stage implementation of FIR filter for WiMAX Application
related to used LUT’s and power consumption [10].
P. Jacob et al. proposed design of FIR filter, Decimation filter and Polyphase Decimation
filters and implementation was done on Field Programmable Gate Array (FPGA) board and the
results proveed that polyphase decimation filter can reduce the sampling rate of the input data stream
compared to conventional filters [11].
R. M. Rewatkar et al. Presented Optimization Technique of Multirate Polyphase Decimator
and implementation done on Field Programmable Gate Array (FPGA) board and optimized power
dissipation, speed and area analyzed using Xilinx ISE [12].
Robert D. Turney et al. provides an introduction of multirate filter techniques and polyphase
decimators and interpolators also explain wavelet theory from both a signal expansion and filter bank
viewpoint [13].
3. CONTRIBUTION OF THIS WORK
In this paper, the theoretical concepts of Multirate Decimation Filter, Multirate Decimation
Filter based on Polyphase decomposition and the computationally efficient structure of Polyphase
decimation Filter structures are developedusing Xilinx System Generator and it is synthesized for
Spartan6xslv150T-4fgg676 FPGA board. The performances of these structures are compared in
terms of speed, power consumption, logic area occupied and throughput.
4. MATERIAL AND METHODOLOGY
Multirate signal processing is essential for matching the sampling rates of multiple systems
being operated at different sample rates and connected in cascade. Fundamental operations in
Multirate signal processing are decimation and interpolation [15]. Multirate signal processing alters
the sampling without significant error in the output. In decimation, the sampling rate is reduced from
Fs to Fs/M by discarding M – 1 samples and keeping everyMth
sample in the original sequence. It
consist of digital antialiasing filter with a transfer function H(z) to band limit a input signal and a
compressor, symbolized by down arrow and the decimation factor ‘M’ as shown in Fig 1.
Fig.1: Multi rate decimator

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4.1 Polyphase Decomposition
The polyphase decomposition is a technique that divides a filter into L-sections of sub-filters
that can be realized in parallel. In this decomposition the sub-filters are differed only in phase
characteristics. The decimator shown in Fig.1 is computationally inefficient because it throws away
the processed samples. By using noble identity it is possible to rearrange the structure such that the
processed outputs are not thrown away. The filter transfer function H(z) is decomposed into
polyphase components [7][13]. Its representation is given in equation1:
(1)
The coefficients h(k) of the antialiasing filter are decomposed into M polyphase sub-filters
filters, each with (N/M) taps, where N is the number of taps in the filter and M is the decimation
factor. The transfer function of polyphase decimation filter is represented by equation 1.
Each term in equation 1 represents a polyphasesubfilter.Fig.2shows the realization of
polyphase decimation filter [3][8][12].
Fig.2: Polyphase decimation filter
The decimator in the structure of Fig.2selectsonly one sample in every M samples of the
output. It can be made computationally efficiently by embedding a down sampler block before
multiplier in FIR filter structure. The block diagram showing this operation of superposition
principal is shown in Fig.3 [5][14].
Fig.3: Superposition principal
These structures are implemented by block level simulation method i.e. Xilinx System Generator and
synthesized to evaluate and compare their performances.
The performance index matrix consists of speed, logic area, throughput, computation rate and
power consumption. Throughput (μ) is calculated by using the formula mentioned in equation2. The

5
total throughput is directly proportional to the operating frequency (F) and the levels of parallelism
(α), and inversely proportional to the size of the input(N). It is measured in terms of Mega Samples
per Sec (MSPS). The computation rate (γ) is computed using a formula mentioned in equation3 and
its unit is Mega Multiply Accumulate operations Per Sec (MMACPS). Itis directly proportional to
the levels of parallelism (α) and the maximum clock frequency (F) in MHz.
(2)
(3)
4.2 Example
In order to compare performances of Decimation Filter, Decimation Filter based on
Polyphase Decomposition and the computationally efficient structure of Polyphase Decimation
Filter, a Low Pass FIR antialiasing filter is designed. The specifications of the chosen filter are: Pass
band attenuation (Ap) 1dB, Stop band attenuation (As) 60dB, decimation factor (M) is set to 2, Input
sampling frequency Fsamp is set to 2000Hz with a Pass band edgefrequency (Fp) of 150Hz and Stop
band edgefrequency(Fstop) of 350Hz.
Using the above specifications an FIR filter is designed using Filter Design and Analysis tool
available in MATLAB. The FIR filter has an order of 19and the generated coefficients are quantized
to 16.14 fixed point format. Fixed point representation is essential for its implementation on FPGA
platform. Decimation filter implementation divides the coefficients as even and odd to half the
sampling rate (M=2). Itspolyphase representation is represented by equation4.
(4)
5. RESULTS AND CONCLUSION
The performances of decimation filter, Polyphase decimation and efficient Polyphase
decimation filters are evaluated and recorded in TABLE 1.
TABLE 1: Performance comparison of decimation filter structures

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Fig.4: Comparison of maximum frequency of
decimation structures based on timing analysis
results
Fig.5: Comparison of power consumption of
decimation structures based on power analysis
results
Fig.6: Comparison of throughput of decimation structures
The resource utilization summary is given in TABLE2.
TABLE 2: Resource Utilization of decimation filter structures

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Fig.7: Comparison of resource utilization of decimation structures based on synthesis results
The following conclusions are drawn after comparing decimation, polyphase decimation and
efficient polyphase decimation filter structures.
• The maximum frequency indicates speed of the implemented algorithm.
The efficient polyphase decimation filter structure has shown high speed with high throughput
compared to the other decimation filter structures.
• The power consumption of efficient polyphase decimation filter is less than the decimation
filter structure but more than polyphase decimation filter.
REFERENCES
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