This document describes the design and development of a 5-stage pipelined RISC processor based on the MIPS architecture. It discusses the stages of a typical 5-stage pipelined RISC processor: instruction fetch, instruction decode, execution, memory access, and write back. It then provides details on the design of a 32-bit MIPS processor with this 5-stage pipeline in Verilog HDL. The behavioral model is studied and verified to function as intended. Key aspects of the MIPS instruction sets and 5-stage pipelined design are outlined.