This document contains model answers to questions related to digital electronics and logic design. It includes questions on binary to gray code conversion, look-ahead carry generators, decade counters, full adders using multiplexers, Johnson counters, flip-flops, asynchronous state machines, programmable logic arrays, CMOS inverters, TTL logic gates, microcontroller features and addressing modes, and 8051 microcontroller pins and instructions. The document is authored by Prof. Gharu A. N. and provides detailed answers to exam questions on digital and logic circuit design topics.

1. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
DELD MODEL ANSWER NOV – 2017
Q 1. a ) Design and implement Binary to Gray code converter using logic gates. [6]
Ans :-

2. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
b ) Explain Look-ahead Carry Generator in details. [4]
Ans :

3. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.

4. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
c ) Draw basic internal structure of Decade Counter IC 7490 and explain its operation. [2]
Ans :-
OR

5. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
Q 2. a ) Implement Full Adder using 8:1 Multiplexer and draw diagram. [6]
Ans :-

6. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
b ) Write Short notes on Johnson Counter. [4]
Ans :-

7. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
c ) Convert the following flip-flop : D-ff to T-ff. (Flip-flop) [2]
Ans :-

8. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
Q 3. a ) Design the ASM Chart for a 2-bit binary counter having one enable line E such
that when : E = 1 (count enabled) & E = 0 (count is disabled). [6]
Ans :-
b ) A combinational Circuit is defined by the following function : [6]
F1(A, B, C) = ∑m (0, 1, 3, 7) F2(A, B, C) = ∑m (1, 2, 5, 6)
Implement this circuit using PLA.
Ans :-

9. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
OR
Q 4. a) Write VHDL code for Full Adder using structural style of Modeling (Declare half
adder as a component) and also draw truth table and diagram of Full Adder [6]
Ans :-
b ) Explain entity declaration for XOR gate. [2]
c ) A Combinational circuit is defined by the function :
F = ∑m(0, 1, 3, 4) Implement this circuit with PAL. [4]
Ans :-

10. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
OR
Q 5. Draw & explain the circuit diagram of CMOS Inverter. [5]
Ans :-
b ) define the following terms and mention the standard values for TTL logic family :
1. Noise Margin : a quantity measure of noise immunity of logic family is known as Noise
Margin. 0.4 V.
2. Fan Out : it is defined as the maximum number of input of the same IC family that gate
can drive without outside the specified voltage limit. Fanout is 10.
3. Power Dissipation : it means how much voltage and current is applied to particular
logic family. 10Mw.
4. Propagation Delay : time delay between two instant is called as propagation delay. 10ns.
OR

11. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
Q 6. a ) Draw and explain 2-input NAND TTL logic gate with totem pole output driver. [7]
Ans :

12. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.

13. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
b ) 1. Give the classification of logic family. [6]
Ans :
2. Explain the advantages of open collector output.
Ans : wired Anding becomes possible.

14. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
Q 7. a ) Explain the features of 8051 Microcontroller. [4]
Ans :
b ) What are the different addressing modes in 8051? Give example of each. [6]
Ans :

15. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
c ) Explain the following pins of 8051 : [3]
1. ALE : It stands for Address Latch Enable. It is used to demultiplex the address and data
line. ALE is pin no. 30 in pin diagram. It is multiplex pin.
2. XTAL : input to the inverting oscillator amplifier and input to the internal clock
operating circuit.
3. EA : External Access enable. It must be strapped to ground in order to enable the device
to fetch code from external program memory locations starting from 0000H to FFFFH.
OR
Q 8. a) Describe different timer mode of 8051 Microcontroller. Draw TMOD register. [7]

16. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
Mode 1 :
TMOD REGISTER :-
b ) Explain the following instruction with respective to 8051 and give example of each : [6]
1. PUSH :

17. Digital Electronics & Logic Design SE Computer Engineering
Pune Vidyarthi Griha’s COE, NASHIK-4 Prepared By :- Prof. Gharu A. N.
2. MUL :
3. CPL :
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