Optimized Floating-point Complex number multiplier on FPGA
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This document presents the design of an optimized floating point complex number multiplier on an FPGA. It begins with an introduction and motivation for the project, explaining that complex number multiplications are common in signal processing. It then discusses previous complex number multiplier designs and their limitations. The proposed architecture is described, using three intermediate multiplications to calculate the real and imaginary parts. Simulation results are shown for the floating point adder/subtractor and multiplier blocks. The current status and future work are outlined, along with references.
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Complex Number Updated
This Our presentation about complex number.
This is very easy and you can explore it to all within a short time .
I think everybody like it and satisfied about this presentation.
Class10
The document discusses floating point arithmetic and the IEEE 754 standard. It covers topics such as floating point representation including normalized and denormalized numbers, special values like infinity and NaN, rounding modes, and properties of floating point operations like addition and multiplication. Examples are provided to illustrate concepts like normalized encoding, the dynamic range of different representations, and answers to puzzles about floating point comparisons and operations.
Decimal arithmetic in Processors
To represent a binary floating-point number as an exact fraction, the number of decimal digits needed depends on the precision of the binary floating-point format. Higher precision formats like double precision may require on the order of 15-17 decimal digits.
To represent a binary floating-point number reversibly so that it can be converted back to the same binary value, the number of decimal digits needed depends on the precision as well as the desired rounding mode. For double precision numbers using round-to-nearest rounding, about 16-17 decimal digits are typically needed.
Fixed-point arithmetic
The document discusses fixed-point arithmetic, which represents numbers using a fixed number of bits after the binary point. It compares fixed-point to integer and floating-point representations. It then covers notation for representing fixed-point numbers, converting between types, rounding methods, basic operations, and implementing common mathematical functions using fixed-point arithmetic. Several open-source fixed-point arithmetic libraries are also mentioned.
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Representation of complex number
This slide describes on the historical events, representation types and application of the complex number.
Representation of Real Numbers
Real numbers include whole numbers, rational numbers like fractions and decimals, and irrational numbers like pi. They can be positive, negative or zero. In computing, real numbers are represented using floating point notation, which stores numbers as a mantissa and exponent. The mantissa holds the significant digits of the number, while the exponent tracks the decimal place. Increasing the bit size of the mantissa improves accuracy, while increasing the exponent size expands the representable range of numbers.
X2 T01 01 complex number definitions
The document discusses complex numbers and their definitions. It states that all complex numbers can be written as z = x + iy, where x is the real part and y is the imaginary part. If the real part is 0, the number is pure imaginary, and if the imaginary part is 0, the number is real. Every complex number has a complex conjugate of z = x - iy.
Fixed point and floating-point numbers
Fixed-point and floating-point numbers can be represented in computers using binary numbers. Floating-point numbers represent numbers in scientific notation with a sign, mantissa, and exponent. In 8-bit floating point, numbers use 1 bit for sign, 3 bits for exponent, and 4 bits for mantissa, such as 0.001 x 21 = 2.25. Larger precision formats such as 32-bit and 64-bit floating point according to the IEEE standard use more bits for exponent and mantissa.
Complex number
A complex number is a number that can be expressed in the form a + bi, where a and b are real numbers and i is the imaginary unit, satisfying the equation i2 = −1.[1] In this expression, a is the real part and b is the imaginary part of the complex number. If {\displaystyle z=a+bi} {\displaystyle z=a+bi}, then {\displaystyle \Re z=a,\quad \Im z=b.} {\displaystyle \Re z=a,\quad \Im z=b.}
Complex numbers extend the concept of the one-dimensional number line to the two-dimensional complex plane by using the horizontal axis for the real part and the vertical axis for the imaginary part. The complex number a + bi can be identified with the point (a, b) in the complex plane. A complex number whose real part is zero is said to be purely imaginary, whereas a complex number whose imaginary part is zero is a real number. In this way, the complex numbers are a field extension of the ordinary real numbers, in order to solve problems that cannot be solved with real numbers alone.
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The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
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Complex number
The document provides an introduction to complex numbers including:
- Combining real and imaginary numbers like 4 - 3i.
- Properties of i including i2 = -1.
- Converting complex numbers between Cartesian, polar, trigonometric and exponential forms.
- Operations on complex numbers such as addition, subtraction, multiplication and division.
- Comparing real and imaginary parts of complex numbers when solving equations.
Quick tutorial on IEEE 754 FLOATING POINT representation
CONVERSION FROM STANDARD DECIMAL FORM TO IEEE 754 STANDARD FLOATING POINT REPRESENTATION AND VICE VERSA
1.3 Complex Numbers, Quadratic Equations In The Complex Number System
1) The document introduces complex numbers as a way to solve equations that involve taking the square root of a negative number.
2) It defines the imaginary unit i as the number such that i^2 = -1, and defines complex numbers as numbers of the form a + bi, where a is the real part and bi is the imaginary part.
3) It provides rules for adding, subtracting, multiplying and dividing complex numbers by treating the real and imaginary parts separately and using properties of i.
Complex number
This document provides an overview of complex numbers. It defines complex numbers as numbers consisting of a real part and imaginary part written in the form a + bi. It discusses the subsets of complex numbers including real and imaginary numbers. It also covers topics such as the complex conjugate, modulus, addition, subtraction, multiplication, and division of complex numbers. Finally, it mentions applications of complex numbers in science, mathematics, engineering, and statistics.
06 floating point
The document discusses floating point numbers and the IEEE 754 standard. It describes how floating point numbers represent numbers with fractions using a sign bit, exponent field, and fraction field. The IEEE 754 standard uses a biased exponent representation for normalized floating point values, along with special values like infinity and NaN. It also details denormalized numbers, which allow gradual underflow to zero.
Computer arithmetic
All the data about computer arithmetic .. i searched for it in slide share but no result.. so i made it for u guys..
Complex numbers org.ppt
Osama Tahir's presentation introduces complex numbers. [1] Complex numbers consist of a real and imaginary part and can be written in the form a + bi, where i = -1. [2] Complex numbers were introduced to solve equations like x^2 = -1 that have no real number solutions. [3] Key topics covered include addition, subtraction, multiplication, and division of complex numbers, representing them in polar form using De Moivre's theorem, and applications in fields like electric circuits and root locus analysis.
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Online Dating Recommender Systems: The Split-complex Number Approach
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Quick tutorial on IEEE 754 FLOATING POINT representation
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1.3 Complex Numbers, Quadratic Equations In The Complex Number System
1.3 Complex Numbers, Quadratic Equations In The Complex Number System
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Optimized Floating-point Complex number multiplier on FPGA
- 1. Optimized Floating- Point Complex Number Multiplier on FPGA Presented By M. Jaya Lakshmi (10B01D5705) Under the esteemed guidance of Dr. K. Pushpa Professor in ECE ,Head of ATL Shri Vishnu Engineering College for Women, Bhimavaram, AP
- 2. Page 2 Agenda Aim Motivation Background Introduction Proposed Architecture of Complex Number Multiplier . Floating point Adder/Subtractor . Floating Point Multiplier Work done Simulation Results Status of the Project References
- 3. Page 3 Aim To design floating point complex number multiplier which # Occupies less area # Consumes less power # High Speed
- 4. Page 4 Motivation In general signals are represented as complex numbers. Operations on complex numbers represent a large part of DSP operations Every modern DSP includes a Floating-Point (FP) multiplier that complies with the IEEE- 754 Standard. Large portion of the FP instructions consists of FP
- 5. Page 5 Background One Complex Number Multiplier was reported by Akinwande . It is very fast implementation in GaAs hetero structure FET technology. But the level of integration for this multiplier is very low It is also possible to use CORDIC algorithm for computation of product of two complex numbers, but CORDIC algorithm design was complex and should be designed with rotation algorithms with reference to angles. Many complex number multipliers are designed previously using four IEEE-754 floating Point Multipliers .
- 6. Page 6 Introduction Multiplication of two complex numbers is a very frequent operation in many signal processing algorithms A general complex number multiplication is as follows (a+jb) (c+jd) = (ac-bd) + j(ad+bc) -Here 4 multipliers and 3 Adder/Subtractor blocks are used -floating point multiplier occupies large area on FPGA.
- 7. Page 7 Contd. . . Representation of IEEE-754 Floating point Number •1-bit sign, S: A value of ‘1’ indicates that the number is negative, and a ‘0’ indicates a positive number •Exponent: e = E + bias: This gives us an exponent range from Emin = -126 to Emax = 127 •Fraction /mantissa: The fractional part of the number
- 8. Page 8 Proposed Architecture Of Complex Number Multiplier Three intermediate multiplications are defined as follows Real Part : P+Q Imaginary part : Q- P
- 9. Page 9 Contd. . .
- 10. Page 10 FLOATING -POINT ADDER/SUBTRACTOR
- 11. Page 11 Floating Point Multiplier
- 12. Page 12 Work done Simulated Floating point Adder/Subtractor Simulated Floating Point Multiplier
- 13. Page 13 Simulation Results Fig. Simulation results for Floating Point Multiplier IEEE-754 FP number Decimal Equivalent 40133333 2.3 3fa66666 1.3 403f5c28 2.9 3fd851ea 1.69
- 14. Page 14 Contd . . . IEEE-754 FP number Decimal Equivalent 40133333 2.3 3fa66666 1.3 40666666 3.6 3f800000 1 Fig. Simulation results for Floating Point Adder/ Subtractor
- 15. Page 15 Status of the Project I have Presented my project in a National Conference on “ Expanding Horizon in Computer, Information Technology, Telecommunication & Electronics” organized by IETE at Layola ICAM college, Chennai. I have designed IEEE-754 single precision Floating-point arithmetic and I have to implement complex number multiplier using this arithmetic block. I would like to implement this complex number multiplier using inbuilt Wallace tree, Dadda , Modified Booth algorithms and compare the results In future I would like to use the complex number multiplier to calculate FFT
- 16. Page 16 References G. Even and P.-M. Seidel. “A comparison of three rounding algorithms for IEEE floating- point multiplication”. Technical Report EES1998-8, EES Dep., Tel-Aviv Univ., 1998. http://www.eng.tau.ac.il/Utils/reportlist/reports/repfram.html C. Hinds, E. Fiene, D. Marquette, and E. Quintana. “Parallel method and apparatus for detecting and completing floating point operations involving special operands”. U.S. patent 5339266, 1994. IEEE standard for binary floating point arithmetic. ANSI/ IEEE754-1985, New York, 1985. S. Oberman, H. Al-Twaijry, and M. Flynn. The SNAP project:Design of floating point arithmetic units. In Proceedings of the 13th Symposium on Computer Arithmetic, volume 13, pages 156–165. IEEE, 1997. Akinwande “A 500 MHz 16x16 Complex Multiplier using Self -Aligned gate GaAs Hetero Structure FET technology”, IEEE journal of Solid-State circuits, 2009 http://www.etsimo.uniovi.es/~antonio/uned/ieee754/IEEE-754hex32.html www.xilinx.com
- 17. Thank You