This document describes the design and implementation of a power optimized 32-bit floating point arithmetic logic unit (ALU) using a block enabling technique. It discusses the motivation, introduction, literature survey, objectives, floating point ALU design, block enabling technique, tools used, and plan of action. The document presents the design of floating point addition, subtraction, multiplication, and division modules. It compares the synthesis results and power analysis of the proposed floating point ALU with block enabling to a conventional floating point ALU. The goal is to reduce power consumption by limiting unnecessary switching activities through the block enabling technique.
1. DESIGN AND IMPLEMENTATION OF POWER OPTIMIZED
HIGH PERFORMANCE 32 BIT FLOATING POINT ALU
EMPLOYING BLOCK ENABLING TECHNIQUE
Under the guidance of
Dr .Y. SYAMALA
Associate Professor
Department of ECE
Gudlavalleru Engineering College.
By
B N V A SURENDRA BABU
13481D5505
M.Tech -Embedded Systems.
2. CONTENTS
Motivation
Introduction
Literature survey
Objective
Floating point ALU
Block enabling technique
Floating point ALU block diagram
Tools required
Plan of action
Conclusion
References
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3. INTRODUCTION
Floating point describes a system for representing
numbers that would be too large or too small.
IEEE-754 32-bit Single-Precision Floating-Point
Numbers represented as
The floating point coprocessor perform operations
more efficiently and faster, so that it increasing
the overall speed of a computer.
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4. LITERATURE SURVEY
In 2013, Manisha Sangwan and Angeline implemented Floating
point ALU with four basic operations like addition, subtraction,
multiplication ,division and they performed functional verification
of the system.
Itagi Mahal and S.S kerur implemented Floating point point ALU
in 2013, and they had shown results in terms of number of clock
cycles required for each operation.
In 2011, Ankit mitra implemented ALU with clock gating technique
and the results were compared with the ALU with out clock gating
technique.
Jagrit Kathuria and Ayoubkhan implemented different types of
clock gating techniques in 2011 and they had shown their simulation
results.
In 2013, Manisha and Anita Angeline implemented a Pipelined FP
Co-Processor which performs four basic arithmetic operations and
results were compared with the existing coprocessor.
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6. OBJECTIVE
To design a 64bit floating point ALU core using
verilog HDL.
To simulate using xilinx-14.7 ISE simulator .
To synthesize using xilinx-14.7 XST synthesizer.
Power analysis will be observed using xilnx-
14.7 XPA .
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9. SYNTHESIS RESULTS AND POWER ANALYSIS OF
FLOATINGPOINT ADDER
Number of Slice Registers utilized 617 out of 69120 0%
Number of Slice LUTs utilized 514 out of 69120 0%
Number of fully used LUT-FF pairs 330 out of 801 41%
umber of bonded IOBs utilized 198 out of 640 30%
Adders/ Subtractors 5
Registers 23
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frequency(MHZ) power(W)
100 1.212
200 1.376
300 1.535
400 1.693
500 1.849
Device utilization summary:
power analysis :
12. SYNTHESIS RESULTS AND POWER ANALYSIS OF
FLOATINGPOINT SUBTRACTOR
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frequency(MHZ) power(W)
10 1.074
100 1.278
200 1.506
300 1.731
400 1.955
500 2.719
Device utilization summary:
Number of Slice Registers utilized 689 out of 69120 0%
Number of Slice LUTs utilized 1138 out of 69120 1%
Number of fully used LUT-FF pairs 437 out of 1390 31%
umber of bonded IOBs utilized 437 out of 1390 31%
Adders/ Subtractors 3
Registers 688
power analysis :
15. SYNTHESIS RESULTS AND POWER ANALYSIS
OF FLOATINGPOINT MULTIPLIER
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Device utilization summary:
Number of Slice Registers utilized 1214 out of 69120 1%
Number of Slice LUTs utilized 1991 out of 69120 2%
Number of fully used LUT-FF pairs 1060 out of 2145 49%
umber of bonded IOBs utilized 200 out of 640 31%
Adders/ Subtractors 9
Registers 1236
power analysis :
frequency(MHZ) power(W)
10 1.052
100 1.143
200 1.365
300 1.585
400 1.805
500 2.024
18. SYNTHESIS RESULTS AND POWER ANALYSIS
OF FLOATINGPOINT DIVISION MODULE
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Device utilization summary:
Number of Slice Registers utilized 938 out of 69120 1%
Number of Slice LUTs utilized 1843 out of 69120 2%
Number of fully used LUT-FF pairs 638 out of 2143 29%
umber of bonded IOBs utilized 200 out of 640 31%
Adders/ Subtractors 10
Registers 919
power analysis :
frequency(MHZ) power(W)
10 1.059
100 1.221
200 1.388
300 1.552
400 1.716
500 1.879
19. BLOCK ENABLING TECHNIQUE
Changing the logic state
of the circuit leads
to power dissipation.
Block enabling technique
is used to reduce
unnecessary Switching
activities.
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20. FLOATING POINT ALU
In this work, the floating point ALU will be
designed to perform eight number of different
arithmetic and logical operations.
This floating point ALU is employed with block
enabling technique which is used to reduce the
total power consumption of the existing FPU.
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22. TOOLS USED
Tools Required: Front end Design Tools-XILINX 14.7
Language Required: verilog HDL programming
language.
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23. PLAN OF ACTION
S.NO ACTIVITY WEEKS(40)
1 Literature survey 3
2 Study and implementation of base paper 4
3 Implementation of floating point addition
/subtraction module+ Literaure survey.
3
4 Implementation of other floating point
modules +Literaure survey.
8
5 Implementation of floating point ALU with
block enabling technique.
6
6 Power Analysis of Proposed floating point ALU
and Conventional ALU +Literature survey
8
7 Paper publication work +Literature survey 4
8 Project documentation work +Literature survey 4
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24. CONCLUSION
A double precision 64 bit floating point
ALU will implement with block enabling
technique.
The results of this proposed floating point
ALU with block enabling technique will
compared with the conventional floating
point ALU.
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25. REFERENCES
[1] Manisha Sangwan, A Anita Angeline “Design and Implementation of Single Precision
Pipelined Floating Point Co-Processor” 2013 International Conference on Advanced
Electronic Systems (ICAES) ,pp. 78-81, july2013.
[2] Rajit Ram Singh, Asish Tiwari, Vinay Kumar Singh, GeetamS “VHDL environment for
floating point Arithmetic Logic Unit -ALU design and simulation” in 2011 IEEE
International Conference on Communication Systems and Network Technologies , pp.
162-170, july2011.
[3] Sameh Galal, Student Member, IEEE, and Mark Horowitz, Fellow, IEEE “Energy-
Efficient Floating-Point Unit Design” IEEE transactions on computers, pp. 913-922,
july 2011.
[4] Manish Kumar Jaiswal ,Ray C.C. Cheung “VLSI Implementation of Double-Precision
Floating- Point Multiplier Using Karatsuba Technique” Springer Science+Business
Media, pp.15 -27, 19 July 2012.
[5] Jeff Rupley, John King, Eric Quinnell, Frank Galloway, Ken Patton, Peter-Michael
Seidel, James Dinh, Hai Bui, “The Floating-Point Unit of the Jaguar x86 Core” IEEE
21st Symposium on Computer Arithmetic., pp.7-16, july 2013.
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16
26. [5]Taek-Jun Kwon, Jeff Sondeen and Jeff Draper ,“Floating-Point Division and Square Root
Implementation using a Taylor-Series Expansion Algorithm”, IEEE 2008, pp. 106-118,
july 2008.
[6] A. Vazquez, E. Antelo, and P. Montuschi, “A New Family of High–“Performance Parallel
Decimal Multipliers”. Proceedings of the 18th IEEE Symposium on Computer Arithmetic,
pp. 195-204, June2007.
[7] Taek-Jun Kwon, Joong-Seok Moon, Jeff Sondeen, Jeff Draper,“0.18μm Implementation of a
Floating - Point Unit for a Processing-In-Memory System”, in Proc. of the IEEE
Internation Symposium on Circuits and Systems, pp. 922-936, May 2004.
[8] P. Belanovic and M. Leeser, “A Library of Parameterized Floating-Point Modules and
Their Use”, in 12th International Conference on Field-Programmable Logic and
Applications (FPL-02). London, UK: Springer-Verilag, pp. 632-649, September 2002 .
[9] G. Even and P.-M. Seidel, “A Comparison of Three Rounding Algorithms for IEEE
Floating-Point Multiplication,”IEEE Trans.Computers, pp. 638-650, July 2000.
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28. Yes No
Pass the value of
exponent and mantissa
Left shift the smaller
mantissa by the difference
Left shift the smaller
mantissa by the
difference
If e2>e1
start
Take two operands in
IEEE754 standard
Compare
two
exponents
If e1>e2If e1=e2
Take two sign bits,
exponent & two mantissas
XOR the Sign
bits of
mantissas
Is sign
Add theSubtract the
