The document contains questions from a switching theory and logic design exam. It asks students to answer any five of eight questions. The questions cover topics like: 1. Complements and duals of Boolean functions 2. Implementing logic circuits with PLA and K-maps 3. Sequential circuits like counters, flip-flops and state machines 4. Codes like binary, gray and hamming codes 5. Arithmetic operations using binary numbers

1. R09 Set No. 2Code No: A109211002
1
II B.Tech I Semester Examinations,MAY 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) Explain the procedure to obtain the Complement of a Function. Explain how
it differs from Dual of a function.
(b) Determine the complements of the following function.
i. AB+ CD(AB0
+CD)
ii. AB(BC0
+BC)(AC0
+AB)
iii. A + B[A +(B+C)0
D]
iv. AB + A0
B0
+ A0
BC [8+7]
2. (a) How the size of PLA specified? How to calculate the number of programmed
fuses? What is the number of inputs, product terms and outputs in a typical
PLA?
(b) A combinational logic circuit is defined by the functions
F1(X,Y,Z) = Σ(1,4,5,7) F2(X,Y,Z) = Σ(0,1,4,7) Implement the circuit with a
PLA having 3 inputs, 4 product terms and 2 outputs. [8+7]
3. Reduce the given function using Quine McC lusky method
F(A,B,C,D,E,F)=Σm (0,1,2,4,6,9,12,16,21,25,29,32,37,41,43,45,56,58,62,63) [15]
4. (a) Write short notes on Asynchronous inputs.
(b) What is excitation table? Write the excitation tables for the following flip
flops.
i. SR Flip flop
ii. JK flip flop
iii. D flip flop
iv. T flip flop [4+11]
5. (a) Draw an ASM chart for designing a circuit which is used to count the number
of bits in a register that have a value 1.
(b) Discuss the procedure to implement an ASM chart using Multiplexer. [8+7]
6. Find the equivalence partition for the machine shown in figure. Show a standard
form of the corresponding reduced machine. Find a minimum length sequence that
distinguishes state A from state B. [15]

2. R09 Set No. 2Code No: A109211002
2
PS NS,Z
X = 0 X = 1
A B,1 H,1
B F,1 D,1
C D,0 E,1
D C,0 F,1
E D,1 F,1
F C,1 E,1
G C,1 D,1
H C,0 A,1
7. (a) Explain Alphanumeric codes.
(b) Convert the decimal number 99 and 54 to Gray code.
(c) Convert the gray code number 1010000 and 1001001011 to the equivalent
binary Number. [5+5+5]
8. (a) Design a 4 bit parallel adder. Differentiate serial adder and parallel adder.
(b) Design a circuit to eliminate the propagation delay in the parallel adder. [8+7]
? ? ? ? ?

3. 3
R09 Set No. 4Code No: A109211002
II B.Tech I Semester Examinations,MAY 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) Express the Boolean function:
F(x,y,z) = xy +x0
z in a product of maxterm form
(b) How many rows will be there in the truth table of a logic system having n
input binary variable?
(c) Prepare the truth table for the Boolean function
F(X, Y , Z) = X(YZ0
+ Y0
Z) [7+2+6]
2. Design a logic circuit with BCD input and the output of the circuit should produce
a gray code for corresponding input. Use K-map for reduction. [15]
3. (a) What are Self complementing codes? Give examples.
(b) Write the procedure for constructing Hamming codes. Construct hamming
codes for the decimal numbers 1,4,8. [8+7]
4. (a) Design a Serial in and parallel out 4 bit Shift Register.
(b) Design a 8-bit Ring counter. [8+7]
5. (a) If for example the following events are listed in a ASM block, compare the
execution with respect to conventional flow chart and ASM chart.
i. Register A is incremented
ii. Value of E is verified.
iii. If E=1, then Register R is cleared and control goes to state T4.
iv. If E=0, then the value of F is verified.
v. Depending upon the value of F the control goes to state T2 or T3
(b) Draw the State diagram of a Mod-6 counter. Implement the same in the ASM
chart. Explain the sequence of operation in each ASM block. [8+7]
6. Define UNATE functions. Give the properties of Unate functions. [15]
7. Design a Logic circuit which accepts two 5 bit binary numbers. The circuit should
perform binary addition when the carry in is 0 and should perform binary subtrac-
tion using 2’s complement addition when the input carry is 1. [15]
8. Give the conditions for the two machines are to be equivalent. For the Machine
given below, find the equivalence partition and a corresponding reduced machine

4. 4
R09 Set No. 4Code No: A109211002
in standard form. [15]
PS NS,Z
J1 J2
Y1 Y6,0 Y2,1
Y2 Y7,0 Y1,1
Y3 Y2,0 Y3,1
Y4 Y3,0 Y2,1
Y5 Y4,0 Y1,1
Y6 Y5,1 Y6,1
Y7 Y5,1 Y7,1
? ? ? ? ?

5. 5
R09 Set No. 1Code No: A109211002
II B.Tech I Semester Examinations,MAY 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) Give details about the invention of Boolean algebra. How was it modified
later? Define Binary logic.
(b) For the following functions draw the truth table.
i. F1 = x0
yz
ii. F2 = x0
y0
z + x0
yz + xy0
iii. F3 = xy0
+ x0
z [8+7]
2. For the machine shown in table below obtain.
(a) The corresponding reduced machine table in standard form.
(b) Find a minimum length that distinguishes state A from state B. [15]
PS NS,Z
X=0 X=1
S1 S2,1 S8,1
S2 S6,1 S4,1
S3 S4,0 S5,1
S4 S3,0 S6,1
S5 S4,1 S3,1
S6 S3,1 S3,1
S7 S3,1 S4,1
S8 S3,0 S1,1
3. (a) Design a Modulo 8 Gray counter.
(b) Discuss the usage of Preset and clear inputs. Discuss the operation performed
for different combinations of preset and clear. [10+5]
4. Design a sequential logic circuit of a 4 bit counter to start counting from 0000 to
1000 and this process should go on. Draw the ASM chart and design the Data
processing unit and the control unit. [15]
5. (a) Design a logic circuit which converts serial input to parallel output.
(b) Design a combinational logic circuit which compares two 4 bit numbers (A&B)
and produces 3 outputs to indicate whether A>B or A=B or A<B.(DL-M).
[8+7]
6. Map the following function and simplify using K-Map

6. 6
R09 Set No. 1Code No: A109211002
(a) F = (A+B+C)(A+B0
+C)(A+B0
+C0
)(A0
+B+C)
(b) F = (A0
BC0
D0
+A0
BC0
D+AB0
CD+AB0
CD0
+ABCD+A0
B0
C0
D0
) [15]
7. Implement the following Boolean functions using ROM and PAL.
F1(x,y,z) = Σ(0,1,5,7)
F2(x,y,z) = Σ(1,2,3,6,7)
F3(x,y,z) = Σ(3,5,6,7)
F4(x,y,z) = Σ(0,2,3,4,6) [15]
8. (a) The binary numbers listed have a sign bit in the left most position and, if nega-
tive, are in 1’s complement form. Perform the arithmetic operations indicated
and verify the answers.
i. 100101 + 110010
ii. 001000 + 101010
iii. 110011 - 001011
iv. 100001 110100
(b) Explain how 1’s complement and 2’s complement of a binary number is ob-
tained? Illustrate by an example. [11+4]
? ? ? ? ?

7. 7
R09 Set No. 3Code No: A109211002
II B.Tech I Semester Examinations,MAY 2011
SWITCHING THEORY AND LOGIC DESIGN
Common to Instrumentation And Control Engineering, Electronics And
Computer Engineering, Electronics And Instrumentation Engineering
Time: 3 hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. Draw the block diagram of the 3 to 8 decoder. Draw the circuit diagram of the
decoder and explain the operation of the decoder.
(a) If the input 3 bit code is 110, then which decoder output will be HIGH?
(b) If the output of the decoder D3 is HIGH, what is the input code of the decoder?
[15]
2. Design a combinational logic circuit is defined by the functions
F1 = a0
b0
c0
d + a0
c0
d0
+ ab0
cd0
F2 = a0
b0
c + b0
cde0
+ a0
bcde0
F3 = abcd0
+ ab0
cd0
+ abcde0
[15]
3. Express the following in standard POS form
(a) F = A0
BC+AB0
C+ABC+ABC
(b) F = X0
YZ+W0
Y0
Z +WXYZ0
(c) F = F = PQ+RS+P0
Q+P0
QR
(d) F = MNOP+M0
OP+MNP0
[15]
4. (a) Write short notes on ASM chart. Give the different boxes used in the ASM
chart. Explain them with examples.
(b) Write the salient features of ASM chart. [8+7]
5. (a) Explain in detail about Mealy machine and Moore machine.
(b) Explain the minimization procedure of completely specified sequential ma-
chines. [8+7]
6. (a) Differentiate in detail the synchronous and asynchronous sequential circuits.
(b) Design the SR flip flop using NAND gates and explain its operation with the
help of characteristic table and characteristic equation. [8+7]
7. Draw the logic circuits using AND, OR, NOT elements to represent the following:
(a) AB0
+A0
B
(b) ((AB)0
(CD)0
)0
(c) ((A+B)(C+D))E +FG

8. 8
R09 Set No. 3Code No: A109211002
(d) AB + (AB)0
+ A0
BC
Implement the above functions using only NAND gates and only NOR gates [15]
8. What are Gray codes? Justify how gray code is an Un-weighted code. Why Gray
code is called as cyclic code. Create 4-bit Gray codes using reflection method. [15]
? ? ? ? ?