This document discusses pipelining in CPUs. It describes the stages in a typical instruction pipeline as fetch, decode, calculate operands, fetch operands, execute, and write back. It provides timing diagrams to illustrate how pipelining allows overlapping execution of instructions. It also discusses hazards that can occur in pipelining, including resource hazards when instructions need the same resource, data hazards when instructions depend on previous results, and control hazards with branches. Solutions proposed include increasing resources, forwarding dependencies, branch prediction, and delayed branching.