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Pipelining
Acknowledgement
Mr. Gazi Zahirul Islam
Assistant Professor
Department of Computer Science and
Engineering
Group Name: Gain Of Day
Nirnay Mukharjee
ID: 143-15-4421
What is Pipeline?
Types of Pipeline
• Fetch instruction(FI)
• Decode instruction(DI)
• Calculate operands(CO)
• Fetch operands(FO)
• Execute instructions(EI)
• Write operands(WO)
Two stage instruction pipeline.
Timing Diagram for
Instruction Pipeline Operation
The Effect of a Conditional Branch on
Instruction Pipeline Operation
Six Stage
Instruction Pipeline
Alternative Pipeline Depiction
Hazards of Pipelining
 Types of hazards
 Resource Hazards
 Data Hazards
 Control Hazards
Resource Hazards
 Two (or more) instructions in pipeline need same
resource
 Executed in serial rather than parallel for part of
pipeline
 Also called structural hazard
 E.g. Assume simplified five-stage pipeline
-Each stage takes one clock cycle
 One solution: increase available resources
-Multiple main memory ports
-Multiple ALUs
Resource Hazards Diagram
Data Hazards
 E.g. x86 machine instruction sequence:
• ADD EAX, EBX /* EAX = EAX + EBX
• SUB ECX, EAX /* ECX = ECX – EAX
Data Hazard Diagram
Types of Data Hazard
Read after write
(RAW),or
true dependency
Write after read
(WAR),or
anti-dependency
Write after write
(WAW), or
output dependency
Data Hazard
Write After Read (WAR) Write After Write (WAW)
• A write after read (WAR) data
hazard represents a problem
with concurrent execution.
Example
For example:
i1. R4 <- R1 + R3
i2. R3 <- R1 + R2
• A write after write (WAW) data
hazard may occur in a concurrent
execution environment.
Example
For example:
i1. R2 <- R4 + R7
i2. R2 <- R1 + R2
Control Hazard
• Dealing with Branches
– Multiple Streams
– Prefetch Branch Target
– Loop buffer
– Branch prediction
– Delayed branching
Branch Prediction Flowchart
Thank You

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