Chpt 4 (presentation 2)
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To learn the definition of Static CMOS Logic Circuit, truly know how to apply in use of the function of Static CMOS Logic Circuit in life.
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This document summarizes research on gate leakage reduction techniques for deep submicron integrated circuits. It discusses how gate leakage has become a significant source of power dissipation as devices are scaled down, due to increased subthreshold leakage, gate oxide tunneling, and reverse bias junction leakage. The document then describes complementary pass transistor logic (CPL) and differential cascade voltage switch logic (DCVSL) as logic families that aim to reduce static power by using fewer transistors and eliminating inverters.
low pw and leakage current techniques for cmos circuits
This document discusses various techniques to reduce leakage power in CMOS circuits, including the sleep mode approach, stack mode approach, leakage feedback approach, sleepy stack approach, and sleepy keeper approach. It then proposes a new LECTOR technique which introduces two leakage control transistors between the pull-up and pull-down circuits to ensure that one transistor is always near cutoff, reducing leakage power dissipation. The document concludes that leakage reduction is important for VLSI circuit design as scaling continues, and that the LECTOR method is effective at reducing leakage power in both active and standby modes.
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9_DVD_Dynamic_logic_circuits.pdf
This document discusses dynamic logic circuits. It describes how dynamic circuits use temporary storage of signal values on capacitance rather than a static low or high value. Dynamic circuits have advantages like smaller silicon area and lower power compared to static circuits, but require a clock and are susceptible to charge leakage issues. Several types of dynamic logic are described, including dynamic latches, dynamic shift registers, and domino logic, which cascades evaluation stages to improve speed but can have charge sharing problems. Precharge-evaluate and other clocked dynamic logic styles aim to address these issues.
UNIT-4-Logic styles for low power_part_2.ppt
There are two approaches to realize digital circuits using MOS technology: gate logic and switch logic. Gate logic uses inverters and gates like NAND and NOR, while switch logic uses pass transistors. There are also two types of gates - static and dynamic. Static gates do not need a clock, while dynamic gates use intrinsic capacitors that must be refreshed regularly to avoid information loss. The document discusses three logic styles for low power design: static CMOS logic, dynamic CMOS logic, and pass transistor logic (PTL), outlining their advantages and disadvantages in area, power, speed, and complexity.
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IC_Lectures_Updated.pdf
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Chpt 4 (presentation 2)
- 1. By : LIEW YONG HAO (07DEP15F1056) CAROLINE SAMADAU (07DEP15F1087) DEE6113 - CMOS IC DESIGN PRESENTATION 2
- 2. Static CMOS logic - The principle of static CMOS logic is the output is connected to ground through an n- block and to VDD through a dual p-block - Without changes of the inputs, this gate consumes only the leakage currents of some transistors. - When it is switching, it draws an additional current which is needed to charge and discharge the internal capacitances and the load. - Although the gate's logic function is ideally independent of the transistor channel widths, they determine the dynamic behavior essentially: wider transistors will switch a capacitive load faster, but they will also cause a larger input capacitance of the gate. - Unless otherwise noted, minimum-width and, of course, minimum-channel-length transistors are assumed. - For given capacitances the transistors' on-state current will limit the switching speed of the gate and, consequently, the maximum clock frequency of a synchronous circuit
- 4. Ex: Logic gates, mux, decoder, adder Ex: Registers, counters, oscillators, memory
- 5. COMBINATIONAL LOGIC SEQUENTIAL LOGIC - Circuits (or non-regenerative) that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). - No intentional connection between outputs and inputs is present. - Or regenerative circuits — the output is not only a function of the current input data, but also of previous values of the input signals - This is accomplished by connecting one or more outputs intentionally back to some inputs. - Consequently, the circuit “remembers” past events and has a sense of history. - A sequential circuit includes a combinational logic portion and a module that holds the state.