Design of a Low Voltage Low Dropout LDO Regulator Using Current Splitting Technique and 90nm Technology.

1. A Presentation
On
DESIGN OF A LOW- VOLTAGE LOW- DROPOUT REGULATOR
In Partial Fulfillment of the Requirements for the Degree of
MASTER OF TECHNOLOGY
in
Advanced Electronics and Communication Engineering with Specialization in VLSI Design
by
DEVYANI
(Enrollment No.: 1309136702)
Under the Supervision of
Dr. Sampath Kumar and Mrs. Sangeeta Mangesh
JSS Academy of Technical Education, Noida
To the
Department of Electronics Engineering
Dr. A.P.J. ABDUL KALAM UNIVERSITY
LUCKNOW
May 2016

2. OUTLINE
• Problem Statement
• Project Objective
• Block Diagram
• Proposed Work (Basic Circuit to result analysis)
• Conclusion
• Future Scope
References

3. PROBLEM STATEMENT
“Design Of Low-Voltage Low-Dropout Regulator Using Current Splitting Technique
And 90nm CMOS Technology”

4. PROJECT OBJECTIVE
The aim is to design a LDO using current splitting technique with 90nm technology
model file. In which input of 1V convert into output of 0.85-0.5V with load of 1μF and
quiescent current of 60μA.
The next aim is to optimize the circuit to reduce power dissipation.

5. BLOCK DIAGRAM
Conceptual block diagram of LDO regulator

6. BASIC CIRCUIT OF LDO
LDO With Capacitor

7. SIMULATION OF LDO WITH 1μF CAPACITOR
and
AVERAGE POWER IS 7.06mW

8. CONVENTIONAL TWO STAGE MILLER OP- AMP

9. ANALYSIS OF SLEW RATE OF TWO STAGE MILLER OP- AMP

10. PROPOSED LDO WITH APPOS CIRCUIT

11. SIMULATION OF PROPOSED LDO WITH APPOS CIRCUIT
And
AVERAGE POWER IS 2.07mW

12. CONCLUSION
This project contains a deep study of LDO. An input of 1V used to achieve output of
0.85 to 0.5 V with a load capacitor of 1uF and quiescent current up to 60uA. This
LDO provides minimum area of 0.0041mm2. But the drawback of the circuit is that it
doesn’t include power and energy delivered to meet this compact area desire. However,
on the basis of simulation results we can see that the power consumed by circuit is 7.06
mW which is exceptionally quite large.
In order to maintain a tradeoff between power and area an assistant push- pull output
stage circuit was introduce along with class AB stage op- amp through which power
consumption reduced to a level. And, this time average power of the circuit was
2.07mW

13. FUTURE SCOPE
We use low dropout regulator in most hand-held, battery-powered electronics feature power
saving techniques to reduce power consumption.
• The complexity and density of today's electronic designs equate to a limited amount of
PCB space. In order to address the trend toward ever-smaller electronics, LDOs must
deliver the same performance while consuming as little space as possible.
• It offers a variety of LDOs that have been designed to address high-performance
requirements in a tiny solution size.
• It’s wide input voltage LDOs (up to 100 volts) help designers manage large transient
voltages for smart metering, smart grid, building automation and medical device
applications. With their low quiescent current (down to 1uA), they extend the designs
primary or back-up battery life. They come in robust packaging to accommodate power
dissipation and harsh environments.

14. REFERENCES
BASE PAPER: Chung-Hsun Huang, Member, IEEE, Ying-Ting Ma, and Wei-Chen Liao,
“Deaign of a Low – Voltage Low – Dropout Regulator,” IEEE J. TRANSACTIONS ON
VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , VOL. 22, NO. 6, JUNE 2014.
Y.-H. Lee, Y.-Y. Yang, K.-H. Chen, Y.-H. Lin, S.-J. Wang, K.- L. Zheng, P.-F. Chen, C.-Y.
Hsieh, Y.-Z. Ke, Y.-K. Chen, and C.-C. Huang, 2010. A DVS embedded system power
management for high efficiency integrated SoC in UWB system,” IEEE J. Solid-State
Circuits, vol. 45, no. 11, pp. 2227–2238.
M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E. SanchezSinencio, 2010. High PSR low
drop-out regulator with feed-forward ripple cancellation technique, IEEE J. Solid-State
Circuits, vol. 45, no. 3, pp. 565–577
P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, 2005. ―Area-
efficient linear regulator with ultra-fast load regulation,‖ IEEE J. Solid-State Circuits, vol. 40,
no. 4, pp. 993–940
M. Al-Shyoukh, H. Lee, and R. Perez, 2007. A transient-enhanced low- quiescent current low-
dropout regulator with buffer impedance attenuation,‖ IEEE J. Solid-State Circuits, vol. 42,
no. 8, pp. 1732–1742.

15. Y.-H. Lam and W.-H. Ki, 2008 ―A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator
with fast transient response,‖ in Proc. IEEE Int. Solid-State Circuits Conf., pp. 442–443, 626.
H.-C. Lin, H.-H. Wu, and T.-Y. Chang, 2008. An active frequency compensation scheme for
CMOS low-dropout regulators with transient response improvement,‖ IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 55, no. 9, pp. 853–857
A. Garimella, M. W. Rashid, and P. M. Furth, 2010. Reverse nested miller compensation using
current Buffers in a three-stage LDO,‖ IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 57, no. 4,
pp. 250–254
C. Chen, J. H. Wu, and Z. X. Wang, 2011. 150 mA LDO with self-adjusting frequency
compensation scheme,‖ Electron. Lett., vol. 47, no. 13, pp. 767–768.
J. Hu, B. Hu, Y. Fan, and M. Ismail, 2011 ―A 500nA quiescent, 100 mA maximum load CMOS
low-dropout regulator,‖ in Proc. IEEE Int. Conf. Electron. Circuits Syst., pp. 386–389.

16. C. Zhan and W.-H. Ki, 2011. An adaptively biased low-dropout regulator with transient
enhancement,‖ in Proc. Asia South Pacific Design Autom. Conf., pp. 117–118.
Edgar Sánchez-Sinencio, 2011. Low Drop-Out (LDO) Linear Regulators : Design
Considerations and Trends for High Power Supply Rejection (PSR),‖ IEEE Santa Clara
Valley (SCV) Solid State Circuits Society.
G. A. Rincon-Mora and P. E. Allen, 1998. A low-voltage, low quiescent current, low drop-out
regulator,‖ IEEE J. Solid-State Circuits, vol. 33, no. 1,pp. 36– 44
M. Al-Shyoukh, H. Lee, and R. Perez, 2007. A transient-enhanced low quiescent current low-
dropout regulator with buffer impedance attenuation, IEEE J. Solid-State Circuits, vol. 42,
no. 8, pp. 1732–1742.
D. D. Buss, 2002. Technology in the Internet age,‖ in Proc. IEEE Int. Solid- State Circuits
Conf. Tech. Dig. Papers, San Francisco, CA, pp. 18–21.
R. J. Milliken, J. S. Martinez, and E. S. Sinencio, 2007. Full on-chip CMOS low dropout
voltage regulator,‖ IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 54, no. 9, pp. 1879–1890.

17. E. N. Y. Ho and P. K. T. Mok, 2010. A capacitor-less CMOS active feedback low-dropout
regulator with slew-rate enhancement for portable on-chip application,‖ IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 57, no. 2,pp. 80–84.
C. Zheng and D. S. Ma, 2011. Design of monolithic CMOS LDO regulator with D2 coupling
and adaptive transmission control for adaptive wireless powered bio-implants,‖ IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 58,no. 10, pp. 2377–2387
P. Y. Or and K. N. Leung, 2010. An output-capacitor less low-dropout regulator with direct
voltage-spike detection,‖ IEEE J. Solid-State Circuits, vol. 45,no. 2, pp. 458–466.
C. Chen, J. H. Wu, and Z. X. Wang, 2011. 150mALDO with self adjusting frequency
compensation scheme,‖Electron. Lett., vol. 47,no. 13, pp. 767-768.
J. Hu, B. Hu, Y. Fan, and M. Ismail, 2011. A 500nAquiescent, 100mAmaximum load CMOS
low-dropout regulator,‖ inProc. IEEE Int. Conf.Electron. Circuits System. pp. 386–389.
C. Zhan and W.-H. Ki, 2011. An adaptively biasedlow-dropout regulatorwith transient
enhancement,‖inProc. Asia South Pacific Design Autom.Conf. pp. 117–118.

18. G. W. den Besten and B. Nauta, 1998. Embedded 5 V-to-3.3 V voltage regulator for supplying
digital IC’s in 3.3 V technology,‖ IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 956–962.
P. Hazucha, T. Karnik, Bradley A. Bloechel, IEEE, C. Parsons, D. Finan, and S. Borkar, 2005.
Area-efficient linear regulator with ultra-fast load regulation,‖ IEEE Journal of Solid-State
Circuits, vol. 40, no. 4, pp. 933-940.
K. N. Leung, P. K. T. Mok, 2003. A capacitor-free CMOS low-dropout regulator with
damping-factor-control frequency,‖ IEEE J. Solid-State Circuits, vol. 37, pp. 1691-1701.
Vishal Gupta, Gabriel Rincon-Mora, and Prasun Raha, 2004. Analysis and design of
monolithic, high PSR, linear regulators for SoC applications,‖ IEEE International System on
Chip Conference, Santa Clara, CA, pp. 311 – 315.
G. Patounakis, Y. W. Li and K. Shepard, 2004. A fully integrated on-chip DC-DC conversion
and power management system,‖ IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 443-
451.
Treacy, M.M.J.; Ebbesen, T.W.; Gibson, J.M., 1996. Exceptionally high Young's modulus
observed for individual carbon nanotubes. Nature 381(6584): 678–680. Bibcode
S. Lin, Y. B. Kim and F. Lombardi, 2010, IEEE T.10, 217.
E. Dubrova, Proc. NORCHIP Conference, 340 (1999).
S.L.Hurst, IEEE
Comput.33,1160,1984.http://dx.doi.org/10.1109/TC.1984.1676392

19. K. Navi, M. H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour and B. M abloom Nezhad,
Elsevier, Microelectronic. J. 40, 126 (2009).http://dx.doi.org/10.1016/j.mejo.2008.08.020
S. Ijiima, Nature, 354, 56 (1991). http://dx.doi.org/10.1038/354056a0 [33]P. L. McEwen,
M. Fuhrer and H. Park, IEEE T. Nanotech. 1, 78 (2002).
G. Cho, Y. B. Kim and F. Lombardi, Proc. IEEE International Instrumentation and
Measurement Technology Conference 909 (2009).
Srivastava and K. Venkatapathy, VLSI Design 4, 75 (1996)
++http://dx.doi.org/10.1155/1996/94696
Deng and H.S.P.Wong, IEEE T. Electron. Dev. 54, 31 86 (2007).
http://dx.doi.org/10.1109/TED.2007.909030
https://en.wikipedia.org/wiki/Low-dropout regulator
www.understandingnano.com LDO.html
www.pa.msu.edu/cmp/csc/ldo

20. THANK- YOU