The document discusses the concept of virtual memory. Virtual memory allows a program to access more memory than what is physically available in RAM by storing unused portions of the program on disk. When a program requests data that is not currently in RAM, it triggers a page fault that causes the needed page to be swapped from disk into RAM. This allows the illusion of more memory than physically available through swapping pages between RAM and disk as needed by the program during execution.
The document discusses the memory system in computers including main memory, cache memory, and different types of memory chips. It provides details on the following key points in 3 sentences:
The document discusses the different levels of memory hierarchy including main memory, cache memory, and auxiliary memory. It describes the basic concepts of memory including addressing schemes, memory access time, and memory cycle time. Examples of different types of memory chips are discussed such as SRAM, DRAM, ROM, and cache memory organization and mapping techniques.
This document discusses multiprocessor architecture types and limitations. It describes tightly coupled and loosely coupled multiprocessing systems. Tightly coupled systems have shared memory that all CPUs can access, while loosely coupled systems have each CPU connected through message passing without shared memory. Examples given are symmetric multiprocessing (SMP) and Beowulf clusters. Interconnection structures like common buses, multiport memory, and crossbar switches are also outlined. The advantages of multiprocessing include improved performance from parallel processing, increased reliability, and higher throughput.
The document discusses computer memory organization and the memory hierarchy. It describes different types of memory like RAM, ROM, cache memory and secondary storage. It explains the memory hierarchy as fast but expensive memory like registers and cache being used for frequently accessed data, while slower but cheaper memory like hard disks are used for long term and bulk storage. The principle of locality is discussed where programs tend to access data and instructions that are near each other in memory. Cache memory aims to improve performance by storing recently accessed data from main memory.
Cache memory is a small, high-speed memory located between the CPU and main memory. It stores copies of frequently used instructions and data from main memory in order to speed up processing. There are multiple levels of cache with L1 cache being the smallest and fastest located directly on the CPU chip. Larger cache levels like L2 and L3 are further from the CPU but can still provide faster access than main memory. The main purpose of cache is to accelerate processing speed while keeping computer costs low.
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses the input/output interface that provides communication between the CPU and I/O devices. It also describes asynchronous data transfer methods like strobe pulse and handshaking that allow synchronization between independent units transferring data asynchronously.
This document summarizes the instruction set of the 8085 microprocessor. It is classified into different types: data transfer instructions to move data, arithmetic instructions to perform operations like addition and subtraction, logical instructions for logical operations like AND and OR, branching instructions to alter program flow, and machine instructions to control the processor. Some examples of instructions are provided for each type.
The document discusses the concept of virtual memory. Virtual memory allows a program to access more memory than what is physically available in RAM by storing unused portions of the program on disk. When a program requests data that is not currently in RAM, it triggers a page fault that causes the needed page to be swapped from disk into RAM. This allows the illusion of more memory than physically available through swapping pages between RAM and disk as needed by the program during execution.
The document discusses the memory system in computers including main memory, cache memory, and different types of memory chips. It provides details on the following key points in 3 sentences:
The document discusses the different levels of memory hierarchy including main memory, cache memory, and auxiliary memory. It describes the basic concepts of memory including addressing schemes, memory access time, and memory cycle time. Examples of different types of memory chips are discussed such as SRAM, DRAM, ROM, and cache memory organization and mapping techniques.
This document discusses multiprocessor architecture types and limitations. It describes tightly coupled and loosely coupled multiprocessing systems. Tightly coupled systems have shared memory that all CPUs can access, while loosely coupled systems have each CPU connected through message passing without shared memory. Examples given are symmetric multiprocessing (SMP) and Beowulf clusters. Interconnection structures like common buses, multiport memory, and crossbar switches are also outlined. The advantages of multiprocessing include improved performance from parallel processing, increased reliability, and higher throughput.
The document discusses computer memory organization and the memory hierarchy. It describes different types of memory like RAM, ROM, cache memory and secondary storage. It explains the memory hierarchy as fast but expensive memory like registers and cache being used for frequently accessed data, while slower but cheaper memory like hard disks are used for long term and bulk storage. The principle of locality is discussed where programs tend to access data and instructions that are near each other in memory. Cache memory aims to improve performance by storing recently accessed data from main memory.
Cache memory is a small, high-speed memory located between the CPU and main memory. It stores copies of frequently used instructions and data from main memory in order to speed up processing. There are multiple levels of cache with L1 cache being the smallest and fastest located directly on the CPU chip. Larger cache levels like L2 and L3 are further from the CPU but can still provide faster access than main memory. The main purpose of cache is to accelerate processing speed while keeping computer costs low.
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses the input/output interface that provides communication between the CPU and I/O devices. It also describes asynchronous data transfer methods like strobe pulse and handshaking that allow synchronization between independent units transferring data asynchronously.
This document summarizes the instruction set of the 8085 microprocessor. It is classified into different types: data transfer instructions to move data, arithmetic instructions to perform operations like addition and subtraction, logical instructions for logical operations like AND and OR, branching instructions to alter program flow, and machine instructions to control the processor. Some examples of instructions are provided for each type.
This document discusses memory organization and virtual memory. It describes paging and segmentation as methods for virtual memory address translation. Paging divides memory and processes into equal sized pages, while segmentation divides processes into variable sized segments. Both methods use data structures like page tables to map logical addresses to physical addresses. Caching is also discussed as a way to improve memory performance by storing frequently accessed data in a small, fast memory near the CPU.
This document discusses various aspects of computer memory systems including cache memory. It begins by defining key terms related to memory such as capacity, organization, access methods, and physical characteristics. It then covers cache memory in particular, explaining the basic concept of caching as well as aspects of cache design like mapping, replacement algorithms, and write policies. Examples of cache configurations from different processor models over time are also provided.
The document discusses the instruction cycle in a computer system. The instruction cycle retrieves program instructions from memory, decodes what actions they specify, and carries out those actions. It has four main steps: 1) fetching the next instruction from memory and storing it in the instruction register, 2) decoding the encoded instruction, 3) reading the effective address for direct or indirect memory instructions, and 4) executing the instruction by passing control signals to relevant components like the ALU to perform the specified actions. The instruction cycle is the basic operational process in which a computer executes instructions.
This document provides an overview of hardware multithreading techniques including fine-grained, coarse-grained, and simultaneous multithreading. Fine-grained multithreading switches threads after every instruction to hide latency. Coarse-grained multithreading switches threads only after long stalls to avoid slowing individual threads. Simultaneous multithreading issues instructions from multiple threads each cycle to better utilize functional units.
In Harvard architecture, the CPU is connected with both the data memory (RAM) and program memory (ROM), separately. In Von-Neumann architecture, there is no separate data and program memory. Speed of execution is faster because the processor fetches data and instructions simultaneously.
This document discusses pipelining in microprocessors. It describes how pipelining works by dividing instruction processing into stages - fetch, decode, execute, memory, and write back. This allows subsequent instructions to begin processing before previous instructions have finished, improving processor efficiency. The document provides estimated timing for each stage and notes advantages like quicker execution for large programs, while disadvantages include added hardware and potential pipeline hazards disrupting smooth execution. It then gives examples of how four instructions would progress through each stage in a pipelined versus linear fashion.
The document discusses different addressing modes used in microprocessors, including the 8086. It describes five main addressing modes: immediate, register, direct, register indirect, and implicit. Immediate addressing uses data contained in the instruction itself. Register addressing uses operands in registers. Direct addressing directly specifies a memory location. Register indirect addressing uses a memory location pointed to by a register pair. Implicit addressing hides the operand in the instruction. The document provides examples of instructions that use each addressing mode.
This document discusses computer registers and their functions. It describes 8 key registers - Data Register, Address Register, Accumulator, Instruction Register, Program Counter, Temporary Register, Input Register and Output Register. It explains what each register stores and its role. For example, the Program Counter holds the address of the next instruction to be executed, while the Accumulator is used for general processing. The registers are connected via a common bus to transfer information between memory and registers for processing instructions.
The document discusses status registers and shift registers used in digital circuits. A status register contains status bits that indicate the result of arithmetic logic unit (ALU) operations, including carry (C), sign (S), zero (Z), and overflow (V) bits. The carry bit is set if there is an output carry from the ALU, the sign bit is set if the highest order bit is 1, the zero bit is set if the ALU output is all zeros, and the overflow bit is set if the result is out of the ALU's range. Shift registers are used to shift data in digital circuits.
A microprogrammed control unit stores control signals for executing instructions in a control memory rather than using dedicated logic. It has four main components: 1) a control memory that stores microinstructions specifying microoperations, 2) a control address register that selects microinstructions, 3) a sequencer that generates the next address, and 4) a pipeline register that holds the selected microinstruction. Microprograms are sequences of microinstructions that are executed to carry out machine-level instructions. Microinstructions can implement conditional branching to alter the control flow.
The document provides an introduction to computer architecture. It discusses binary numbers and the bit and byte units used to measure digital information. It describes the major components of a computer system, including the central processing unit (CPU), memory, hard drives, and input/output components. The CPU functions are explained, including fetching and executing instructions through a cycle and using registers, caches, and memory in a hierarchy. Direct access memory like RAM is faster than sequential access storage like hard disks.
Assignment on different types of addressing modesNusratJahan263
The document discusses different types of addressing modes used in computer architecture. It describes 8 types of addressing modes: register, register indirect, immediate, direct, indirect, implicit, relative, and indexed. For each type, it provides an example instruction, brief explanation of how that addressing mode works, and diagram illustrating the addressing mode. It also discusses auto-increment and auto-decrement addressing modes.
The passage discusses the importance of protecting privacy and limiting data collection in the digital age. It notes that large technology companies now collect vast amounts of personal data on users through their devices and online activities. However, unchecked data collection could threaten privacy and enable unanticipated uses of personal information that people did not consent to sharing.
This document discusses binary coded decimal (BCD) and decimal decoders. It begins by introducing the team members and then provides information about BCD, including that each decimal digit is represented by 4 bits. It describes how BCD is commonly used in electronic displays. It then discusses decimal decoders, including how they work to decode a BCD input into one of ten decimal outputs. It provides examples of 2-4 and BCD to decimal decoders. It concludes by discussing other types of decoders and how decoders can be used in logic design.
The document discusses multithreading and how it can be used to exploit thread-level parallelism (TLP) in processors designed for instruction-level parallelism (ILP). There are two main approaches for multithreading - fine-grained and coarse-grained. Fine-grained switches threads every instruction while coarse-grained switches on long stalls. Simultaneous multithreading (SMT) allows a processor to issue instructions from multiple threads in the same cycle by treating instructions from different threads as independent. This converts TLP into additional ILP to better utilize the resources of superscalar and multicore processors.
This document summarizes different types of random access memory (RAM), including static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and double data rate SDRAM (DDR SDRAM). It describes the basic operation and characteristics of each type of RAM, such as the use of transistors and capacitors, refresh requirements, packaging, and timing. Key details covered include the differences between SRAM and DRAM, DRAM refresh requirements, DRAM and SDRAM timing diagrams, and how DDR SDRAM transfers data on both clock edges.
Synchronous data transfer involves sharing a common clock between a CPU and I/O interface so that data transfer is coordinated. Asynchronous transfer has independent clocks, so handshaking methods like strobe control and handshaking are used. Strobe control uses a single strobe pulse to indicate valid data. Handshaking adds a second control signal for acknowledgment between units. This ensures the source knows data was received and the destination knows data is available.
This document provides information about a computer architecture course taught at Velammal Engineering College. The course is aimed at teaching students the basic structure and operations of a computer. It will cover topics like the ALU, pipelined execution, parallelism, memory hierarchies, and virtual memory. The course outcomes include discussing computer basics, designing an ALU, analyzing pipelining and parallel architectures, and examining memory systems. The syllabus is divided into 5 units covering basic computer structure, arithmetic, processors, parallelism, and memory/I/O systems. Textbooks and an introduction to the course are also included.
This document discusses the MIPS instruction set architecture and principles of computer architecture. It covers:
- The goals of being able to derive MIPS instruction code from assembler code and assembler code from C code.
- An introduction to the MIPS instruction set architecture, which has instructions with 3 operands and performs one operation at a time.
- Four important design principles for instruction set architecture: simplicity favors regularity, smaller is faster, good design demands good compromise, and make the common case fast.
- Details of the MIPS instruction set such as registers, memory organization, and use of load and store instructions to transfer data between registers and memory.
This document discusses memory organization and virtual memory. It describes paging and segmentation as methods for virtual memory address translation. Paging divides memory and processes into equal sized pages, while segmentation divides processes into variable sized segments. Both methods use data structures like page tables to map logical addresses to physical addresses. Caching is also discussed as a way to improve memory performance by storing frequently accessed data in a small, fast memory near the CPU.
This document discusses various aspects of computer memory systems including cache memory. It begins by defining key terms related to memory such as capacity, organization, access methods, and physical characteristics. It then covers cache memory in particular, explaining the basic concept of caching as well as aspects of cache design like mapping, replacement algorithms, and write policies. Examples of cache configurations from different processor models over time are also provided.
The document discusses the instruction cycle in a computer system. The instruction cycle retrieves program instructions from memory, decodes what actions they specify, and carries out those actions. It has four main steps: 1) fetching the next instruction from memory and storing it in the instruction register, 2) decoding the encoded instruction, 3) reading the effective address for direct or indirect memory instructions, and 4) executing the instruction by passing control signals to relevant components like the ALU to perform the specified actions. The instruction cycle is the basic operational process in which a computer executes instructions.
This document provides an overview of hardware multithreading techniques including fine-grained, coarse-grained, and simultaneous multithreading. Fine-grained multithreading switches threads after every instruction to hide latency. Coarse-grained multithreading switches threads only after long stalls to avoid slowing individual threads. Simultaneous multithreading issues instructions from multiple threads each cycle to better utilize functional units.
In Harvard architecture, the CPU is connected with both the data memory (RAM) and program memory (ROM), separately. In Von-Neumann architecture, there is no separate data and program memory. Speed of execution is faster because the processor fetches data and instructions simultaneously.
This document discusses pipelining in microprocessors. It describes how pipelining works by dividing instruction processing into stages - fetch, decode, execute, memory, and write back. This allows subsequent instructions to begin processing before previous instructions have finished, improving processor efficiency. The document provides estimated timing for each stage and notes advantages like quicker execution for large programs, while disadvantages include added hardware and potential pipeline hazards disrupting smooth execution. It then gives examples of how four instructions would progress through each stage in a pipelined versus linear fashion.
The document discusses different addressing modes used in microprocessors, including the 8086. It describes five main addressing modes: immediate, register, direct, register indirect, and implicit. Immediate addressing uses data contained in the instruction itself. Register addressing uses operands in registers. Direct addressing directly specifies a memory location. Register indirect addressing uses a memory location pointed to by a register pair. Implicit addressing hides the operand in the instruction. The document provides examples of instructions that use each addressing mode.
This document discusses computer registers and their functions. It describes 8 key registers - Data Register, Address Register, Accumulator, Instruction Register, Program Counter, Temporary Register, Input Register and Output Register. It explains what each register stores and its role. For example, the Program Counter holds the address of the next instruction to be executed, while the Accumulator is used for general processing. The registers are connected via a common bus to transfer information between memory and registers for processing instructions.
The document discusses status registers and shift registers used in digital circuits. A status register contains status bits that indicate the result of arithmetic logic unit (ALU) operations, including carry (C), sign (S), zero (Z), and overflow (V) bits. The carry bit is set if there is an output carry from the ALU, the sign bit is set if the highest order bit is 1, the zero bit is set if the ALU output is all zeros, and the overflow bit is set if the result is out of the ALU's range. Shift registers are used to shift data in digital circuits.
A microprogrammed control unit stores control signals for executing instructions in a control memory rather than using dedicated logic. It has four main components: 1) a control memory that stores microinstructions specifying microoperations, 2) a control address register that selects microinstructions, 3) a sequencer that generates the next address, and 4) a pipeline register that holds the selected microinstruction. Microprograms are sequences of microinstructions that are executed to carry out machine-level instructions. Microinstructions can implement conditional branching to alter the control flow.
The document provides an introduction to computer architecture. It discusses binary numbers and the bit and byte units used to measure digital information. It describes the major components of a computer system, including the central processing unit (CPU), memory, hard drives, and input/output components. The CPU functions are explained, including fetching and executing instructions through a cycle and using registers, caches, and memory in a hierarchy. Direct access memory like RAM is faster than sequential access storage like hard disks.
Assignment on different types of addressing modesNusratJahan263
The document discusses different types of addressing modes used in computer architecture. It describes 8 types of addressing modes: register, register indirect, immediate, direct, indirect, implicit, relative, and indexed. For each type, it provides an example instruction, brief explanation of how that addressing mode works, and diagram illustrating the addressing mode. It also discusses auto-increment and auto-decrement addressing modes.
The passage discusses the importance of protecting privacy and limiting data collection in the digital age. It notes that large technology companies now collect vast amounts of personal data on users through their devices and online activities. However, unchecked data collection could threaten privacy and enable unanticipated uses of personal information that people did not consent to sharing.
This document discusses binary coded decimal (BCD) and decimal decoders. It begins by introducing the team members and then provides information about BCD, including that each decimal digit is represented by 4 bits. It describes how BCD is commonly used in electronic displays. It then discusses decimal decoders, including how they work to decode a BCD input into one of ten decimal outputs. It provides examples of 2-4 and BCD to decimal decoders. It concludes by discussing other types of decoders and how decoders can be used in logic design.
The document discusses multithreading and how it can be used to exploit thread-level parallelism (TLP) in processors designed for instruction-level parallelism (ILP). There are two main approaches for multithreading - fine-grained and coarse-grained. Fine-grained switches threads every instruction while coarse-grained switches on long stalls. Simultaneous multithreading (SMT) allows a processor to issue instructions from multiple threads in the same cycle by treating instructions from different threads as independent. This converts TLP into additional ILP to better utilize the resources of superscalar and multicore processors.
This document summarizes different types of random access memory (RAM), including static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and double data rate SDRAM (DDR SDRAM). It describes the basic operation and characteristics of each type of RAM, such as the use of transistors and capacitors, refresh requirements, packaging, and timing. Key details covered include the differences between SRAM and DRAM, DRAM refresh requirements, DRAM and SDRAM timing diagrams, and how DDR SDRAM transfers data on both clock edges.
Synchronous data transfer involves sharing a common clock between a CPU and I/O interface so that data transfer is coordinated. Asynchronous transfer has independent clocks, so handshaking methods like strobe control and handshaking are used. Strobe control uses a single strobe pulse to indicate valid data. Handshaking adds a second control signal for acknowledgment between units. This ensures the source knows data was received and the destination knows data is available.
This document provides information about a computer architecture course taught at Velammal Engineering College. The course is aimed at teaching students the basic structure and operations of a computer. It will cover topics like the ALU, pipelined execution, parallelism, memory hierarchies, and virtual memory. The course outcomes include discussing computer basics, designing an ALU, analyzing pipelining and parallel architectures, and examining memory systems. The syllabus is divided into 5 units covering basic computer structure, arithmetic, processors, parallelism, and memory/I/O systems. Textbooks and an introduction to the course are also included.
This document discusses the MIPS instruction set architecture and principles of computer architecture. It covers:
- The goals of being able to derive MIPS instruction code from assembler code and assembler code from C code.
- An introduction to the MIPS instruction set architecture, which has instructions with 3 operands and performs one operation at a time.
- Four important design principles for instruction set architecture: simplicity favors regularity, smaller is faster, good design demands good compromise, and make the common case fast.
- Details of the MIPS instruction set such as registers, memory organization, and use of load and store instructions to transfer data between registers and memory.
The document discusses assembly languages and the MIPS instruction set architecture. It introduces key concepts of assembly language such as registers, memory addressing, and instructions. It describes the MIPS instruction format, which uses three operands of destination, source1, and source2. The document outlines the basic MIPS instructions for arithmetic, data transfer, and control flow. It explains how assembly code maps to low-level machine instructions and hardware.
This document provides information on the course EC8552 Computer Architecture and Organization. The objectives of the course are to understand MIPS instruction set architecture, arithmetic and logic units, data and control paths, memory and I/O organization, and parallel processing architectures. The outcomes are that students will be able to analyze computer system performance, illustrate arithmetic operations, describe pipelining and hazards, explain memory and I/O, and interpret parallel architectures. Assessments include tests, quizzes, assignments, and tutorials. The course will use an online Canvas platform.
An advanced processor is a type of microprocessor that is designed to handle complex tasks and perform calculations at a high speed. These processors are typically used in high-performance computing applications, such as scientific research, artificial intelligence, and data analysis. They often have multiple cores and advanced instruction sets that allow them to process large amounts of data quickly and efficiently. Some examples of advanced processors include Intel's Core i9 and AMD's Ryzen Threadripper
The document discusses various types of computers and their characteristics. It begins by classifying computers based on speed, cost, computational power, and application. It then describes different types of computers like desktop computers, notebook computers, workstations, mainframe systems, server systems, and supercomputers. It also defines basic computer terminology and concepts like hardware, software, memory, storage, inputs, outputs, and processing. The document further explains functional units of a computer like CPU, memory, and bus structure. It concludes with discussing instruction execution, instruction formats, and branching in computer programs.
This document provides an overview of MIPS machine language instructions. It describes the key components of MIPS instructions, including register operands, immediate operands, and different instruction formats. It explains basic arithmetic, load/store, branch, and jump instructions. It also discusses MIPS register organization, memory organization including byte ordering, the fetch-execute cycle, and MIPS addressing modes including register, word-relative, and PC-relative addressing. The document is serving as a lecture on MIPS instruction set architecture for a computer organization and architecture course.
This document discusses the differences between RISC and CISC instruction set architectures. RISC uses simple, fixed-length instructions that can execute in one cycle, while CISC uses more complex, variable-length instructions that may take multiple cycles. Key differences include RISC having fewer instructions, registers, and addressing modes compared to CISC, which aims to support high-level languages with a wider range of instructions. Branching, condition codes, and instruction formats are also covered.
FLPU = Floating Points operations Unit
PFCU = Prefetch control unit
AOU = Atomic Operations Unit
Memory-Management unit (MMU)
MAR (memory address register)
MDR (memory data register)
BIU (Bus Interface Unit)
ARS (Application Register Set)
FRS File Register Set
(SRS) single register set
Layers of Computer Science, ISA and uArch Alexander Titov 20 September 2014.li50916ku
This document describes the different layers of abstraction in computer architecture from the application layer down to the physics layer. It focuses on the instruction set architecture (ISA) and microarchitecture layers. The ISA defines the machine language and hardware structures available to programmers. The microarchitecture defines the detailed implementation of hardware structures and operations not visible to programmers. The document uses MIPS as an example ISA and explains key ISA concepts like data formats, memory addressing, registers, and common instruction types.
The document provides information about an upcoming prelim exam for CS 3410 at Cornell University. It states that the prelim will take place on the same day as the summary at 7:30pm sharp in various locations based on student ID. It covers material from chapters 1-4, homework assignments 1 and 2, and labs 0-2. Students should arrive early as the exam will start promptly.
MCA-I-COA- overview of register transfer, micro operations and basic computer...Rai University
This document provides an overview of register transfer, micro operations, and basic computer organization and design. It discusses the key concepts of a stored program, instructions, and how instructions are executed through an instruction cycle that involves fetching, decoding, and executing instructions via a sequence of microoperations controlled by a sequence counter register. It also describes the register architecture and instruction set of the Mano computer model, which uses a basic set of registers and a hierarchical 1+3 bit instruction format to support 25 instructions for arithmetic, logic, data movement, program control, and I/O operations.
The document discusses instruction set architecture (ISA), which defines the interface between software and hardware. It describes ISA as specifying storage locations, operations, and how to invoke and access them. The document then compares ISA to human language and discusses program compilation. It outlines the basic instruction execution model of fetching, decoding, executing and writing instructions. The document also describes different types of instruction sets like stack, accumulator and register-set architectures. Finally, it contrasts complex instruction set computers (CISC) with reduced instruction set computers (RISC).
4.1 Introduction 145• In this section, we first take a gander at a.pdfarpowersarps
4.1 Introduction 145
• In this section, we first take a gander at an exceptionally straightforward PC called MARIE: A
Machine
Design that is Really Intuitive and Easy.
• We then give brief reviews of Intel and MIPS machines, two prevalent
models mirroring the CISC (Complex Instruction Set Computer) and RISC
(Diminished Instruction Set Computer) outline theories.
• The goal of this part is to give you a comprehension of how a PC
capacities.
4.1.1 CPU Basics and Organization 145
• The Central handling unit (CPU) is in charge of bringing system guidelines,
translating every direction that is brought, and executing the demonstrated succession of
operations on the right information.
• The two key parts of the CPU are the datapath and the control unit.
• The datapath comprises of a number juggling rationale unit (ALU) and capacity units
(registers)
that are interconnected by an information transport that is likewise associated with principle
memory. Check
page 29 Figure 1.4.
• Various CPU segments perform sequenced operations as indicated by signs
given by its control unit.
• Registers hold information that can be promptly gotten to by the CPU.
• They can be executed utilizing D flip-flops. A 32-bit register requires 32 D flip-flops.
• The number juggling rationale unit (ALU) completes intelligent and math operations as
coordinated by the control unit.
• The control unit figures out which activities to do as per the qualities in a
program counter enroll and a status register.
CMPS375 Class Notes Page 3/22 by Kuo-pao Yang
4.1.2 The Bus 147
• The CPU offers information with other framework segments by method for an information
transport.
• A transport is an arrangement of wires that all the while pass on a solitary piece along every
line.
• Two sorts of transports are normally found in PC frameworks: point-to-point, and
multipoint transports.
FIGURE 4.1 (a) Point-to-Point Busses; (b) A Multipoint Bus
• At any one time, stand out gadget (be it a register, the ALU, memory, or some other
segment) may utilize the transport.
• However, the sharing regularly brings about a correspondences bottleneck.
CMPS375 Class Notes Page 4/22 by Kuo-pao Yang
• Master gadget is one that starts activities and a slave reacts to demands by a
expert.
• Busses comprise of information lines, control lines, and address lines.
• While the information lines pass on bits starting with one gadget then onto the next, control
lines decide
the bearing of information stream, and when every gadget can get to the transport.
• Address lines decide the area of the source or goal of the information.
FIGURE 4.2 The Components of a Typical Bus
• In an expert slave design, where more than one gadget can be the transport expert,
simultaneous transport expert solicitations must be refereed.
• Four classifications of transport mediation are:
o Daisy chain: Permissions are passed from the most noteworthy need gadget to the
most reduced.
o Centralized parallel: Each gadget is straightforwardly ass.
Various processor architectures are described in this presentation. It could be useful for people working for h/w selection and processor identification.
This document provides an overview of computer architecture and programming design. It discusses early computing technologies including the abacus and Pascal's mechanical calculator. It also describes Charles Babbage's Difference Engine and Analytic Engine, and George Boole's work on Boolean algebra. The document outlines the Von Neumann architecture and its basic operations. It defines key components of computer systems like the processor, memory, I/O devices, and buses. It also discusses memory types, logic design, embedded systems, and software design methodology.
The document discusses computer architecture and describes the basic components of a computer. It discusses the instruction cycle which involves fetching instructions from memory, decoding them, reading the effective address from memory, and executing the instruction. The basic computer has three types of instructions - memory reference, register reference, and input/output. Memory reference instructions refer to memory addresses and use direct or indirect addressing. Register reference instructions perform operations on registers. Input/output instructions are used for communication with external devices. The instruction cycle is then completed by fetching and executing the next instruction.
The document discusses instruction set architecture (ISA), describing it as the interface between software and hardware that defines the programming model and machine language instructions. It provides details on RISC ISAs like MIPS and how they aim to have simpler instructions, more registers, load/store architectures, and pipelining to improve performance compared to CISC ISAs. The document also discusses different types of ISA designs including stack-based, accumulator-based, and register-to-register architectures.
Similar to Basic Structure of a Computer System (20)
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...University of Maribor
Slides from talk presenting:
Aleš Zamuda: Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapter and Networking.
Presentation at IcETRAN 2024 session:
"Inter-Society Networking Panel GRSS/MTT-S/CIS
Panel Session: Promoting Connection and Cooperation"
IEEE Slovenia GRSS
IEEE Serbia and Montenegro MTT-S
IEEE Slovenia CIS
11TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTING ENGINEERING
3-6 June 2024, Niš, Serbia
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEMHODECEDSIET
Time Division Multiplexing (TDM) is a method of transmitting multiple signals over a single communication channel by dividing the signal into many segments, each having a very short duration of time. These time slots are then allocated to different data streams, allowing multiple signals to share the same transmission medium efficiently. TDM is widely used in telecommunications and data communication systems.
### How TDM Works
1. **Time Slots Allocation**: The core principle of TDM is to assign distinct time slots to each signal. During each time slot, the respective signal is transmitted, and then the process repeats cyclically. For example, if there are four signals to be transmitted, the TDM cycle will divide time into four slots, each assigned to one signal.
2. **Synchronization**: Synchronization is crucial in TDM systems to ensure that the signals are correctly aligned with their respective time slots. Both the transmitter and receiver must be synchronized to avoid any overlap or loss of data. This synchronization is typically maintained by a clock signal that ensures time slots are accurately aligned.
3. **Frame Structure**: TDM data is organized into frames, where each frame consists of a set of time slots. Each frame is repeated at regular intervals, ensuring continuous transmission of data streams. The frame structure helps in managing the data streams and maintaining the synchronization between the transmitter and receiver.
4. **Multiplexer and Demultiplexer**: At the transmitting end, a multiplexer combines multiple input signals into a single composite signal by assigning each signal to a specific time slot. At the receiving end, a demultiplexer separates the composite signal back into individual signals based on their respective time slots.
### Types of TDM
1. **Synchronous TDM**: In synchronous TDM, time slots are pre-assigned to each signal, regardless of whether the signal has data to transmit or not. This can lead to inefficiencies if some time slots remain empty due to the absence of data.
2. **Asynchronous TDM (or Statistical TDM)**: Asynchronous TDM addresses the inefficiencies of synchronous TDM by allocating time slots dynamically based on the presence of data. Time slots are assigned only when there is data to transmit, which optimizes the use of the communication channel.
### Applications of TDM
- **Telecommunications**: TDM is extensively used in telecommunication systems, such as in T1 and E1 lines, where multiple telephone calls are transmitted over a single line by assigning each call to a specific time slot.
- **Digital Audio and Video Broadcasting**: TDM is used in broadcasting systems to transmit multiple audio or video streams over a single channel, ensuring efficient use of bandwidth.
- **Computer Networks**: TDM is used in network protocols and systems to manage the transmission of data from multiple sources over a single network medium.
### Advantages of TDM
- **Efficient Use of Bandwidth**: TDM all
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
1. Velammal Engineering College
Department of Computer Science
and Engineering
Welcome…
Slide Sources: Patterson & Hennessy COD book
website (copyright Morgan Kaufmann) adapted
and supplemented
Mr. A. Arockia Abins &
Ms. R. Amirthavalli,
Asst. Prof,
CSE,
Velammal Engineering College
2. Course Objectives
• This course aims to learn the basic structure and operations of
a computer.
• The course is intended to learn ALU, pipelined execution,
parallelism and multi-core processors.
• The course will enable the students to understand memory
hierarchies, cache memories and virtual memories.
3. Course Outcomes
CO 1
Discuss the basics structure of computers, operations and
instructions.
CO 2 Design arithmetic and logic unit.
CO 3 Analyze pipelined execution and design control unit.
CO 4 Analyze parallel processing architectures.
CO 5 Examine the performance of various memory systems
CO 6 Organize the various I/O communications.
4. Syllabus
Unit Titles:
• Unit I Basic Structure of a Computer System
• Unit II Arithmetic for Computers
• Unit III Processor and Control Unit
• Unit IV Parallelism
• Unit V Memory & I/O Systems
5. Syllabus – Unit I
UNIT-I BASIC STRUCTURE OF A COMPUTER
SYSTEM
Functional Units – Basic operational concepts –– Instructions:
Operations, Operands – Instruction representation – Instruction
Types – MIPS addressing, Performance
6. Syllabus – Unit II
UNIT-II ARITHMETIC FOR COMPUTERS
Addition and Subtraction – Multiplication – Division – Floating
Point Representation – Floating Point Addition and Subtraction.
7. Syllabus – Unit III
UNIT-III PROCESSOR AND CONTROL UNIT
A Basic MIPS implementation – Building a Datapath – Control
Implementation Scheme – Pipelining – Pipelined datapath and
control – Handling Data Hazards & Control Hazards.
8. Syllabus – Unit IV
UNIT-IV PARALLELISM
Introduction to Multicore processors and other shared memory
multiprocessors – Flynn’s classification: SISD, MIMD, SIMD,
SPMD and Vector – Hardware multithreading – GPU
architecture.
9. Syllabus – Unit V
• UNIT-V MEMORY & I/O SYSTEMS
Memory Hierarchy – memory technologies – Cache Memory –
Performance Considerations, Virtual Memory,TLB’s – Accessing
I/O devices – Interrupts – Direct Memory Access – Bus Structure
– Bus operation.
10. Text Books
• Book 1:
o Name: Computer Organization and Design: The
Hardware/Software Interface
o Authors: David A. Patterson and John L. Hennessy
o Publisher: Morgan Kaufmann / Elsevier
o Edition: Fifth Edition, 2014
• Book 2:
o Name: Computer Organization and Embedded Systems
Interface
o Authors: Carl Hamacher, Zvonko Vranesic, Safwat Zaky and
Naraig Manjikian
o Publisher: Tata McGraw Hill
o Edition: Sixth Edition, 2012
11. Introduction
• What is mean by Computer Architecture?
Hardware parts
Instruction set
Interface between hardware &
software
13. Instruction Set Architecture
(ISA)
ISA: The interface or contact between the hardware and
the software
Rules about how to code and interpret machine
instructions:
Execution model (program counter)
Operations (instructions)
Data formats (sizes, addressing modes)
Processor state (registers)
Input and Output (memory, etc.)
14. Introduction
• What is meant by Computer
Architecture?
Computer architecture encompasses
the specification of an instruction set
and the functional behavior of the
hardware units that implement the
instructions.
28. Connection between the processor and the main
memory Code Snippet:
Load R2, LOC
Add R4, R3, R2
Store LOC, R4
29. IR & PC
• Instruction Register:
The instruction register (IR) holds the
instruction that is currently being executed.
• Program Counter:
The program counter (PC) contains the
memory address of the next instruction to be
fetched and executed.
35. Machine vs Assembly
Language
Machine Language Assembly Language
• A particular set of
instructions that the
CPU can directly
execute – but these
are ones and zeros
• Ex:
0100001010101
• Assembly language
is a symbolic
version of the
equivalent machine
language
• Ex:
add a,b
36.
37. Instructions
• Instruction Set:
o The vocabulary of commands understand by a
given architecture.
• Some ISA:
o ARM
o Intel x86
o IBM Power
o MIPS
o SPARC
• Different CPUs implement different set of
instructions.
38. MIPS
MIPS - Microprocessor with Interlocked Pipeline Stages
Features:
• five-stage execution pipeline: fetch, decode, execute,
memory-access, write-result
• regular instruction set, all instructions are 32-bit
• three-operand arithmetical and logical instructions
• 32 general-purpose registers of 32-bits each
• only the load and store instruction access memory
• flat address space of 4 GBytes of main memory (2^32
bytes)
39. MIPS Assembly Language
• Categories:
oArithmetic – Only processor and registers
involved (sum of two registers)
oData transfer – Interacts with memory
(load and store)
oLogical - Only processor and registers
involved (and, sll)
oConditional branch – Change flow of
execution (branch instructions)
oUnconditional Jump – Change flow of
execution (jump to a subroutine)
43. Load & Store Instructions
• Load:
o Transfer data from memory to a register
• Store:
o Transfer a data from a register to memory
• Memory address must be specified by
load and store
•
Processor Memory
STORE
LOAD
48. MIPS Arithmetic
• All MIPS arithmetic instructions have 3 operands
• Operand order is fixed (e.g., destination first)
• Example:
C code: A = B + C
MIPS code: add $s0, $s1, $s2
compiler’s job to associate
variables with registers
49. MIPS Arithmetic
• Design Principle 1: simplicity favors regularity.
Translation: Regular instructions make for simple hardware!
• Simpler hardware reduces design time and manufacturing cost.
• Of course this complicates some things...
C code: A = B + C + D;
E = F - A;
MIPS code add $t0, $s1, $s2
(arithmetic): add $s0, $t0, $s3
sub $s4, $s5, $s0
• Performance penalty: high-level code translates to denser machine
code.
Allowing variable number
of operands would
simplify the assembly
code but complicate the
hardware.
50. MIPS Arithmetic
a b c f g h i j
$ s 0 $ s 1 $ s 2 $ s 3 $ s 4 $ s 5 $ s 6
$ s 7
a = b - c ;
f = ( g + h ) – ( i + j ) ;
s u b $ s 0 , $ s 1 , $ s 2
a d d $ t 0 , $ s 4 , $ s 5
a d d $ t 1 , $ s 6 , $ s 7
s u b $ s 3 , $ t 0 , $ t 1
1 9 / 6 7
T r y :
1 . f = g + ( h – 5 )
2 . f = ( i + j ) – ( k – 2 0 )
51. Registers vs. Memory
• Arithmetic instructions operands must be in registers
o MIPS has 32 registers
• Compiler associates variables with registers
• What about programs with lots of variables (arrays, etc.)? Use
memory, load/store operations to transfer data from memory to
register – if not enough registers spill registers to memory
• MIPS is a load/store architecture
Processor I/O
Control
Datapath
Memory
Input
Output
52. Memory Organization
• Viewed as a large single-dimension array with access by
address
• A memory address is an index into the memory array
• Byte addressing means that the index points to a byte of
memory, and that the unit of memory accessed by a load/store
is a byte
0
1
2
3
4
5
6
...
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
53. Memory Organization
• Bytes are load/store units, but most data items use larger words
• For MIPS, a word is 32 bits or 4 bytes.
• 232 bytes with byte addresses from 0 to 232-1
• 230 words with byte addresses 0, 4, 8, ... 232-4
o i.e., words are aligned
o what are the least 2 significant bits of a word address?
0
4
8
12
...
32 bits of data
32 bits of data
32 bits of data
32 bits of data
Registers correspondingly hold 32 bits of data
54. The Endian Question
Big Endian
31 0
MIPS can also load and
store 4-byte words and
2-byte halfwords.
The endian question:
when you read a word, in
what order do the bytes
appear?
Little Endian: Intel, DEC,
et al.
Big Endian: Motorola,
IBM, Sun, et al.
MIPS can do either
SPIM adopts its host’s
convention
by te 0 by te 1 by te 2 by te 3
Little Endian
31 0
by te 3 by te 2 by te 1 by te 0
3 2 / 6 7
56. Load/Store Instructions
• Load and store instructions
• Example:
C code: A[8] = h + A[8];
MIPS code (load): lw $t0, 32($s3)
(arithmetic): add $t0, $s2, $t0
(store): sw $t0, 32($s3)
• Load word has destination first, store has destination last
• Remember MIPS arithmetic operands are registers, not memory
locations
o therefore, words must first be moved from memory to registers using
loads before they can be operated on; then result can be stored back to
memory
offset address
value
57. So far we’ve learned:
• MIPS
o loading words but addressing bytes
o arithmetic on registers only
• Instruction Meaning
add $s1, $s2, $s3 $s1 = $s2 + $s3
sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100]= $s1
• Try:Find the assembly code of B[8]=A[i]+A[j];
A and B available in $s6 and $s7 respectively
$so-$s5 consists of the values f-j
58. Exercise
Q: For the following C statement, what is the corresponding
MIPS assembly code? Assume that the variables f, g, h,
and i are given and could be considered 32-bit integers as
declared in a C program. Use a minimal number of MIPS
assembly instructions. f = g + (h − 5);
Solution:
f -> $s1, g -> $s2, h -> $s3
addi $t0, $s3,-5
add $s1, $s2, $t0
59. Representing Instructions
in the Computer
• Instruction format:
o A form of representation of an instruction
composed of fields of binary numbers.
• All MIPS instructions are 32 bit long.
• Three types of instruction formats:
o R-type (for register) or R-format
o I-type (for immediate) or I-format
o J-type (for jump) or J-format
60. R-type (for register)
• MIPS fields:
• op: Basic operation of the instruction (opcode)
• rs: The first register source operand
• rt: The second register source operand
• rd: The register destination operand
• shamt: Shift amount
• funt: Function. It selects the specific variant of the
operation in the op filed. (function code)
Ex: add $t0, $s1, $s2
61. I-type (for immediate)
• MIPS fields:
• op: Basic operation of the instruction (opcode)
• rs: The register source operand
• rt: destination register, which receives the result of the
load
• constant or address: It contains 16 bit constant or
address value.
68. Translating a MIPS Assembly
Instruction into a Machine Instruction
Given instruction: add $t0,$s1,$s2
• Solution:
• Identify the type instruction format: R-type
• Format: Operation rd, rs, rt
• rs -> $s1, rt -> $s2, rd -> $t0, shamt – NA
• Op -> , funct ->
• Decimal representation:
• Binary representation:
op rs rt rd shamt funct
0 17 18 8 0 32
op rs rt rd shamt funct
000000 10001 10010 01000 00000 100000
69. Exercise
Q: Translate the following MIPS Assembly code
into binary code.
sub $t3,$s4,$s5
op rs rt rd Shamt Funct
0 20 21 11 0 34
000000 10100 10101 01011 00000 100010
70. Exercise
Q: Translate the following MIPS Assembly code
into binary code.
sub $t3,$s4,$s5
000000 10100 10101 01011 00000 100010
71. Translating a MIPS Assembly
Instruction into a Machine Instruction
Given instruction: lw $t0,32($s3)
• Solution:
• Identify the type instruction format: I-type
• Format: Operation rt, addr.(rs)
• rs -> $s3, rt -> $to, immediate -> 32
• Decimal representation:
• Binary representation:
op rs rt address
35 19 8 32
op rs rt
100011 10011 01000 0000 0000 0010 0000
72. Exercise
Q: Translate the following MIPS Assembly code
into binary code.
sw $t2,58($s5)
101011 10101 01010 0000 0000 0011 1010
73. Translating High level Language
into Machine Language
Q: Consider the following high level statement
A[300] = h + A[300];
If $t1 has the base of the array A and $s2 corresponds to
h, What is the MIPS machine language code?
81. Instructions for Making
Decisions
• Sequences that allow programs to execute statements in order
one after another.
• Branches that allow programs to jump to other points in a
program.
• Loops that allow a program to execute a fragment of code
multiple times.
• MIPS Instructions:
beq register1, register2, L1
bne register1, register2, L1
• beq and bne are mnemonics
• Conditional branches
82. Instructions for Making
Decisions
Q: In the following code segment, f, g, h, i, and j are
variables. If the five variables f through j correspond to the
five registers $s0 through $s4, what is the compiled MIPS
code for this C if statement?
if (i == j) f = g + h; else f = g - h;
84. Instructions for Making
Decisions
High level code:
if (i == j)
f = g + h;
else
f = g - h;
MIPS code:
bne $s3,$s4,Else # go to Else if i ≠ j
add $s0,$s1,$s2 # f = g + h (skipped if i ≠ j)
j Exit # go to Exit
Else: sub $s0,$s1,$s2 # f = g - h (skipped if i = j)
Exit:
85. Compiling a while Loop
in C
while (save[i] == k)
i += 1;
Assume that i and k correspond to registers $s3 and $s5
and the base of the array save is in $s6. What is the MIPS
assembly code corresponding to this C segment?
86. Compiling a while Loop
in C
while (save[i] == k)
i += 1;
1. load save[i] into a temporary register
1. add i to the base of array save to form the address
2. performs the loop test
1. go to Exit if save[i] ≠ k
3. adds 1 to I
4. back to the while test at the top of the loop
5. Exit
87. while (save[i] == k)
i += 1;
Assume that i and k correspond to registers $s3 and $s5
and the base of the array save is in $s6. What is the MIPS
assembly code corresponding to this C segment?
Solution:
Loop: sll $t1,$s3,2 # Temp reg $t1 = i * 4
add $t1,$t1,$s6 # $t1 = address of save[i]
lw $t0,0($t1) # Temp reg $t0 = save[i]
bne $t0,$s5, Exit # go to Exit if save[i] ≠ k
addi $s3,$s3,1 # i = i + 1
j Loop # go to Loop
Exit:
88. MIPS Addressing Mode
• The different ways for specifying the locations
of instruction operands are known as
addressing mode.
• The MIPS addressing modes are the following:
1. Immediate addressing mode
2. Register addressing mode
3. Base or displacement addressing mode
4. PC-relative addressing mode
5. Pseudodirect addressing mode
89. Immediate addressing mode
• Def:
o the operand is a constant within the instruction itself
• Ex:
o addi $s1, $s2, 20 #$s1=$s2+20
• Ilustration:
90. Register addressing mode
• Def:
o source and destination operands are registers which are
available in processor registers.
o Direct addressing mode
• Ex:
o add $s1, $s2, $s3 #$s1=$s2+$s3
• Ilustration:
91. Base or displacement
addressing mode
• Def:
o the operand is at the memory location whose address is the
sum of a register and a constant in the instruction
o Indirect addressing mode
• Ex:
o lw $s1, 20 ($s3) #$s1= Memory[$s3+20]
• Ilustration:
92. PC-relative addressing mode
• Def:
o the branch address is the sum of the PC and a constant in
the instruction
• Ex:
o bne $s4, $s5, 25 # if ($s4 != $s5), go to
pc=12+4+100
• Ilustration:
93. Pseudodirect addressing
mode
• Def:
o the jump address is the 26 bits of the instruction
concatenated with the upper bits of the PC
• Ex:
o j 1000
• Ilustration:
94. Decoding Machine Code
• Q: What is the assembly language statement
corresponding to this machine instruction?
00af8020hex
Solution:
converting hexadecimal to binary
Binary instruction format
Assembly instruction
95. Translating Machine Language
to Assembly Language
• Translate the following machine language code into
assembly language.
0x02F34022
96. Performance
• Performance is the key to understanding underlying motivation for
the hardware and its organization
• Measure, report, and summarize performance to enable users to
o make intelligent choices
o see through the marketing hype!
• Why is some hardware better than others for different programs?
• What factors of system performance are hardware related?
(e.g., do we need a new machine, or a new operating system?)
• How does the machine's instruction set affect performance?
97. Computer Performance:
TIME, TIME, TIME!!!
• Response Time (elapsed time, latency):
o how long does it take for my job to run?
o how long does it take to execute (start to
finish) my job?
o how long must I wait for the database query?
• Throughput:
o how many jobs can the machine run at once?
o what is the average execution rate?
o how much work is getting done?
• If we upgrade a machine with a new processor what do we increase?
• If we add a new machine to the lab what do we increase?
Individual user
concerns…
Systems manager
concerns…
98. Execution Time
• Elapsed Time
o counts everything (disk and memory accesses, waiting for I/O, running
other programs, etc.) from start to finish
o a useful number, but often not good for comparison purposes
elapsed time = CPU time + wait time (I/O, other programs, etc.)
• CPU time
o doesn't count waiting for I/O or time spent running other programs
o can be divided into user CPU time and system CPU time (OS calls)
CPU time = user CPU time + system CPU time
elapsed time = user CPU time + system CPU time + wait time
• Our focus: user CPU time (CPU execution time or, simply, execution
time)
o time spent executing the lines of code that are in our program
99. Definition of Performance
• For some program running on machine X:
PerformanceX = 1 / Execution timeX
• If there are two machines X and Y if the performance of X is greater than performance of
Y,
PerformanceX > PerformanceY
ie., 1 / Execution timeX > 1 / Execution timeY
• X is n times faster than Y means:
PerformanceX / PerformanceY = n
PerformanceX / PerformanceY = Execution timeY / Execution timeX = n
100. Q: If computer A runs a program in 10 sec
and computer B runs the same program in
15 secs, how much faster is A than B
• We know that,
PerformanceA / PerformanceB
= Execution timeB / Execution timeA = n
Thus the performance ratio is,
Execution timeB / Execution timeA = 15 / 10 = 1.5
ie., PerformanceA / PerformanceB = 1.5
Therfore Peformance of A 1.5 times faster than Performance
of B
101. Clock Cycles
• Instead of reporting execution time in seconds, we often use cycles.
In modern computers hardware events progress cycle by cycle: in
other words, each event, e.g., multiplication, addition, etc., is a
sequence of cycles
• Clock ticks indicate start and end of cycles:
• cycle time = time between ticks = seconds per cycle
• clock rate (frequency) = clock cycles per second (1 Hz. = 1
cycle/sec, 1 MHz. = 106 cycles/sec)
• Example: A 200 Mhz. clock has a cycle time of ????
time
seconds
program
cycles
program
seconds
cycle
cycle
tick
tick
102. Performance Equation I
• So, to improve performance one can either:
o reduce the number of cycles for a program, or
o reduce the clock cycle time, or, equivalently,
o increase the clock rate
seconds
program
cycles
program
seconds
cycle
CPU execution time CPU clock cycles Clock cycle time
for a program for a program
=
equivalently
Also, CPU execution time CPU clock cycles / Clock cycle rate
for a program for a program
103. Our favorite program runs in 10 seconds on computer A, which has a 2
GHz clock. We are trying to help a computer designer build a computer,
B, which will run this program in 6 seconds. The designer has determined
that a substantial increase in the clock rate is possible, but this increase
will affect the rest of the CPU design, causing computer B to require 1.2
times as many clock cycles as computer A for this program. What clock
rate should we tell the designer to target?
CPU timeA = CPU Clock cyclesA / clock rateA
10 sec = CPU Clock cyclesA / 2*109 cycles/sec
CPU Clock cyclesA = 10 sec * 2*109 cycles/sec
= 20 *109 cycles
CPU timeB = 1.2 * CPU Clock cyclesA / clock rateB
6 secs = 1.2 * 20 *109 cycles / clock rateB
clock rateB = 1.2 * 20 *109 cycles / 6 sec= 4 * 109 Hz
To run the program in 6 secs, B must be 4 * 109 Hz
104. Instruction Performance
• No reference to no of instructions in previous equation
• The execution time depends on the number of
instructions in the program
Clock cycles per instruction (CPI)
• Average number of clock cycles per instruction for a
program or program fragment
105. Suppose we have two implementations of the same instruction
set architecture. Computer A has a clock cycle time of 250 ps
and a CPI of 2.0 for some program, and computer B has a
clock cycle time of 500 ps and a CPI of 1.2 for the same
program. Which computer is faster for this program and by
how much?
• Same number of instructions are instructions are
executed
106. Instruction Performance
CPU execution time = Instruction count * average CPI * Clock cycle time
for a program for a program
Or
CPU execution time = Instruction count * average CPI / Clock rate
for a program for a program