HDLC Controller MEGACELL is a high performance module for the bit oriented, switched, non-switched packet transmission module. The controller fulfills the specifications according to ITU Q.921, X.25 Level 2 recommendation. It supports half duplex and full duplex communication lines, point-to-point and multipoint channels. The Controller is designed to permit synchronous, code transparent data transmission. The control information is always in the same position and specific bit patterns used for control differ dramatically from those representing data, which reduces the chances of errors. The data stream and transmission rate is controlled from the network node. In this paper I study the various HDLC Controller.

1. National Conference on Emerging Trends in Electrical, Instrumentation & Communication Engineering 1
Architectures of HDLC Controllers (A Study)
Neeraj kumar Misra
M.Tech. (Pursuing), Dept. of Electronics, ASET, Amity University, Lucknow, India
E-mail: neeraj.mishra3@gmail.com
ABSTRACT
HDLC Controller MEGACELL is a high
performance module for the bit oriented, switched,
non-switched packet transmission module. The
controller fulfills the specifications according to
ITU Q.921, X.25 Level 2 recommendation. It
supports half duplex and full duplex communication
lines, point-to-point and multipoint channels. The
Controller is designed to permit synchronous, code
transparent data transmission. The control
information is always in the same position and
specific bit patterns used for control differ
dramatically from those representing data, which
reduces the chances of errors. The data stream and
transmission rate is controlled from the network
node. In this paper I study the various HDLC
Controller.
Keywords: HDLC Controller, SDLC e.t.c.
1.1 INTRODUCTION TO HDLC
CONTROLLER
HDLC [High-level Data Link Control] is a group of protocols
for transmitting [synchronous] data [Packets] between [Point-
to-Point] nodes. In HDLC, data is organized into a frame.
HDLC protocol resides with Layer 2 of the OSI model, the
data link layer. HDLC uses zero insertion/deletion process [bit
stuffing] to ensure that the bit pattern of the delimiter flag does
not occur in the fields between flags. The HDLC frame is
synchronous and therefore relies on the physical layer to
provide method of clocking and synchronizing the
transmission and reception of frames
1.2 HDLC Operation Modes
HDLC has three operational modes
1. Normal Response Mode (NRM)
2. Asynchronous Response Mode (ARM)
3. Asynchronous Balanced Mode (ABM)
1. Normal Response Mode (NRM)-refers to the standard
primary-secondary relationship. In this mode, a secondary
device must have permission from the primary device before
transmitting. Once permission from the secondary has been
granted, the secondary may initiate a response transmission of
one or more frames containing data.
2. Asynchronous Response Mode (ARM) - a secondary may
initiate the transmission without permission from the secondary
whenever the channel is idle. ARM does not alter the primary-
secondary relationship in any other way. All transmissions from
a secondary must still be made to the primary for relay to final
destination.
3. Asynchronous Balanced Mode (ABM) - all stations are
equal and therefore only combined stations connected in point-
to-point are used. Either combined station may initiate
transmission with the order-combined station without
permission
1.3 DESCRIPTION OF VARIOUS HDLC CONTROLLERS
1.1 GDA’s HDLC Controller -
It is a single-channel HDLC controller core. The device
contains a full-duplex transceiver with independent transmit and
receive sections for bit-level HDLC protocol operations. The
core is designed for easy integration into wide range of
applications implemented on most ASIC and FPGA
technologies. The interface of this core can be adapted for a
wide range of FIFO controllers. Main features of this Controller
are as under Flag insertion and detection, Enable and data valid
signals for flow control, Abort generation and detection and
Full-duplex operation.

2. Architectures of HDLC Controllers (A Study)
National Conference on Emerging Trends in Electrical, Instrumentation & Communication Engineering
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1.2 Amphion single channel HDLC Controller
The Amphion Semiconductor HDLC Protocol Core is a high
performance module for the bit oriented packet transmission
mode. It is suitable for Frame- Relay, X.25, ISDN B-Channel
(64 KBit/s) and DChannel (16 KBit/s). The core fulfills the
specification according to ITU Q.921, X.25 Level 2
recommendation. The data stream and transmission rate is
controlled from the network node (PCM highway clock) with
a backpressure mechanism. This eliminates additional
synchronization and buffering of the data at the network
interface. The data interface is 8 bits wide synchronous and is
suitable for interfacing to transmit and receive FIFOs. An
example of an HDLC frame structure is shown below, for an
8-bit address field with an interframe fill pattern of back-to-
back flags. This figure does not include bits inserted for
transparency. The fields are transmitted in order from left to
right, least significant bit first.
Fig. b Block Diagram of Amphion HDLC Controller
1.3 Avnet Core Single-Channel HDLC Controller
The MC-ACT-HDLC performs the most common functions of
an HDLC controller. Data bytes are clocked into the device
based on a divided version of the transmit clock. This data is
then serialized and framed according to the rules of HDLC and
sent out the serial transmit data pin. Receive frames are clocked
into the receive data pin synchronous to the receive clock. The
framing overhead is then stripped off and the data bytes are
converted from serial to parallel and passed on through the
parallel receive bus. Feature is Flag & Zero insertion and
detection and Full synchronous operation.
Fig. c Block Diagram of Amphion HDLC Controller
1.3 CAST SDLC PROTOCOL CONTROLLER
The SDLC controller is a synthesizable HDL core of a high-
speed synchronous serial communication interface. Operation
of the controller is similar to that used in Intel 8XC152 Global
Serial Channel (GSC) working in SDLC mode under CPU
control. Communication with CPU is realized through Special
Function Registers (SFRs) and 3 interrupt sources. This allows
the SDLC controller for an easy integration into any CPU core.
The design is strictly synchronous with positive-edge clocking,
no internal tri-states and a synchronous reset; therefore scan
insertion is straightforward. Feature is Single and double byte
address recognition and Flexible addressing schemes
VII. CONCLUSION
1.5 CONCLUSION
This paper study and investigate of various HDLC Controller
main aim to present is to compare the different architectures of
HDLC Controllers with their merits and demerits.

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