Elk 1909-125 manuscript-2

Turk J Elec Eng & Comp Sci
() : –
c TÜB˙ITAK
doi:10.3906/elk-
A novel design of current differencing transconductance amplifier with high1
transconductance gain and enhanced bandwidth2
Shireesh Kumar RAI1
, Rishikesh PANDEY1
, Bharat GARG1
, Sujit Kumar PATEL1∗
1
Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India
Received: .201 • Accepted/Published Online: .201 • Final Version: ..201
3
Abstract: In this paper, transconductance gain of current differencing transconductance amplifier (CDTA) has been4
boosted by using a novel approach. Transconductance is generally varied by two well-known techniques. In the first5
technique, bias current of differential pair MOSFETs is varied whereas in the second technique, aspect ratios of differential6
pair MOSFETs are changed. The drawbacks of first technique are limited range of transconductance and higher power7
dissipation whereas second technique restricts dynamic range, output swing and bandwidth of CDTA. To overcome these8
drawbacks, two new structures of CDTA, namely high transconductance gain CDTAs (HTG-CDTA-I & HTG-CDTA-II)9
have been proposed. HTG-CDTA-I utilizes partial positive feedback in the active loads of differential pair MOSFETs10
to increase the transconductance gain. The partial positive feedback reduces the linear range of HTG-CDTA-I that is11
counter balanced by employing source degeneration resistors. In addition, parallel MOSFETs are used in the structures12
of current mirrors to achieve higher value of transconductance. To enhance the bandwidth of proposed HTG-CDTA-13
I, another structure known as HTG-CDTA-II has also been proposed. In this structure, compensation resistors are14
connected at the gate terminals of driver MOSFETs of current mirrors. To prove the worthiness of proposed HTG-15
CDTA-II, KHN filter is realized and its advantages have been discussed.16
Key words: Current differencing transconductance amplifier, partial positive feedback, source degeneration, compen-17
sation resistor, filters, oscillators18
1. Introduction19
There is always a keen interest among researchers and engineers to find a new active building block which can20
offer promising results in the area of signal processing. Analog signal processing uses various active building21
blocks in which operational amplifier, operational transconductance amplifier (OTA) and current conveyors are22
the most popular one among all blocks. Operational amplifiers are considered as one of the dominating blocks23
due to its usage in variety of applications. It has been observed while using OPAMP in different applications that24
there should be some alternatives of OPAMP because it uses much more passive components with appropriate25
matching to achieve desired functionality [1]. Another block namely OTA places itself in the race of OPAMP26
due to its simpler design and feature of electronic tunability. The feature of electronic tunability offers several27
advantages but it also suffers from some drawbacks such as limited range of linearity, higher power dissipation28
and restricted range of transconductance gain. In view of this, current conveyors started dominating due to29
its inherent features of higher linearity, wider bandwidth and lower power consumption. Interestingly, current30
∗Correspondence: sujit.patel@thapar.edu
1

Sujit Kumar PATEL, Bharat GARG and Shireesh Kumar RAI/Turk J Elec Eng & Comp Sci
conveyor was reported in 1968 by Smith and Sedra [2] but it gained popularity after few years in the area of1
current-mode signal processing. Now, current-mode active building blocks are becoming popular and therefore,2
a new block namely current differencing transconductance amplifier (CDTA) by using the advantages of both3
current conveyors as well as OTA was suggested by Biolek in 2003 [3]. CDTA is now one of the dominating4
blocks and is widely being used in numerous applications of analog signal processing. These applications5
include comparator [4], current limiter [5], analog filters [6, 7], inductance simulation circuits [8], modulator [9],6
multiplier [10], oscillator [11], squaring circuit and square rooter [12], precision power detector [13], rectifier [14]7
and Schmitt trigger [15]. Apart from these applications, different structures of CDTAs have also been reported8
by many researchers. The bipolar junction transistor based CDTA was reported in [16] whereas CMOS based9
CDTA was presented in [17]. The CMOS based CDTA was also used to realize a simpler and economical10
design of current-mode KHN filter. Another structure of BJT based current-controlled current differencing11
transconductance amplifier (CCCDTA) was reported in which parasitic resistances were controlled by the input12
biasing current [18] whereas the CMOS based CCCDTA was realized in [19]. A high performance CDTA was13
reported in [20] which reduces the parasitic resistances and was utilized in precision rectification. A flipped14
voltage follower based current differencing unit and multiple output OTA were combined to realize a multiple15
output CDTA [21]. Next, CDTA with low input impedance, high output impedance, improved linearity and16
high gain was reported in [22]. A modified structure of CDTA namely Z -copy CDTA and its application as17
single resistance controlled oscillator were presented in [23]. Thereafter, the output resistance and linearity of18
CDTA were increased by using cascode current mirrors and cross-coupled quad configuration, respectively in19
[24]. A bulk driven technique was used to reduce supply voltage requirement in the reported structure of CDTA20
[25]. A modified current differencing unit and flipped voltage follower technique were combined to realize CDTA21
and was also utilized to design a universal filter [26]. A Z -copy CDTA reported in [27] uses third generation22
current conveyor and dual output OTA to improve its universality. Subsequently, in order to reduce the input23
resistance, a positive feedback technique has been used in Z -copy CDTA [28]. To enhance the bandwidth,24
authors have suggested another structure of CDTA based on NMOS transistors only [29]. The cross coupled25
MOSFETs are also employed to improve the linearity. A high performance CDTA with enhanced bandwidth26
was reported in which tuning of transconductance was achieved by varying the bias voltage [30]. Another27
structure of transconductance boosted CDTA has been reported in which biasing current is kept constant and28
transconductance is varied by changing the number of parallel MOSFETs used in place of differential pair29
MOSFETs [31]. Later on, positive feedback technique has been used in the active load of differential pair of30
CDTA to achieve higher value of transconductance [32]. In another circuit of CDTA, partial positive feedback31
and parallel MOSFETs in place of differential pair have been used in order to achieve significant range and values32
of transconductance [33]. A high performance CDTA has been reported in [34] where the transconductance33
is boosted by combining the output of two current mirror structures. Recently, a paper has been published34
on transconductance boosting by utilizing common source amplifiers in between gate and source terminals of35
differential pair MOSFETs. In addition, partial positive feedback technique is also utilized but the power36
dissipation of the CDTA is nearly 7 mW [35].37
In most structures of CDTA reported so far in literature, the variation of transconductance is obtained by38
varying the bias current. This method of transconductance variation has some drawbacks including higher power39
dissipation and restricted range of transconductance. Increasing aspect ratios of differential pair MOSFETs to40
obtain a higher value of transconductance also adversely affect the bandwidth and input/output swing of41
2

CDTA. Therefore, the paper aims to design two structures of CDTA using novel approach which overcome the1
above mentioned drawbacks. In this paper, a new approach of transconductance boosting has been proposed2
which utilizes two different techniques. The first technique utilizes the partial positive feedback in the active3
load of differential pair MOSFETs to achieve a higher transconductance gain. The well-known side effect of4
positive feedback is reduced linearity which is counter balanced by employing source degeneration resistors5
in the differential pair MOSFETs. In addition, parallel MOSFETs are used in the structure of current6
mirrors to further achieve a higher transconductance gain which adversely affect the bandwidth of CDTA.7
The bandwidth is enhanced by using resistive compensation method [36] to balance and mitigate the adverse8
effect of parallel MOSFETs used in current mirror structures. The proposed structure of CDTA is named as9
high transconductance gain CDTA (HTG-CDTA). The paper is organized as follows. The symbolic notation10
and characteristics of conventional CDTA is given in Section 2. The proposed structures of HTG-CDTAs and11
small signal analysis are covered in Section 3. Simulation results and comparison with other existing structures12
of CDTAs are given in Section 4. Application example of proposed HTG-CDTA-II and its advantage are13
highlighted in Section 5. Section 6 presents the concluding remarks.14
2. Symbolic notation and characteristics of CDTA15
The symbolic notation of CDTA is given in Figure 1. It is a five terminal block in which p and n are input16
terminals, z is intermediate terminal and x+ and x− are output terminals. The input impedances of p and n17
terminals are quite low whereas the output impedances of x+ and x− are very high. Currents Ip and In are18
applied at p and n terminals, respectively and difference of these currents is obtained at z terminal as given in19
Eq. (1). The voltage Vz at z terminal is obtained by connecting impedance Zz at z terminal as expressed in20
Eq. (2). The voltage Vz serves the input for transconductance amplifier which converts the voltage Vz into two21
output currents Ix+ and Ix− by its transconductance gain (gm ) as given by Eq. (3). The transconductance of22
CDTA is controlled by varying bias current IB and aspect ratios of differential pair MOSFETs as given in Eq.23
(4). The most commonly used structure of CDTA is depicted in Figure 2.24
Vp = Vn = 0; Iz = Ip − In (1)
Vz = Iz · Zz (2)
Vx+ = gmVz, Ix− = −gmVz (3)
gm = 2µnCox
W
L
× IB (4)
Figure 1. Symbolic notation of CDTA.
3

Figure 2. Circuit diagram of conventional CDTA [17].
3. Proposed design of high transconductance gain CDTAs (HTG-CDTAs)1
In the proposed design of HTG-CDTA-I shown in Figure 3, partial positive feedback technique is used to enhance2
the transconductance gain. The disadvantage of positive feedback technique is non-linearity which is counter3
balanced by using source degeneration resistors in differential pair MOSFETs. The partial positive feedback is4
formed by MOSFETs M27 and M28. The source degeneration resistors RD are connected at source terminals5
of differential pair MOSFETs (M7 and M8). In addition, the current mirrors (formed by MOSFETs M9-M13,6
M14-M18, M19-M22 and M23-M26) are used in such a way that their combined outputs boost the values of7
currents at Ix+ and Ix− terminals of HTG-CDTA-I. The current through differential pair MOSFETs (IT and8
IT ) are copied by each parallel MOSFET of current mirrors and their combination gives the higher values of9
currents Ix+ and Ix− . These two techniques in combination give much better results as compared to other10
structures of CDTAs available in the literature.11
Figure 3. Circuit diagram of proposed HTG-CDTA-I .
4

The parallel MOSFETs used in the structures of current mirrors aﬀect the bandwidth of HTG-CDTA-I due1
to increased values of parasitic capacitances at x+ and x− terminals. Therefore, another structure of CDTA2
namely HTG-CDTA-II shown in Figure 4, has been proposed in which bandwidth has been increased by using3
the compensation resistors (R) between gate and drain terminals of current mirrors formed by MOSFETs4
M9-M13, M14-M18, M19-M22 and M23-M26 [36].5
Figure 4. Circuit diagram of proposed HTG-CDTA-II.
3.1. Small signal analysis of proposed HTG-CDTAs6
The small signal equivalent model of transconductance ampliﬁer of proposed HTG-CDTA-I is shown in Figure 5.7
Various equations have been obtained under appropriate assumptions to derive the equation of transconductance8
(Gm) gain. It can be concluded from Figure 5 that the value of ro9||ro27|| 1
gm9
||(− 1
gm27
) is reduced to 1
gm9−gm27
9
as the values of output resistances r09 and r027 are very high as compared to 1
gm9
and − 1
gm27
. After applying10
KCL at node B, we get11
gm7vz
2
+
vg10
r07
= vB
1
RD
+
1
r07
(5)
vB = −vg10(gm9 − gm27)RD (6)
Substituting the value of vB from Eq. (6) into Eq. (5) , we get12
vg10
∼=
−gm7
vz
2
(gm9 − gm27) 1 + RD
r07
(7)
The value of r014||r028|| 1
gm14
|| − 1
gm28
is reduced to 1
gm14−gm28
as r014||r028
1
gm14
|| − 1
gm28
.13
5

Figure 5. Small signal equivalent model of proposed HTG-CDTA-I.
Therefore, after applying KCL at node C gives1
vg15
∼=
gm8
vz
2
(gm14 − gm28) 1 + RD
r08
(8)
The value of vg20 can be obtained after applying KCL at node D as2
vg20
∼= −
gm15
gm19
×
gm8
vz
2
1
r07
+ (gm14 − gm28) 1 + RD
r08
(9)
Due to similar aspect ratios of MOSFETs of Figure 3, the corresponding transconductance gains of MOSFETs3
can be considered equal as given in Eq. (10)4
gm9 = gm10 = gm11 = gm12; gm19 = gm20 = gm21 = gm22; gm14 = gm15; gm7 = gm8 = gm (10)
The value of current ix+ can be derived after applying KCL at node E as5
ix+ = − (gm10 + gm11 + gm12) vg10 − (gm20 + gm21 + gm22) vg20 (11)
With the help of Eqs. (7), (9), (10) and (11) the value of ix+ can be approximated as6
ix+ =
3gm
(1 − η)(1 + β)
vz (12)
where η = gm27
gm9
and β = RD
r07
.7
The enhanced value of Gm is given by Eq. (13)8
Gm =
3gm
(1 − η)(1 + β)
(13)
By choosing the appropriate values of η, the transconductance gain (Gm) of proposed HTG-CDTA-I is increased9
while the appropriate value of β helps in maintaining the acceptable range of linearity of proposed HTG-CDTA-10
I. In HTG-CDTA-II (Figure 4), compensation resistors are connected between gate and drain terminals of driver11
6

MOSFETs of current mirrors (M9, M14, M19 and M23) to enhance the bandwidth and therefore the voltages1
at gate terminals of MOSFETs M9 & M10 (vg9 and vg10 ), M14 & M15 (vg14 and vg15 ), M18 & M19 (vg18 and2
vg19 ), and M23 & M24 (vg23 and vg24 ) are diﬀerent. The relation between vg9 and vg10 can be easily derived3
using equivalent model shown in Figure 6. After applying KCL at node G we get4
vg10 = vg9 1 +
Cgs
Cgd
s + 1
R(Cgs+Cgd)
s + 1
RCgd
(14)
Figure 6. Small signal model incorporating compensation resistor in HTG-CDTA-II.
5
It is clearly observed from the Eq. (14) that the compensation resistor introduces one zero and one pole.6
Therefore, dominant pole of HTG-CDTA-II can be cancelled by choosing appropriate value of compensation7
resistor which results in enhanced bandwidth.8
4. Simulation results and discussions of HTG-CDTAs9
The proposed HTG-CDTAs are designed and simulated by Mentor Graphics Eldo simulator using 180 nm CMOS10
technology parameters. The supply voltages are chosen as VDD = −VSS = 0.9V. The bias currents are selected11
as IB1 = IB2 = 30µA and IB = 50µA. The values of source degeneration and compensation resistors are12
chosen as 5KΩ and 75KΩ, respectively. The aspect ratios of MOSFETs used to design proposed HTG-CDTAs13
are shown in Table 1.14
Table 1. Aspect ratios of MOSFETs
MOSFETs W/L (µm)
M1-M4 6/0.36
M5-M6 36/0.36
M7-M8 3.6/0.36
M9-M18, M27, M28 1.8/0.36
M19-M26 1.4/0.36
7

4.1. Simulation results of HTG-CDTA-I1
The variation in the transconductance gain of conventional CDTA [17] is shown in Figure 7(a). It is observed2
that the transconductance gain of conventional CDTA varies from 0.13 to 0.41 mA/V for variations in the3
bias current from 10 to 50 µA. Its power dissipation remains in the range of 1.03 to 1.50 mW. Figure 7(b)4
shows the variations in the transconductance gain of proposed HTG-CDTA-I and it is clearly seen that the5
transconductance range varies from 1.75 to 6 mA/V for the same range of bias current from 10 to 50 µA.6
The power dissipation is in the range of 213.02 to 432.35 µW. The range of transconductance gain of HTG-7
CDTA-II is shown in Figure 7(c). It is observed that proposed HTG-CDTA-II also gives the same range of8
transconductance gain as that of HTG-CDTA-I for the same range of biasing currents due to which power9
dissipations also remain in the same range. Therefore, it can be concluded from simulation results that the10
proposed HTG-CDTAs provide higher values and range of transconductance gain for the same range of bias11
current while the power dissipation is also reduced as compared to conventional CDTA.12
(a) (b)
(c)
Figure 7. Variation of transconductance (a) existing CDTA [17] and proposed (b) HTG-CDTA-I (c) HTG-CDTA-II.
Monte Carlo (MC) analysis has been performed to observe the deviations of transconductance gain of proposed13
8

HTG-CDTAs while source degeneration resistances are varied by 10% of their nominal values. Gaussian random1
variations have been given to analyse the eﬀect of mismatch. In MC analysis, the transconductance gains of2
proposed HTG-CDTAs for 100 runs are shown in Figures 8 (a) and (b). It is seen from simulation results that3
the transconductance gains of proposed HTG-CDTAs for the biasing current of 50µA remain in the range of 5.54
to 6.3 mA/V while values of source degeneration resistances are varied by 10%. Therefore, the slight deviation5
in the boosting of transconductance gains is observed when source degeneration resistances are mismatched but6
it remains in the acceptable range for proposed HTG-CDTA-I and HTG-CDTA-II7
(a) (b)
Figure 8. MC analysis for transconductance gain of proposed (a) HTG-CDTA-I, (b) HTG-CDTA-II.
The current gains (Ix+
Ip
, Ix+
In
) and (Ix−
Ip
, Ix−
In
, Iz
Ip
, Iz
In
) of HTG-CDTA-I are shown in Figure 9 and Figure 10,8
respectively. The 3 dB bandwidths of current gains Ix+
Ip
, Ix+
In
, Ix−
Ip
, Ix−
In
are found to be same as 17.5 MHz while9
3 dB bandwidth of current gains Iz
Ip
and Iz
In
are obtained as 475 MHz and 480 MHz. From DC analysis, the10
(a) (b)
Figure 9. Current gain of proposed HTG-CDTA-I: (a)
Ix+
Ip
, (b)
Ix+
In
.
9

(a) (b)
(c) (d)
Figure 10. Current gain of proposed HTG-CDTA-I: (a)
Ix−
Ip
, (b)
Ix−
In
, (c) Iz
Ip
, and (d) Iz
In
.
(a) (b)
Figure 11. (a) Linear range of proposed HTG-CDTA-I, (b) Transient response of proposed HTG-CDTA-I.
linear range of proposed HTG-CDTA-I is obtained from -100 to + 100 mV as shown in Figure 11(a). For1
transient analysis, a sinusoidal current of peak to peak amplitude of 50 µA with 1 MHz frequency is applied on2
input terminal p of HTG-CDTA-I which gives two current outputs Ix+ and Ix− of peak to peak amplitude3
of 180 µA as shown in Figure 11(b). These currents are opposite in phase.4
10

4.2. Simulation results of HTG-CDTA-II1
The bandwidth of proposed HTG-CDTA-II is enhanced by employing compensation resistors between gate- to-2
drain terminals of driver MOSFETs of current mirror structures. The current gains Ix+
Ip
, Ix+
In
, Ix−
Ip
, Ix−
In
, Iz
Ip
, Iz
In
3
of proposed HTG-CDTA-II are plotted in Figures 12(a)-12(f). The 3 dB bandwidth is signiﬁcantly improved4
as compared to 3 dB bandwidth of HTG-CDTA-I and is found to be 77 MHz, 78 MHz, 76.5 MHz, 77.5 MHz,5
475 MHz and 480 MHz for Ix+
Ip
, Ix+
In
, Ix−
Ip
, Ix−
In
, Iz
Ip
, Iz
In
, respectively.6
(a) (b)
(c) (d)
(e) (f)
Figure 12. Current gain of proposed HTG-CDTA-II: (a)
Ix+
Ip
, (b)
Ix+
In
, (c)
Ix−
Ip
, (d)
Ix−
In
, (e) Iz
Ip
, and (f) Iz
In
.
11

Linear range of proposed HTG-CDTA-II is also obtained from -100 to +100 mV as shown in Figure 13(a).1
The transient analysis is shown in Figure 13(b) which gives two current outputs of peak-to-peak amplitudes of2
200 µA when a current input of peak-to-peak amplitude of 50 µA is applied at ‘p’ terminal of HTG-CDTA-II.3
(a) (b)
Figure 13. (a) Linear range of proposed HTG-CDTA-II (b) Transient response of proposed HTG-CDTA II.
The performance parameters of proposed structures of HTG-CDTAs have been compared with existing4
structures of CDTA as given in Table 2. It is concluded from Table 2 that the proposed structures of HTG-5
CDTAs provide significant value of transconductance gain for very less value of bias current and thereby reduces6
power dissipation. The gain bandwidth (GBW) product of proposed HTG-CDTA-II is greater than most of7
the reported structure of CDTA. Only two structures reported in [20] and [34] have greater GBW but their8
power dissipations are much more than the proposed HTG-CDTA-II. It is also observed that the bandwidth9
of proposed HTG-CDTA-II has been increased by more than five times over the bandwidth of HTG-CDTA-I10
while power dissipations of both structures remain in the same range.11
5. Application of proposed HTG-CDTA-II12
The performance of proposed HTG-CDTA-II is verified by realizing a KHN filter. The advantages offered by13
HTG-CDTA-II in KHN filter is highlighted.14
5.1. KHN filter realized by proposed HTG-CDTAs15
KHN filter is one of the standard analog filters which has been realized by using both conventional as well as16
proposed HTG-CDTA-II in order to compare the performances. The center frequency (f0 ) of KHN filter shown17
in Figure 14 is given as18
f0 =
1
2π
Gm1 · Gm2
C1 · C2
(15)
where Gm1 = Gm2 = Gm are the transconductance gains of the proposed HTG-CDTAs.19
The values of capacitors used in the realization of KHN filters are chosen as C1 = C2 = 10 pF. The biasing20
currents (IB ) are selected as 50 µA for KHN filters realized by both conventional CDTA as well as proposed21
12

Table 2. Comparison between different structures of CDTA
Reference Technology Supply Transconductance Bandwidth GBW Power Diss.
Voltage (V) (Siemens) (MHz) (mW)
[7] 0.35 µm ±0.75 210 µS @ 54 µA 20 4.2 −−
[17] 0.25 µm ±2.5 1.53 mS @ 1 mA 145 221.8 12.07
[20] 0.35 µm ±1.8 873 µS @ 40 µA 926 808.4 6.31
[25] 0.25 µm ±0.6 99 µS @ Rset = 10kΩ 17 1.7 0.143
[29] 0.5 µm ±1.25 138.4 µS @ 1.5 mA 959 132.7 2.48
[30] 0.18 µm ±0.8 1.175 mS @ 1V 1150 135.1 1.79
[31] 0.18 µm ±2 7.88 mS @ 200µA 26 204.9 8.75
[32] 0.18 µm ±2 7.8 mS @ 1mA 52 405.6 12.07
[33] 0.18 µm ±2 14.01 mS @ 1 mA 78 109.3 7.95
[34] 0.18 µm ±2 6.12 mS @ 600 µA 103 630.4 12.38
[35] 0.18 µm ±0.9 15.8 mS @ 1 mA 67 105.9 7.43
Proposed 0.18 µm ±0.9 6 mS @ 50µA 17.5 105 0.432
HTG-CDTA-I
Proposed 0.18 µm ±0.9 6 mS @ 50µA 78 468 0.432
HTG-CDTA-II
GBW: Gain bandwidth product in Siemens-KHz.
Figure 14. KHN filter [17] realized by using proposed HTG-CDTA-II.
HTG-CDTA-II. Conventional CDTA offers transconductance gain of 0.41 mA/V while proposed HTG-CDTA-1
II offers transconductance of 6.02 mA/V. The center frequency (f0 ) of KHN filter designed by conventional2
CDTA is 6.5 MHz and the power dissipation is 3 mW. The center frequency of KHN filter realized by proposed3
HTG-CDTA-II gives center frequency up to 96 MHz while the power dissipation is only 864 µW. Therefore,4
it can be concluded that the KHN filter realized by proposed HTG-CDTA-II gives 14.6 times greater center5
frequency as compared to KHN filter realized by conventional CDTA while power dissipation is reduced almost6
3.5 times. The responses of KHN filters are shown in Figures 15(a) and 15(b).7
13

(a) (b)
Figure 15. Frequency response of KHN filter realized by (a) existing CDTA and (b) proposed HTG-CDTA-II.
6. Conclusions1
The transconductance gain of current differencing transconductance amplifier (CDTA) has been boosted by2
using a novel approach. The adverse effects of transconductance boosting have been counter balanced by using3
source degeneration resistors at the source terminals of differential pair MOSFETs. Two new structures of4
CDTAs namely HTG-CDTA-I and HTG-CDTA-II have been proposed. The bandwidth of HTG-CDTA-II has5
also been increased by using compensation resistors between gate and drain terminals of driver MOSFETs of6
current mirrors. The power dissipations of proposed structures are very less as compared to other structures of7
CDTAs available in literature. KHN filters are realized by both conventional and proposed HTG-CDTA-II in8
order to compare their performances. The KHN filter realized by proposed HTG-CDTA-II gives better result as9
compared to KHN filter realized by conventional CDTA because it provides 14.6 times greater center frequency10
while power dissipation is reduced almost 3.5 times.11
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