This document summarizes electromagnetic analyses of different configurations of integrated production umbilical cables. Umbilical cables can have multiple independent power circuits and steel tubes. Three configurations (A, B, C) are analyzed using a combined 2D finite element and transposition methodology to evaluate performance considering load terminal voltages and induced voltages. Configuration B, where each power circuit rotates around its own center, has the best performance with balanced terminal voltages and minimized induction effects along the cable length.
TCAD Based Analysis of Gate Leakage Current for High-k Gate Stack MOSFETIDES Editor
Scaling of metal-oxide-semiconductor transistors
to smaller dimensions has been a key driving force in the IC
industry. This work analysis the gate leakage current behavior
of nano scale MOSFET based on TCAD simulation. The
Sentaurus Simulator simulates the high-k gate stack structure
of N-MOSFET for analysis purpose. The impact of interfacial
oxide thickness on the gate tunneling current has been
investigated as a function of gate voltages for a given equivalent
oxide thickness (EOT) of 1.0 nm. It was reported in the results
that interfacial oxide thickness plays an important role in
reducing the gate leakage current. It is also observed that high-
k stack gated MOSFET exhibits improved performance in term
of Off current and DIBL
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction...IJECEIAES
To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 µW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 µW while CVSL shows total power consumption of 18.94 µW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
Effect of mesh grid structure in reducing hot carrier effect of nmos device s...ijcsa
This paper presents the critical effect of mesh grid that should be considered during process and device
simulation using modern TCAD tools in order to develop and optimize their accurate electrical
characteristics. Here, the computational modelling process of developing the NMOS device structure is
performed in Athena and Atlas. The effect of Mesh grid on net doping profile, n++, and LDD sheet
resistance that could link to unwanted “Hot Carrier Effect” were investigated by varying the device grid
resolution in both directions. It is found that y-grid give more profound effect in the doping concentration,
the junction depth formation and the value of threshold voltage during simulation. Optimized mesh grid is
obtained and tested for more accurate and faster simulation. Process parameter (such as oxide thicknesses
and Sheet resistance) as well as Device Parameter (such as linear gain “beta” and SPICE level 3 mobility
roll-off parameter “ Theta”) are extracted and investigated for further different applications.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
TCAD Based Analysis of Gate Leakage Current for High-k Gate Stack MOSFETIDES Editor
Scaling of metal-oxide-semiconductor transistors
to smaller dimensions has been a key driving force in the IC
industry. This work analysis the gate leakage current behavior
of nano scale MOSFET based on TCAD simulation. The
Sentaurus Simulator simulates the high-k gate stack structure
of N-MOSFET for analysis purpose. The impact of interfacial
oxide thickness on the gate tunneling current has been
investigated as a function of gate voltages for a given equivalent
oxide thickness (EOT) of 1.0 nm. It was reported in the results
that interfacial oxide thickness plays an important role in
reducing the gate leakage current. It is also observed that high-
k stack gated MOSFET exhibits improved performance in term
of Off current and DIBL
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction...IJECEIAES
To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 µW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 µW while CVSL shows total power consumption of 18.94 µW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
Effect of mesh grid structure in reducing hot carrier effect of nmos device s...ijcsa
This paper presents the critical effect of mesh grid that should be considered during process and device
simulation using modern TCAD tools in order to develop and optimize their accurate electrical
characteristics. Here, the computational modelling process of developing the NMOS device structure is
performed in Athena and Atlas. The effect of Mesh grid on net doping profile, n++, and LDD sheet
resistance that could link to unwanted “Hot Carrier Effect” were investigated by varying the device grid
resolution in both directions. It is found that y-grid give more profound effect in the doping concentration,
the junction depth formation and the value of threshold voltage during simulation. Optimized mesh grid is
obtained and tested for more accurate and faster simulation. Process parameter (such as oxide thicknesses
and Sheet resistance) as well as Device Parameter (such as linear gain “beta” and SPICE level 3 mobility
roll-off parameter “ Theta”) are extracted and investigated for further different applications.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
Design of Two Two-Way Out-of-Phase Slotline Power Divider in C-BandIJTET Journal
Abstract— Power divider is one of the major components of radio frequency circuits. In this paper two two-way out-of-phase slotline power dividers designed was presented in a microstrip platform. The power dividing circuit, low profile is designed at compact size structure. To provide better isolation at the two output ports microstripline is bent and a slotline is provided. The design is simulated using ADS, results substantiate low insertion loss, better isolation and amplitude balancing at the output ports.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
In this paper, a Wavelet modulated isolated two-stage three-phase bidirectional AC-DC converter is proposed for electric vehicle (EV) charging systems. Half-bridge resonant CLLC converter is proposed due to its high efficiency, wide gain range, galvanic isolation and bidirectional power flow. Wavelet modulation technique is used for three-phase six leg AC-DC converter due to its benefits of high DC component and lower harmonic contents. The proposed two-stage converter is developed and simulated in MATLAB Simulink environment. The contribution of this paper is on the implementation and performance analysis of Wavelet modulation in bidirectional AC-DC converters. The results show that Wavelet modulation is suitable to be implemented for the proposed bidirectional converter. The performance of the proposed converter delivers very low output voltage ripple and total harmonic distortion output current of less than 10% which is within the expected results.
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
Modeling and Structure Optimization of Tapped Transformer Yayah Zakaria
In this paper, a simplified circuit model of the tapped transformer structure has been presented to extract the Geometric and technology parameters and offer better physical understanding. Moreover, the structure of planar transformer has been optimized by using changing the width and space of the
primary coil, so as to enlarge the quality factor Q and high coupling coefficient K. To verify the results obtained by using these models, we have compared them with the results obtained by employing the MATLAB simulator. Very good agreement has been recorded for the effective primary
inductance value, whereas the effective primary quality factor value has shown a somewhat larger deviation than the inductance.
Compact Dual-Band Bandpass Filter Based on Stub-Loaded Rectangular Loop Stepp...ijeljournal
This work presents a compact dual-band bandpass filter (BPF) based on stub-loaded rectangular loop stepped impedance resonator (SLRLSIR). The proposed SLRLSIR consists of two outer open-circuited and two inner open-circuited stubs, which are designed to the central sides of the rectangular loop resonator. Owing to its symmetry, even-and odd-mode analysis methods are applied to deduce the equivalent-circuit
equations and to justify the structural design. The second passband can be easily tuned by changing the two
inner open-circuited stubs when the first passband is fixed at a desirable frequency. The upper stopband is
improved by a pair of additional open-circuited stubs stepped impedance resonators at the I/O ports. Transmission zeros are generated between passbands and stopbands. A SLRLSIR prototype dual-band BPF with central frequencies of 2.42/4 GHz is fabricated and systematically studied. The measurement results agreed well with the simulation results.
Compact dual band bandpass filter based on stub loaded rectangular loop stepp...ijeljournal
This work presents a compact dual-band bandpass filter (BPF) based on stub-loaded rectangular loop
stepped impedance resonator (SLRLSIR). The proposed SLRLSIR consists of two outer open-circuited and
two inner open-circuited stubs, which are designed to the central sides of the rectangular loop resonator.
Owing to its symmetry, even-and odd-mode analysis methods are applied to deduce the equivalent-circuit
equations and to justify the structural design. The second passband can be easily tuned by changing the two
inner open-circuited stubs when the first passband is fixed at a desirable frequency. The upper stopband is
improved by a pair of additional open-circuited stubs stepped impedance resonators at the I/O ports.
Transmission zeros are generated between passbands and stopbands. A SLRLSIR prototype dual-band BPF
with central frequencies of 2.42/4 GHz is fabricated and systematically studied. The measurement results
agreed well with the simulation results.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Microcontroller–Based Modified SEPIC Converter for Driving Lamp with Power Fa...IJERA Editor
A methodological study of electronic ballast for electrode less lamps including design and development issues is
presented in this paper. The ballast is intended to feed a 300 W ultra violet lamp at 100 kHz with dimming
feature. The proposed topology is composed of a Single-Ended Primary Inductance Converter (SEPIC), used as
power factor correction (PFC) stage, integrated with a resonant half-bridge inverter, used as lamp power control
(PC) stage. The integration of both stages is proposed in this paper, in order to reduce the number of active
switches, as well as to simplify the required driving and control circuitry for this application. The implemented
topology attained very high power factor (0.9982), and low line current total harmonic distortion (THD)
(1.86%), without using electromagnetic interference (EMI) filter, while the measured efficiency was 90% at
nominal lamp power.
Planar transmission line is one of the physical medium used to transmit high frequency signal. The signal flow through the transmission line depends on the important electrical parameter, the frequency. As the signal frequency increases in a conductor, current carriers start to move towards the edges of the conductor. Flow of carriers on the conductor synchronizes with the substrate to achieve better efficiency. The signal flow in the transmission line depends on the dielectric constant of the material and the loss tangent value. The paper shows the simulation studies on return loss and insertion loss of planar transmission lines with constant frequency of 10GHz. To design planar transmission lines different dielectric materials are being selected. In our design, parameters like input impedance, conductor (silver) thickness and conductor height are kept constant. The design and analysis is done using Applied Wave Research (AWR) tool. The obtained results shows unique response and it depends on the type of dielectric medium selected.
A horn may be considered as a flared out waveguide. In this paper, a powerful electromagnetic simulator, 3D
EM solver WIPL-D software is used to design, analyse and optimize the dimensions of horn antenna which is
based on MOM solution for computations. The standard horn antenna at 10 GHz for 15dB gain is modelled and
the radiation pattern was observed. The horn antenna is optimized to achieve more than 20dB gain using
Genetic Algorithm, radiation patterns of the optimized horn antenna are also presented. Geometry of the horn
can be modelled by exploring the toolbar ‘symmetry’ option in WIPL-D. Design of X band Pyramidal Horn
Antenna is fabricated and measured using Network Analyzer.
Design of Two Two-Way Out-of-Phase Slotline Power Divider in C-BandIJTET Journal
Abstract— Power divider is one of the major components of radio frequency circuits. In this paper two two-way out-of-phase slotline power dividers designed was presented in a microstrip platform. The power dividing circuit, low profile is designed at compact size structure. To provide better isolation at the two output ports microstripline is bent and a slotline is provided. The design is simulated using ADS, results substantiate low insertion loss, better isolation and amplitude balancing at the output ports.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
In this paper, a Wavelet modulated isolated two-stage three-phase bidirectional AC-DC converter is proposed for electric vehicle (EV) charging systems. Half-bridge resonant CLLC converter is proposed due to its high efficiency, wide gain range, galvanic isolation and bidirectional power flow. Wavelet modulation technique is used for three-phase six leg AC-DC converter due to its benefits of high DC component and lower harmonic contents. The proposed two-stage converter is developed and simulated in MATLAB Simulink environment. The contribution of this paper is on the implementation and performance analysis of Wavelet modulation in bidirectional AC-DC converters. The results show that Wavelet modulation is suitable to be implemented for the proposed bidirectional converter. The performance of the proposed converter delivers very low output voltage ripple and total harmonic distortion output current of less than 10% which is within the expected results.
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
Modeling and Structure Optimization of Tapped Transformer Yayah Zakaria
In this paper, a simplified circuit model of the tapped transformer structure has been presented to extract the Geometric and technology parameters and offer better physical understanding. Moreover, the structure of planar transformer has been optimized by using changing the width and space of the
primary coil, so as to enlarge the quality factor Q and high coupling coefficient K. To verify the results obtained by using these models, we have compared them with the results obtained by employing the MATLAB simulator. Very good agreement has been recorded for the effective primary
inductance value, whereas the effective primary quality factor value has shown a somewhat larger deviation than the inductance.
Compact Dual-Band Bandpass Filter Based on Stub-Loaded Rectangular Loop Stepp...ijeljournal
This work presents a compact dual-band bandpass filter (BPF) based on stub-loaded rectangular loop stepped impedance resonator (SLRLSIR). The proposed SLRLSIR consists of two outer open-circuited and two inner open-circuited stubs, which are designed to the central sides of the rectangular loop resonator. Owing to its symmetry, even-and odd-mode analysis methods are applied to deduce the equivalent-circuit
equations and to justify the structural design. The second passband can be easily tuned by changing the two
inner open-circuited stubs when the first passband is fixed at a desirable frequency. The upper stopband is
improved by a pair of additional open-circuited stubs stepped impedance resonators at the I/O ports. Transmission zeros are generated between passbands and stopbands. A SLRLSIR prototype dual-band BPF with central frequencies of 2.42/4 GHz is fabricated and systematically studied. The measurement results agreed well with the simulation results.
Compact dual band bandpass filter based on stub loaded rectangular loop stepp...ijeljournal
This work presents a compact dual-band bandpass filter (BPF) based on stub-loaded rectangular loop
stepped impedance resonator (SLRLSIR). The proposed SLRLSIR consists of two outer open-circuited and
two inner open-circuited stubs, which are designed to the central sides of the rectangular loop resonator.
Owing to its symmetry, even-and odd-mode analysis methods are applied to deduce the equivalent-circuit
equations and to justify the structural design. The second passband can be easily tuned by changing the two
inner open-circuited stubs when the first passband is fixed at a desirable frequency. The upper stopband is
improved by a pair of additional open-circuited stubs stepped impedance resonators at the I/O ports.
Transmission zeros are generated between passbands and stopbands. A SLRLSIR prototype dual-band BPF
with central frequencies of 2.42/4 GHz is fabricated and systematically studied. The measurement results
agreed well with the simulation results.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Microcontroller–Based Modified SEPIC Converter for Driving Lamp with Power Fa...IJERA Editor
A methodological study of electronic ballast for electrode less lamps including design and development issues is
presented in this paper. The ballast is intended to feed a 300 W ultra violet lamp at 100 kHz with dimming
feature. The proposed topology is composed of a Single-Ended Primary Inductance Converter (SEPIC), used as
power factor correction (PFC) stage, integrated with a resonant half-bridge inverter, used as lamp power control
(PC) stage. The integration of both stages is proposed in this paper, in order to reduce the number of active
switches, as well as to simplify the required driving and control circuitry for this application. The implemented
topology attained very high power factor (0.9982), and low line current total harmonic distortion (THD)
(1.86%), without using electromagnetic interference (EMI) filter, while the measured efficiency was 90% at
nominal lamp power.
Planar transmission line is one of the physical medium used to transmit high frequency signal. The signal flow through the transmission line depends on the important electrical parameter, the frequency. As the signal frequency increases in a conductor, current carriers start to move towards the edges of the conductor. Flow of carriers on the conductor synchronizes with the substrate to achieve better efficiency. The signal flow in the transmission line depends on the dielectric constant of the material and the loss tangent value. The paper shows the simulation studies on return loss and insertion loss of planar transmission lines with constant frequency of 10GHz. To design planar transmission lines different dielectric materials are being selected. In our design, parameters like input impedance, conductor (silver) thickness and conductor height are kept constant. The design and analysis is done using Applied Wave Research (AWR) tool. The obtained results shows unique response and it depends on the type of dielectric medium selected.
A horn may be considered as a flared out waveguide. In this paper, a powerful electromagnetic simulator, 3D
EM solver WIPL-D software is used to design, analyse and optimize the dimensions of horn antenna which is
based on MOM solution for computations. The standard horn antenna at 10 GHz for 15dB gain is modelled and
the radiation pattern was observed. The horn antenna is optimized to achieve more than 20dB gain using
Genetic Algorithm, radiation patterns of the optimized horn antenna are also presented. Geometry of the horn
can be modelled by exploring the toolbar ‘symmetry’ option in WIPL-D. Design of X band Pyramidal Horn
Antenna is fabricated and measured using Network Analyzer.
Design and manufacturing of iris waveguide filters for satellite communicationTELKOMNIKA JOURNAL
We propose in this paper, two bandpass filters in waveguide technology having rectangular symmetrical discontinuities with a half-radius r, designed and operating respectively in the X-Band (9-11.5) GHz and C-Band (3.5-5.5) GHz. These filters consists of eight irises placed symmetrically respectively on standard rectangular waveguides WR90 and WR229 in which resonant irises are inserted. These irises are used to couple the sections very strongly in this filter, which allows the bandwidth to be increased and the matching to be controlled. The comparison between the numerical and electromagnetic results, which we obtained for the filters, constitutes a means of validation of computer simulation technology (CST) environment and Mician for the design of the other circuit elements in the various frequency bands. We observed excellent consistency between the simulation curves and those of the measurements. The results obtained are promising and pave the way for the use of these structures in the fields of telecommunications.
Control Radiation Pattern for Half Width Microstrip Leaky Wave Antenna by Usi...IJECEIAES
In this paper, a novel design for single-layer half width microstrip leakywave antenna (HW-MLWA) is demonstrated. This model can be digitally control its radiation pattern at operation frequency and uses only two values of the bias voltage, with better impedance matching and insignificant gain variation. The scanning and controlling the radiation pattern of leaky-wave antennas (LWA) in steps at an operation frequency, by using switches PIN diodes, is investigated and a novel HW-MLWA is introduced. A control cell reconfigurable, that can be switched between two states, is the basic element of the antenna. The periodic LWA is molded by identical control cells where as a control radiation pattern is developed by combining numerous reconfigurable control cells. A gap capacitor is independently connected or disconnected in every unit cell by using a PIN diode switch to achieve fixedfrequency control radiation pattern scanning. The profile reactance at the free edge of (HWMLWA) and thus the main lobe direction is altered by changing the states of the control cell. The antenna presented in this paper, can scan main beam between 18o to 44o at fixed frequency of 4.2 GHz with measured peak gain of 12.29 dBi.
MLI Power Topologies and Voltage Eminence: An Exploratory Reviewijeei-iaes
Due to their performances and inherent edges, particularly in medium-voltage and dynamic applications, multilevel inverters have received associate degree increasing attention in universe industrial applications. This paper deals with a review of the most structure electrical converter topologies additionally their commonest derived and hybrid structures quoted in previous analysis works. It additionally encompasses associate degree investigation on voltage harmonic elimination and THD estimation. For that reason, the paper summarizes the foremost relevant modulation techniques used to date to boost the output voltage quality. Theoretical formulas elicited within the literature, for calculating the output voltage THD higher and lower bounds area unit reportable and verified by adequate simulations.
An electric power system is a network of electrical components deployed to supply, transfer, and use electric power. ... The majority of these systems rely upon three-phase AC power—the standard for large-scale power transmission and distribution across the modern world.
Analysis of Stranded Multi-Conductor Cable in Multilayered Dielectric MediaJimmi James
ABSTRACT
Due to complexity of electromagnetic modeling, researchers and scientists always look for development of accurate and fast methods to extract the parameters of electronic transmission cables. These parameters play a critical role in various applications like electro surgery, fault location in cables and many more. In this paper, the modeling of stranded multiconductor cable in multilayered dielectric media is illustrated. We specifically determine the distributed parameters of two wire transmission lines in two-layered dielectric media. The effect of frequency change on the parameters is also discussed. This numerical analysis was successfully implemented for modeling of a cable which connects the hand piece of an electro surgical device to its generator. Comparison of the theoretical and the practically measured results is demonstrated with good agreements.
DISTRIBUTION OF ELECTRIC FIELD ANALYSIS IN 36 KV ROOF TOP BUSHING BY USING FE...Journal For Research
The electric field distribution in medium voltage roof top bushing is principally dependent on the geometry dimension and types of the materials used. The main target is to achieve a bushing design which has a good field stress control. Various combinations of conductive, insulated and earthed parts, connected with the bushing have been treated in the development phase. In this paper, two-dimensional (2D) axial-symmetrical model geometries of roof top bushing have been developed using finite element analysis (FEA) method, which is ANSYS MAXWELL software. These models have been used to obtain the electric filed distribution in roof top bushing model. The effect of the bushing permittivity, electrical conductivity, the width, length and the metallic interface on the electric field distribution in roof bushing structure were analysed. From this study, an understanding of electric field distribution in roof top bushing geometry may be attained, which may help in designing of medium voltage roof top bushing stress control. With the help of simulation result proposed the new design of roof top bushing and it is verified by different test.
Fea of pcb multilayer stack up high voltage planar transformer for aerospace...elelijjournal
High voltage planar transformer is a technology which can replace conventional transformer with its distinct advantages of saturation and cost efficiency. This paper includes, study and solution methods for PCB winding configuration in planar magnetic elements with multilayer
stack up of PCB Cu-tracks, producing High voltage power supply for aerospace application.With finite element analysis (FEA) simulations, different simulation outcomes are discussed for inspecting flux intensity and current density distribution with computing Electric field strength
and Magnetic fields. In principal conclusion of study, complete analysis and some practical design guidelines for
multilayer PCB stack up are discussed in this paper.
Geometric and process design of ultra-thin junctionless double gate vertical ...IJECEIAES
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
2. 3318 IEEE TRANSACTIONS ON MAGNETICS, VOL. 46, NO. 8, AUGUST 2010
Fig. 1. Unifilar diagram of the 3-phase system. Fig. 5. Cross sections used to represent the variation of relative position.
C. Methodology: 2-D FE Model Transposition
In this way, the cable performance is evaluated using 2-D
finite element models coupled to the transposed multiple seg-
ments technique (transposition) [4]. In the particular case of UC,
the interchanges are obtained performing various 2-D steady-
state analyses considering several cross sections to model the
different relative positions between the power cables and the
metallic components.
D. Least Common Multiple (LCM)
Fig. 2. Cross-sections number 1 of the configuration A and B. As described in Section II, the inner layer of this UC com-
pletes 1 turn every 1000 mm while its outer layer completes 1
turn every 1500 mm. The LCM between the layer lengths is then
3000 mm. In other words, there is a repetition of the cable pat-
tern every 3000 mm.
E. Accuracy of the Analysis Method
The number of cross sections defines the accuracy which is
linked to the LCM of the cable layers, as shown in Fig. 5. For
this UC one has compared the results for two values of cross
sections number ( and ) and the difference was
not significant. Fig. 7(a) presents 3 of the 50 cross sections used
to compute the simulations of the configuration A and B.
Fig. 3. Cross-sections number 1 of the configuration C. F. 2-D Finite Element Analysis
From the electromagnetism theory, the induced voltage in one
conductor increases proportionally with the level and the fre-
quency of the current of the surrounded conductors. The con-
verters supply the oil pumps with a constant relation between
voltage and frequency. Considering the operation characteris-
tics, one of the worst conditions is when 3 circuits #1, #2 and #3
supply the pumps on 80 Hz and 1 circuit #4 supplies on 30 Hz.
The general idea of the methodology is summarized in Fig. 6.
Fig. 4. Transmission Lines phase transposition. The computational package FLUX-2-D [6] is used to evaluate
each cross section the configurations.
the variation of the relative position between the metallic cable IV. UMBILICAL CABLE ANALYSIS
components.
In order to compare the performance of the UC with the eval-
B. Transposition Technique uation of the coupling effects between the internal components,
three different configurations are verified:
The concept of transposition is addressed in classical 3-phase • Configuration A: the tubes and the power circuits turn
high voltage transmission lines (TL) theory [4], [5]. The idea is around the cable center, but the power circuits do not turn
to change the position of phases through the TL length, aiming around their own centers, as in Fig. 7(a).
to obtain balanced values for the TL parameters (inductances, • Configuration B: the tubes and the power circuits turn
capacitances and so on). The TL parameters are then calculated around the cable center and the power circuits turn also
from the average values on each phase. Fig. 4 illustrates a TL around their own centers, completing 1 turn every 750
transposition with three interchanges with lengths L/3. mm, as shown in Fig. 7(b).
3. SALLES et al.: ELECTROMAGNETIC ANALYSIS OF SUBMARINE UMBILICAL CABLES 3319
Fig. 8. Magnetic potential lines obtained for the cross section 1 of the Config-
uration A and B (only the first cross section has the same values). (a) 80 Hz,
(b) 30 Hz.
Fig. 6. General steps of the methodology.
Fig. 9. Real components of induced voltage (80 Hz) in phase C of circuit
#4—Configuration A.
Fig. 7. Cross sections along the length of configurations A (a) and B (b).
• Configuration C: the tubes and the power circuits turn
around the cable center (Fig. 3).
Due to the magnetic permeability of the armor ( u0),
the boundary conditions were defined considering a tangential
magnetic field in the outer diameter of the UC. The supply cir-
cuits are modeled with ideal 3-phase voltage sources and the oil
pumps are modeled as a pure resistive load of eight ohms on
each phase. The circuit coupling represents each finite element
region (power conductors, power shields, tubes and armor) by
an electric circuit component.
A. Terminal Voltage Computation
Fig. 10. Imaginary components of induced voltage (80 Hz) in phase C of circuit
Fig. 8(a) shows the equipotential lines obtained from the anal- #4—Configuration A.
ysis of the circuits #1, #2 and #3 supplied on 80 Hz. Fig. 8(b)
shows the analysis of circuit #4 supplied on 30 Hz. These two
separately analyses are necessary to determine the influence of
Fig. 12. The induced voltage in configuration C (not showed)
the 80 Hz on the 30 Hz circuits for frequency domain simulation.
has similar performance of configuration A.
The converter voltages of each phase A of the 3-phase circuits
are at its maximum value.
B. Power Quality Analysis
The average values of the real and the imaginary components
of terminal voltage of the circuit #4 are calculated considering Voltage modulation indicates the induced voltage level in a
each cross section. The terminal voltage of the configuration A phase of a circuit by the surrounding circuits. The computation
and B obtained by the combined methodology are shown from of the induced voltage on phase A of circuit as a result of
Figs. 9 to 12. current flowing through circuit can be calculated individually
The induced voltages are almost constant for the configura- by the (1), (2) and (3)
tion A, as shown in Fig. 9 and in Fig. 10. For the configuration
B, the rotation of the 3-phase power circuits around their own
centers results on a variable induced voltage along the length (1)
of the UC which compensates itself, as shown in Fig. 11 and in
4. 3320 IEEE TRANSACTIONS ON MAGNETICS, VOL. 46, NO. 8, AUGUST 2010
TABLE II
SIMULATION DATA OF DIMENSIONS AND MATERIAL PROPERTIES
Fig. 11. Real components of induced voltage (80 Hz) in phase C of circuit Configuration B is the most appropriate one which guarantee
#4—Configuration B. the balanced voltage at the load terminals and the low level of
modulation on the most sensible circuit (30 Hz).
V. CONCLUSION
The combined methodology presented in this paper enables
the evaluation of the power quality of UC using 2-D steady-
state models, without compromising the accuracy of the results.
One has verified that the rotation of the power circuits results
in a reduction of the voltage modulation. These characteristics
will also guarantee a better oil pump operation, diminishing the
maintenance and enlarging the lifetime.
This analysis gives faster results compared to 3-D steady-
state or 2-D transient. Besides that, the results of the 2-D tran-
sient analysis (not showed in this paper) for the configuration
B are very similar to the one obtained by the frequency domain
analysis. Even thought this methodology mainly analyses the in-
duced voltage in the circuit #4 by the others 3 circuits, different
analysis could also be done modifying the last two steps of the
Fig. 12. Imaginary components of induced voltage (80 Hz) in phase C of circuit Fig. 6, for example, to “loss computation” or “thermal analysis”.
#4—Configuration B.
APPENDIX
TABLE I The main data of the cable geometry and the material prop-
VOLTAGE MODULATION IN THE 30 HZ CIRCUIT (%) erties are given in Table II.
ACKNOWLEDGMENT
The authors gratefully acknowledge the financial support
from the Brazilian government via FAPESP (State of São
Paulo Research Foundation), CNPq (National Counsel of
Technological and Scientific Development) and CAPES (“Co-
ordenação de Aperfeiçoamento de Pessoal de Nível Superior,”
in Portuguese).
Computing total rms voltage on phase A of circuit
, defining as load terminal voltage at fundamental
frequency of circuit REFERENCES
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[4] W. D. Stevenson, Elements of Power System Analysis. New York:
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