This document describes a study of hot carrier damage in laterally diffused nMOSFET (LDMOS) devices. The researchers developed a new methodology using charge pumping measurements to estimate the spatial distribution of hot carrier damage in the devices. They applied constant drain voltage stresses to the devices and measured changes in device parameters and charge pumping curves. They then used a model assuming exponential damage profiles matching simulations of impact ionization rates. By fitting the model to experimental charge pumping data, they were able to extract the interface trap densities and trapped charge distributions as a function of stress conditions and injected charge amount. The methodology provided good agreement with measurements and improved understanding of degradation mechanisms in these high voltage devices.
An analytical model for the current voltage characteristics of GaN-capped AlG...IJECEIAES
We present an analytical model for the I-V characteristics of AlGaN/GaN and AlInN/GaN high electron mobility transistors (HEMT). Our study focuses on the influence of a GaN capping layer, and of thermal and self-heating effects. Spontaneous and piezoelectric polarizations at Al(Ga,In)N/GaN and GaN/Al(Ga,In)N interfaces have been incorporated in the analysis. Our model permits to fit several published data. Our results indicate that the GaN cap layer reduces the sheet density of the twodimensional electron gas (2DEG), leading to a decrease of the drain current, and that n + -doped GaN cap layer provides a higher sheet density than undoped one. In n + GaN/AlInN/GaN HEMTs, the sheet carrier concentration is higher than in n + GaN/AlGaN/GaN HEMTs, due to the higher spontaneous polarization charge and conduction band discontinuity at the substrate/barrier layer interface.
An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET...VLSICS Design
In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations.
Effect of mesh grid structure in reducing hot carrier effect of nmos device s...ijcsa
This paper presents the critical effect of mesh grid that should be considered during process and device
simulation using modern TCAD tools in order to develop and optimize their accurate electrical
characteristics. Here, the computational modelling process of developing the NMOS device structure is
performed in Athena and Atlas. The effect of Mesh grid on net doping profile, n++, and LDD sheet
resistance that could link to unwanted “Hot Carrier Effect” were investigated by varying the device grid
resolution in both directions. It is found that y-grid give more profound effect in the doping concentration,
the junction depth formation and the value of threshold voltage during simulation. Optimized mesh grid is
obtained and tested for more accurate and faster simulation. Process parameter (such as oxide thicknesses
and Sheet resistance) as well as Device Parameter (such as linear gain “beta” and SPICE level 3 mobility
roll-off parameter “ Theta”) are extracted and investigated for further different applications.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
Effects of Scaling on MOS Device Performanceiosrjce
This paper presents effects on MOS transistor performance due to scaling of its dimensions. Scaling
theory deals with the change in the device characteristics with the decrease in the dimensions of a MOS
transistor. MOS transistors are continuously scaled down due to the desire for high density and high
functionality VLSI chips. The driving forces behind these developments are increasing the demand for portable
systems requiring high throughput and high integration capacity. Effects of scaling on the performance
characteristics of a MOS device are analyzed in this paper
An analytical model for the current voltage characteristics of GaN-capped AlG...IJECEIAES
We present an analytical model for the I-V characteristics of AlGaN/GaN and AlInN/GaN high electron mobility transistors (HEMT). Our study focuses on the influence of a GaN capping layer, and of thermal and self-heating effects. Spontaneous and piezoelectric polarizations at Al(Ga,In)N/GaN and GaN/Al(Ga,In)N interfaces have been incorporated in the analysis. Our model permits to fit several published data. Our results indicate that the GaN cap layer reduces the sheet density of the twodimensional electron gas (2DEG), leading to a decrease of the drain current, and that n + -doped GaN cap layer provides a higher sheet density than undoped one. In n + GaN/AlInN/GaN HEMTs, the sheet carrier concentration is higher than in n + GaN/AlGaN/GaN HEMTs, due to the higher spontaneous polarization charge and conduction band discontinuity at the substrate/barrier layer interface.
An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET...VLSICS Design
In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations.
Effect of mesh grid structure in reducing hot carrier effect of nmos device s...ijcsa
This paper presents the critical effect of mesh grid that should be considered during process and device
simulation using modern TCAD tools in order to develop and optimize their accurate electrical
characteristics. Here, the computational modelling process of developing the NMOS device structure is
performed in Athena and Atlas. The effect of Mesh grid on net doping profile, n++, and LDD sheet
resistance that could link to unwanted “Hot Carrier Effect” were investigated by varying the device grid
resolution in both directions. It is found that y-grid give more profound effect in the doping concentration,
the junction depth formation and the value of threshold voltage during simulation. Optimized mesh grid is
obtained and tested for more accurate and faster simulation. Process parameter (such as oxide thicknesses
and Sheet resistance) as well as Device Parameter (such as linear gain “beta” and SPICE level 3 mobility
roll-off parameter “ Theta”) are extracted and investigated for further different applications.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
Effects of Scaling on MOS Device Performanceiosrjce
This paper presents effects on MOS transistor performance due to scaling of its dimensions. Scaling
theory deals with the change in the device characteristics with the decrease in the dimensions of a MOS
transistor. MOS transistors are continuously scaled down due to the desire for high density and high
functionality VLSI chips. The driving forces behind these developments are increasing the demand for portable
systems requiring high throughput and high integration capacity. Effects of scaling on the performance
characteristics of a MOS device are analyzed in this paper
Circuit-based method for extracting the resistive leakage current of metal ox...journalBEEI
Resistive leakage current based condition assessment of metal oxide surge arrester (MOSA) is one of the most extensively employed technique to monitor its degradation. An extraction method is customarily required to extract the resistive component from the total leakage current. The existing methods to extract the resistive current are complex and less accurate. Therefore, this paper describes a simple and accurate circuit-based method to extract the resistive current using equivalent model and measured leakage current of the arrester. The accuracy of the proposed method is validated through experimental results on ABB’s 120 kV surge arrester, EMTP and QuickField software simulations. The performance of the method is also analyzed and verified experimentally on 72, 180 and 240 kV rated ABB’s surge arresters. The obtained results of resistive leakage current have shown the maximum error of 0.001%. Simple and easier computational steps with higher accuracy are the key benefits of the proposed technique.
This paper presents a study on a new full bridge series resonant converter (SRC) with wide zero voltage switching (ZVS) range, and higher output voltage. The high frequency transformer is connected in series with the LC series resonant tank. The tank inductance is therefore increased; all switches having the ability to turn on at ZVS, with lower switching frequency than the LC tank resonant frequency. Moreover, the step-up high frequency (HF) transformer design steps are introduced in order to increase the output voltage to overcome the gain limitation of the conventional SRC. Compared to the conventional SRC, the proposed converter has higher energy conversion, able to increase the ZVS range by 36%, and provide much higher output power. Finally, the a laboratory prototypes of the both converters with the same resonant tank parameters and input voltage are examined based on 1 and 2.2 kW power respectively, for veryfing the reliability of the performance and the operation principles of both converters.
Reduced Dielectric Losses for Underground Cable Distribution SystemsIJAPEJOURNAL
This paper describes the process to reduce dielectric losses for underground cable distribution system. As already known, that system is an alternative solution to energy distribution systems in urban areas. Influence of large capacitance is a separate issue that needs to be resolved.
Large capacitance effect on Express Feeder of 10 miles long has resulted in power losses more than 100 MW per month. In the no-load condition, current dispatch has recorded 10 Amperes, and has increased the voltage at receiving end by 200-500 Volts, with leading power factors.
Installation of the inductor to reduce cable loss dielectrics is done by changing the power factor (pf) to 0.85 lagging. After installation of the inductor, which is 5 mH/700 kVAR, dielectric losses is reduced to 3.57%, which is from 105,983 kW to 102,195 kWh per month. The capacitive leakage current has also been reduced from 249.61 Ampere to 245.17 Ampere.
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Effect of Passive Damping on the Performance of Buck Converter for Magnet Loadpaperpublications3
Abstract: A DC to DC converter is a lossless dc transformer that supply regulated output voltage under varying load and input voltage condition and also the converter parameter values changes with time and physical quantity like temperature etc. This paper presents the design and simulation of an open loop buck converter for magnet load using Simulink and Sim Power System library of MATLAB.
SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylin...IJECEIAES
We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length L g and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/L g ) 10 -7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.
Effect of Mobility on (I-V) Characteristics of Gaas MESFET Yayah Zakaria
We present in this paper an analytical model of the current–voltage (I-V) characteristics for submicron GaAs MESFET transistors. This model takes into account the analysis of the charge distribution in the active region and incorporate a field depended electron mobility, velocity saturation and charge
build-up in the channel. We propose in this frame work an algorithm of simulation based on mathematical expressions obtained previously. We propose a new mobility model describing the electric field-dependent. predictions of the simulator are compared with the experimental data [1] and
have been shown to be good.
Converter Transformers manufactured to the Slovenian RailwaysJuso Ikanovic
The paper contains an overview of the most significant
technical characteristics of converter transformers
manufactured to modernize of Slovenian Railways. The main
features and characteristics of this type of the traction drives
with various intersected winding configurations are described.
The referenced projects include the first application of axial
winding crossing, i.e. a technological innovation resolving the
strong magnetic coupling requirement of low-voltage
windings. The solution is referred to as an intersected winding.
With one, two and three winding crossings coupling factors of
0.920 and 0.967 are achieved. The results meet the
specifications, of the SIST EN standard.
Deterioration of short channel effectsijistjournal
In the proposed work, the analytical model for Surface potential and Electric field has been carried out in a
novel structure named dual halo triple material Surrounding-gate metal-oxide-semiconductor field effect
transistor (DHTMSG). The new device has been incorporated with symmetrical dual halo regions near
source and drain ends, while the gate terminal consists of three different metals with different work
functions. The results prove that the device significantly deteriorates the short channel effects which are
studied by analytical model for surface potential and electric field using parabolic approximation method.
The analytical results are endorsed by the simulation results.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Plasma generator: design of six stage cockcroft-walton voltage multiplier 12 ...TELKOMNIKA JOURNAL
Cockcroft-Walton (CW) voltage multiplier is a voltage booster circuit with an array of series-connected only diodes and capacitors. In this research, voltage multiplier is designed to generate voltage up to 12 kV that the modified 6-stage constructed generator. It is designed as circuit charger of storage capacitor (CS) to generate combination wave impulse application which following standard those set in IEC (International Electrotecnical Commission) 61000-4-5 class 4. CS should be charged up to 4 kV according this standard. High impulse voltage and current works repeatedly in a short time, so the charging system is expected to reach targeted voltage within a maximum time of 10 seconds. Besides charging is also required to design of circuit discharger for discharging electric charge inside the CS. It is expected to reach 0 kV within a maximum time of 15 seconds with overdamped technique. There are three results of the research projects such as output voltage of CW voltage multiplier before connecting CS, charging time of CS, and discharging time of CS. The result showed that CW voltage multiplier can generate up to 12.01 kV on simulation and 11.9 kV on experiment. CS can be charged up to 4 kV in 9.8 seconds on simulation and 7.9 seconds on experiment. CS can be discharged in 14.2 seconds on simulation and 10 seconds on experiment. These results are in accordance with the expectation.
Analysis Of 3C-Sic Double Implanted MOSFET With Gaussian Profile Doping In Th...IJRES Journal
The present work aims at the design of 3C-SiC Double Implanted Metal Oxide Semiconductor Field Effect Transistor (DIMOSFET) with Gaussian doping profile in drift region for high breakdown voltages. By varying the device height ‘h’, function constant m and peak concentration 𝑁0, analysis has been done for an optimum profile for high breakdown voltage. With Gaussian profile peak concentration 𝑁0 = 1016 𝑐𝑚−3 at drain end and m as 1.496 ×10−2cm, highest breakdown voltage of 6.84kV has been estimated with device height of 200μm.
Sensoring Leakage Current to Predict Pollution Levels to Improve Transmission...Yayah Zakaria
Pollution insulator is a serious threat to the safety operations of electric power systems. Leakage current detection is widely employed in transmission line insulators to assess pollution levels. This paper presents the prediction of pollution levels on insulators based on simulated leakage current and voltage in a transmission tower.The simulation parameters are based on improved transmission line model with leakage current resistance insertion between buses. Artificial neural network (ANN) is employed to predict the level of pollution with different locations of simulated leakage current and voltage between two buses. With a sufficient number of training, the test results showed a significant potential for pollution level prediction
with more than 95% Correct Classification Rate (CCR) and output of the ANN showed high agreement with Simulink results.
Circuit-based method for extracting the resistive leakage current of metal ox...journalBEEI
Resistive leakage current based condition assessment of metal oxide surge arrester (MOSA) is one of the most extensively employed technique to monitor its degradation. An extraction method is customarily required to extract the resistive component from the total leakage current. The existing methods to extract the resistive current are complex and less accurate. Therefore, this paper describes a simple and accurate circuit-based method to extract the resistive current using equivalent model and measured leakage current of the arrester. The accuracy of the proposed method is validated through experimental results on ABB’s 120 kV surge arrester, EMTP and QuickField software simulations. The performance of the method is also analyzed and verified experimentally on 72, 180 and 240 kV rated ABB’s surge arresters. The obtained results of resistive leakage current have shown the maximum error of 0.001%. Simple and easier computational steps with higher accuracy are the key benefits of the proposed technique.
This paper presents a study on a new full bridge series resonant converter (SRC) with wide zero voltage switching (ZVS) range, and higher output voltage. The high frequency transformer is connected in series with the LC series resonant tank. The tank inductance is therefore increased; all switches having the ability to turn on at ZVS, with lower switching frequency than the LC tank resonant frequency. Moreover, the step-up high frequency (HF) transformer design steps are introduced in order to increase the output voltage to overcome the gain limitation of the conventional SRC. Compared to the conventional SRC, the proposed converter has higher energy conversion, able to increase the ZVS range by 36%, and provide much higher output power. Finally, the a laboratory prototypes of the both converters with the same resonant tank parameters and input voltage are examined based on 1 and 2.2 kW power respectively, for veryfing the reliability of the performance and the operation principles of both converters.
Reduced Dielectric Losses for Underground Cable Distribution SystemsIJAPEJOURNAL
This paper describes the process to reduce dielectric losses for underground cable distribution system. As already known, that system is an alternative solution to energy distribution systems in urban areas. Influence of large capacitance is a separate issue that needs to be resolved.
Large capacitance effect on Express Feeder of 10 miles long has resulted in power losses more than 100 MW per month. In the no-load condition, current dispatch has recorded 10 Amperes, and has increased the voltage at receiving end by 200-500 Volts, with leading power factors.
Installation of the inductor to reduce cable loss dielectrics is done by changing the power factor (pf) to 0.85 lagging. After installation of the inductor, which is 5 mH/700 kVAR, dielectric losses is reduced to 3.57%, which is from 105,983 kW to 102,195 kWh per month. The capacitive leakage current has also been reduced from 249.61 Ampere to 245.17 Ampere.
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Effect of Passive Damping on the Performance of Buck Converter for Magnet Loadpaperpublications3
Abstract: A DC to DC converter is a lossless dc transformer that supply regulated output voltage under varying load and input voltage condition and also the converter parameter values changes with time and physical quantity like temperature etc. This paper presents the design and simulation of an open loop buck converter for magnet load using Simulink and Sim Power System library of MATLAB.
SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylin...IJECEIAES
We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length L g and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/L g ) 10 -7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.
Effect of Mobility on (I-V) Characteristics of Gaas MESFET Yayah Zakaria
We present in this paper an analytical model of the current–voltage (I-V) characteristics for submicron GaAs MESFET transistors. This model takes into account the analysis of the charge distribution in the active region and incorporate a field depended electron mobility, velocity saturation and charge
build-up in the channel. We propose in this frame work an algorithm of simulation based on mathematical expressions obtained previously. We propose a new mobility model describing the electric field-dependent. predictions of the simulator are compared with the experimental data [1] and
have been shown to be good.
Converter Transformers manufactured to the Slovenian RailwaysJuso Ikanovic
The paper contains an overview of the most significant
technical characteristics of converter transformers
manufactured to modernize of Slovenian Railways. The main
features and characteristics of this type of the traction drives
with various intersected winding configurations are described.
The referenced projects include the first application of axial
winding crossing, i.e. a technological innovation resolving the
strong magnetic coupling requirement of low-voltage
windings. The solution is referred to as an intersected winding.
With one, two and three winding crossings coupling factors of
0.920 and 0.967 are achieved. The results meet the
specifications, of the SIST EN standard.
Deterioration of short channel effectsijistjournal
In the proposed work, the analytical model for Surface potential and Electric field has been carried out in a
novel structure named dual halo triple material Surrounding-gate metal-oxide-semiconductor field effect
transistor (DHTMSG). The new device has been incorporated with symmetrical dual halo regions near
source and drain ends, while the gate terminal consists of three different metals with different work
functions. The results prove that the device significantly deteriorates the short channel effects which are
studied by analytical model for surface potential and electric field using parabolic approximation method.
The analytical results are endorsed by the simulation results.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Plasma generator: design of six stage cockcroft-walton voltage multiplier 12 ...TELKOMNIKA JOURNAL
Cockcroft-Walton (CW) voltage multiplier is a voltage booster circuit with an array of series-connected only diodes and capacitors. In this research, voltage multiplier is designed to generate voltage up to 12 kV that the modified 6-stage constructed generator. It is designed as circuit charger of storage capacitor (CS) to generate combination wave impulse application which following standard those set in IEC (International Electrotecnical Commission) 61000-4-5 class 4. CS should be charged up to 4 kV according this standard. High impulse voltage and current works repeatedly in a short time, so the charging system is expected to reach targeted voltage within a maximum time of 10 seconds. Besides charging is also required to design of circuit discharger for discharging electric charge inside the CS. It is expected to reach 0 kV within a maximum time of 15 seconds with overdamped technique. There are three results of the research projects such as output voltage of CW voltage multiplier before connecting CS, charging time of CS, and discharging time of CS. The result showed that CW voltage multiplier can generate up to 12.01 kV on simulation and 11.9 kV on experiment. CS can be charged up to 4 kV in 9.8 seconds on simulation and 7.9 seconds on experiment. CS can be discharged in 14.2 seconds on simulation and 10 seconds on experiment. These results are in accordance with the expectation.
Analysis Of 3C-Sic Double Implanted MOSFET With Gaussian Profile Doping In Th...IJRES Journal
The present work aims at the design of 3C-SiC Double Implanted Metal Oxide Semiconductor Field Effect Transistor (DIMOSFET) with Gaussian doping profile in drift region for high breakdown voltages. By varying the device height ‘h’, function constant m and peak concentration 𝑁0, analysis has been done for an optimum profile for high breakdown voltage. With Gaussian profile peak concentration 𝑁0 = 1016 𝑐𝑚−3 at drain end and m as 1.496 ×10−2cm, highest breakdown voltage of 6.84kV has been estimated with device height of 200μm.
Sensoring Leakage Current to Predict Pollution Levels to Improve Transmission...Yayah Zakaria
Pollution insulator is a serious threat to the safety operations of electric power systems. Leakage current detection is widely employed in transmission line insulators to assess pollution levels. This paper presents the prediction of pollution levels on insulators based on simulated leakage current and voltage in a transmission tower.The simulation parameters are based on improved transmission line model with leakage current resistance insertion between buses. Artificial neural network (ANN) is employed to predict the level of pollution with different locations of simulated leakage current and voltage between two buses. With a sufficient number of training, the test results showed a significant potential for pollution level prediction
with more than 95% Correct Classification Rate (CCR) and output of the ANN showed high agreement with Simulink results.
Sensoring Leakage Current to Predict Pollution Levels to Improve Transmission...IJECEIAES
Pollution insulator is a serious threat to the safety operations of electric power systems. Leakage current detection is widely employed in transmission line insulators to assess pollution levels. This paper presents the prediction of pollution levels on insulators based on simulated leakage current and voltage in a transmission tower.The simulation parameters are based on improved transmission line model with leakage current resistance insertion between buses. Artificial neural network (ANN) is employed to predict the level of pollution with different locations of simulated leakage current and voltage between two buses. With a sufficient number of training, the test results showed a significant potential for pollution level prediction with more than 95% Correct Classification Rate (CCR) and output of the ANN showed high agreement with Simulink results.
Effect of Mobility on (I-V) Characteristics of Gaas MESFET IJECEIAES
We present in this paper an analytical model of the current–voltage (I-V) characteristics for submicron GaAs MESFET transistors. This model takes into account the analysis of the charge distribution in the active region and incorporate a field depended electron mobility, velocity saturation and charge build-up in the channel. We propose in this frame work an algorithm of simulation based on mathematical expressions obtained previously. We propose a new mobility model describing the electric field-dependent. The predictions of the simulator are compared with the experimental data [1] and have been shown to be good.
Modeling of solar array and analyze the current transientEditor Jacotech
Spacecraft bus voltage is regulated by power
conditioning unit using switching shunt voltage regulator having
solar array cells as the primary source of power. This source
switches between the bus loads and the shunt switch for fine
control of spacecraft bus voltage. The effect of solar array cell
capacitance [5][6] along with inductance and resistance of the
interface wires between solar cells and power conditioning
unit[1], generates damped sinusoidal currents superimposed on
the short circuit current of solar cell when shunted through
switch. The peak current stress on the shunt switch is to be
considered in the selection of shunt switch in power conditioning
unit. The analysis of current transients of shunt switch in PCU
considering actual spacecraft interface wire length by
illumination of solar panel (combination of series and parallel
solar cells) is difficult with hardware simulation. Software
simulation by modeling solar cell is carried out for a single string
(one parallel) in Pspice [6]. Since in spacecrafts number of
parallels and interface cable length are variable parameters the
analysis of current transients of shunt switch is carried out by
modeling solar array with the help of solar cell model[6] for the
actual spacecraft condition.
Modeling of solar array and analyze the current transient response of shunt s...Editor Jacotech
Spacecraft bus voltage is regulated by power
conditioning unit using switching shunt voltage regulator having
solar array cells as the primary source of power. This source
switches between the bus loads and the shunt switch for fine
control of spacecraft bus voltage. The effect of solar array cell
capacitance [5][6] along with inductance and resistance of the
interface wires between solar cells and power conditioning
unit[1], generates damped sinusoidal currents superimposed on
the short circuit current of solar cell when shunted through
switch. The peak current stress on the shunt switch is to be
considered in the selection of shunt switch in power conditioning
unit. The analysis of current transients of shunt switch in PCU
considering actual spacecraft interface wire length by
illumination of solar panel (combination of series and parallel
solar cells) is difficult with hardware simulation. Software
simulation by modeling solar cell is carried out for a single string
(one parallel) in Pspice [6]. Since in spacecrafts number of
parallels and interface cable length are variable parameters the
analysis of current transients of shunt switch is carried out by
modeling solar array with the help of solar cell model[6] for the
actual spacecraft condition.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
At the applied voltage a disc-shaped cavity with partial discharges are measured at variable frequency (0.01-50 Hz). By varying the frequency it was observed that measured PD phase, magnitude of distributions and number of PDs per voltage cycles are varied. In the cavity, sequence of Partial discharge is simulated dynamically. For that purpose a model is presented with charge consistent. Simulated results shows that cavity surface and emission properties are effected by varying the magnitude of applied frequency, mainly conductivity of surface. This paper is illustrating the frequency dependence of PD in a cavity. The paper illustrates how the applied voltage amplitude and the cavity size can influence the frequency dependence PD activity.
Novel technique in charactarizing a pv module using pulse width modulatoreSAT Journals
Abstract The fabrication and characterization of PV modules are always done under standard test conditions (STC). However, The condition of operation are often far from thisstandard conditions. As a result, developing a characterization circuit is considered as a point of interest for researchers.This paper presents a new methodology in characterizing a PV module using an electronic load circuit. The circuit is implemented using a power MOSFET driven by a pulse width modulator (PWM) developed by LABVIEW. The system is tested and its results are validated by comparing it with simulation results performed by Comsol Multiphysics and Matlab. The system shows high accuracy with respect to the previous published work with lower cost and higher simplicity. Keywords: Photovoltaic, Characterization, Electronic load, and Pulse width modulation (PWM)…
Analysis of Electric Circuit Model on Atmospheric Pressure Dielectric Barrier...AM Publications
Analysis of Electric Circuit Model on Atmospheric Pressure Dielectric Barrier Discharge (DBD) Plasma has been simulated using the Simulink-Matlab R2010a software. Plasma reactor being used as the basis to determine the parameters in the circuit is in the coaxial form made of pyrex glass with an iron rod as the active electrode and spiral copper wire as passive electrode. The reactor was filled with argon gas with the flow rate of 2 L/s. Simulation circuit model which was prepared based on a DBD equivalent circuit, operated in a voltage range of 1.0 kV to 6.0 kV for frequency of 10 kHz to 66 kHz. Electrical characterization was performed to describe the plasma discharge that occurs in the reactor. The datas of supply voltage and current, as well as voltage and current discharge, was used to determine the average power during one period. From the simulation was obtained an increase in supply and discharge currents with increasing of frequency at the same operating voltage. Discharge power has increased in a specific voltage and increased frequency. It is obtained the average discharge power for 5.5 kV of 11.28 W and 10.90 W at a frequency of 21 kHz and 24 kHz, respectively. The highest efficiency obtained from the simulation that achieved at voltage of 1 kV and frequency of 45.7 kHz is equal to 56.59%.
ANALYSIS OF LIGHTNING STRIKE WITH CORONA ON OHTL NEAR THE SUBSTATION BY EMTP ADEIJ Journal
Lightning protection and insulation coordination of transmission lines and substations require an accurate
knowledge of the magnitudes and waveforms of lightning overvoltage. To simulate the lightning
overvoltage precisely near the substation, this study has shown how to consider the lightning impulse
corona for distortion effect of this overvoltage.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Lightning Characteristics and Impulse Voltage.Milton Sarker
Lightning characteristics and standard impulse
waveform are related to each other. But the lack
of realization about the relation between them
would make the solution to produce better
protection against lightning surge becomes
harder. Natural lightning surge waveform has
been compared to standard impulse waveform as
evidence that there have similarity between
them. The standard impulse waveform could be
used to test the strength of electrical equipment
against the lightning. Therefore designing and
simulating the impulse generator are the purpose
of this project beside to get better understanding
about lightning characteristics. This project aims
to develop an impulse generator circuit. The
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Mitigation of high voltage induction effect on ICCP system of gas pipelines: ...TELKOMNIKA JOURNAL
An analysis of the high voltage induction effect on the impressed current cathodic protection (ICCP) system on pipelines parallel toward high voltage power lines was employed in this research. Mitigation of high voltage effect throught human and environment is necessary to implemented. Direct current induction was used to increase the electrical potential of the gas pipeline, from Klumpang to sicanang area, Indonesia. During the mitigation process, the highest induction value was obtained 0.00574 KV which is previously was 0.01732 KV, and occurred at the limit of the allowable secure touch tension value of 0.015 KV. The data that acquire from the measurement of test point of ICCP underneath the transmission line revealed a comparison data between field measurements occurred of mitigation process. The direct current induction method is found to be safe for ICCP system and environment.
Measurement of the hot carrier damage profile in LDMOS devices stressed at high drain voltage
1. Measurement of the hot carrier damage profile in LDMOS
devices stressed at high drain voltage
D. Corso a,*, S. Aurite a
, E. Sciacca a
, D. Naso a
, S. Lombardo a
, A. Santangelo b
,
M.C. Nicotra b
, S. Cascino b
a
CNR-IMM, Stradale Primosole, 50, 95121 Catania, Italy
b
STMicroelectronics, Stradale Primosole, 50, 95121 Catania, Italy
Available online 15 February 2007
Abstract
In this paper, the hot carrier degradation of laterally diffused nMOSFETs is investigated in detail by the analysis of the fundamental
device parameters and charge pumping measurements. Starting from this experimental characterization a new approach based on charge
pumping technique is developed to estimate the spatial distribution of the hot carrier damage. This methodology has been applied on test
structures, obtaining good results in the prediction of both the interface states and the trapped charges profiling. The supporting assump-
tions have been verified by fitting to the electrical data and by means of a two-dimensional device simulation.
Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction
The increasing need to achieve RF products suitable for
high power applications has found in the LDMOS (Later-
ally Diffused MOS) transistor one of the most important
devices, particularly in terms of high gain and high linearity
[1]. These performance requirements are achieved by means
of the introduction of a lightly doped drain (LDD) exten-
sion able to reduce the electric field between the drain
and the edge of the channel. Thanks to this, LDMOS tran-
sistors are widely used in power amplifiers at microwave
frequencies in commercial applications such as base-station
transmitters [2] and every time power handling is required.
Nevertheless, since their applications occur at high drain
voltages, effects of gate dielectric degradation due to hot
carrier damage are involved [3]. Therefore, a detailed
understanding of the damage build-up under operation is
necessary to allow accurate evaluation of long-term reli-
ability and to improve the device structure design [4]. This
paper provides a contribution in this direction, since it
reports a new methodology based on charge pumping
(CP) technique [5,6], able to discriminate the effects of
interface states and trapped charge to quantify the damage
under hot carrier stress.
2. Experimental
LDMOS structures with small areas (W · L = 132 ·
0.8 lm2
) and with non-nitrided gate oxides (thickness
about 62 nm) together with non-optimized LDD dose,
were prepared to test our methodology. Fig. 1 shows a
sketch of LDMOS test structure used in this work. As it
is possible to observe, it is basically a nMOSFET with
laterally diffused body and LDD structure at the drain.
The laterally diffused p+
implant enhances the RF gain
and prevents punch-through at high drain-source voltage
Vds, while the lightly doped drain extension controls the
drain-source breakdown voltage BVDSS. The length and
doping of the drain extension, together with the epitaxial-
layer resistivity and thickness, determine BVDSS. This
breakdown voltage can therefore be tuned for a specific
application. In our case the devices are designed to work
at Vds = 32 V. In this operational condition electrons and
holes in the channel and in the pinch-off region can gain
sufficient energy to overcome the energy barrier or tunnel
0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2007.01.011
*
Corresponding author.
E-mail address: domenico.corso@imm.cnr.it (D. Corso).
www.elsevier.com/locate/microrel
Microelectronics Reliability 47 (2007) 806–809
2. into the oxide. Moreover, the impact of the hot carriers at
the oxide/Si interface under the gate, along the channel
and/or within the overlapped LDD region, can produce
both additional interface traps and oxide trapped charges,
leading to a degradation of the device performances.
Exploration of the mechanisms by which this degrada-
tion occurs is of critical importance to obtain reliable
devices. So, to study this effects we have chosen to perform
several stress conditions of drain voltages and times. In
particular, the devices were stressed at room temperature
in on condition at constant gate voltage of 3.9 V, which
is the typical gate bias for the applications of this family
of devices. Drain voltages ranging from 10 V to 40 V for
times ranging from seconds to days have been chosen to
explore different damage cases. In fact, in this conditions
the applied voltage stress monitors the degradation of some
fundamental device parameters, such as transconductance,
on-resistance RDS(on) or threshold voltage. Fig. 2 shows
the drain current curves versus time, i.e. injected charge
Qinj ¼
R
IDðtÞdt, when several constant drain voltages are
applied. As it is clearly visible, the current decreases and
so the RDS(on) increases. This worsening can be reasonably
attributed to a local degradation near the drain, where the
carriers have higher energy.
To improve the understanding of the damage profiling,
charge pumping measurements were performed maintain-
ing constant both the base level and the voltage slew rate.
A typical example of charge pumping curves taken on our
devices in fresh conditions and after stresses at constant
drain voltage with increasing stress time is reported in
Fig. 3.
It is well known that charge pumping curves evolve as a
consequence of two effects: hole or electron trapping in the
gate dielectric and interface states density build-up [7]. The
leading idea of our work is to extract the contributions of
the two effects by means of simple assumptions regarding
the damage profile before and after stress. In the following
section we describe this assumptions and a quantitative
model based on these concepts will be given.
3. Results and discussion
By assuming that the interface states of the fresh test
devices are uniformly distributed along the device interface
under the gate electrode, we can write the charge pumping
current as
Ifresh
cp ðXÞ ¼ qfWXNfresh
it ð1Þ
where q is the elementary charge, f is the frequency of the
gate pulse, W is the channel width, X is the channel
position, and Nfresh
it is the initial interface state density.
Therefore, the charge pumping curve of the fresh device
represents the lateral profile of the threshold voltage (posi-
tion dependent since the local channel doping concentra-
tion varies with the position) [8]
V fresh
th ðXÞ ¼ f À1
ðIfresh
cp ðxÞÞ ð2Þ
Fig. 2. Drain current curves versus injected charge (Qinj), at different
constant drain voltages.
Fig. 3. Charge pumping curves taken on a fresh device (dashed line) and
after stresses (continuous line) at constant drain voltage with increasing
stress time. The curves evolve as a consequence of two effects: hole or
electron trapping in the gate dielectric and interface states density (Nit)
build-up.
n+n-n+
p+ channel
poly-Si
oxide
p- epitaxy
p++ substrate
D SLDD
G
Fig. 1. Schematic cross section of the LDMOS structure used in this
study.
D. Corso et al. / Microelectronics Reliability 47 (2007) 806–809 807
3. From Silvaco ATLAS simulations, solving the
Boltzmann–Poisson equations in the hydrodynamic
approximation, a good exponential behaviour peaked at
the channel-LDD interface with an extinction length of
about 100 nm has been found in the impact ionization rate
profile. A typical example of these simulations, performed
in the same bias conditions of our experiments (Vds % 26 V
and Vgs–Vth of a few hundreds mV), is reported in Fig. 4. It
is then reasonable to expect that the lateral profile of the
damage in the gate dielectric under stress should mirror
the exponential profile of the impact ionization rate under
the channel. So, we assume that the oxide trapped charge
after stress, i.e. the threshold voltage shift ðDV postÀstress
th Þ,
and the additional density of interface states ðDNpostÀstress
it Þ
should follow a similar exponential behaviour:
DNpostÀstress
it ðXÞ ¼ DNpostÀstress
itmax
exp À
X
kNit
ð3Þ
DV postÀstress
th ðXÞ ¼ DV postÀstress
thmax
exp À
X
kV th
ð4Þ
where DNpostÀstress
itmax
and DV postÀstress
thmax
are the maximum values
of the damage profile directly extracted by the experimental
CP curves, and kNit
and kV th
are two free parameters. There-
fore, the charge pumping curve should evolve according to
the following equations:
IpostÀstress
cp ðXÞ ¼ Ifresh
cp ðXÞ þ qfW
Z X
0
DNpostÀstress
it ðX0
ÞdX0
ð5Þ
V postÀstress
th ðXÞ ¼ V fresh
th ðXÞ þ DV postÀstress
th ðXÞ ð6Þ
Now, by using an iterative method we fit the experimen-
tal charge pumping curves with the calculated ones. The
iterative method consists of varying independently the
two free parameters kNit
and kV th
until the best fit, evaluated
using the v2
method, is reached.
The proposed methodology produces an excellent agree-
ment with the experimental data, in a very large range of
drain stress and gate voltages, times, injected charge and
different technologies and device designs. Fig. 5 shows an
example of such agreement: in a log scale plot the charge
pumping curve calculated assuming the combined effect
of interface state and oxide trapped charge shows a very
good fit with the data in the whole investigated range.
This approach has been systematically applied varying
the drain voltage stress and, consequently, the injected
charge: Fig. 6 shows an example of charge pumping curves
taken on the same type of devices stressed at various levels
of injected charge and drain voltage together with the fit
curves.
As the injected charge increases, the calculated gate
dielectric damage profile evolves (Fig. 7) according to
Eqs. (3) and (4) and a typical example of the evolution of
the parameters involved is reported in Fig. 8. Note that
Fig. 4. Simulation of electron-hole impact ionization rate versus position
and extinction length of the damage. Note that a behaviour quite well
represented by a single exponential tail peaked at the channel-LDD
position and with an extinction length of about 100 nm has been obtained.
Fig. 5. Charge pumping curve (continuous line) calculated assuming the
combined effect of interface state (dashed line) and oxide trapped charge
(dash-dot line). Experimental data for fresh (triangles) and for stressed
(circles) device are also reported.
Fig. 6. Experimental charge pumping curves (circles) of devices stressed at
various levels of injected charge and drain voltage together with the fit
curves (dashed line).
808 D. Corso et al. / Microelectronics Reliability 47 (2007) 806–809
4. the best fit extinction lengths kNit
and kV th
are of the order
of 100 nm, i.e., very close to the values expected on the
basis of the calculation of the impact ionization rate
(Fig. 4).
In summary, using an iterative method, the simple
assumptions described in the Eqs. (1)–(4) consent to predict
the stress-induced CP current as a combined effect of inter-
face traps (Eq. (5)) and trapped charge (Eq. (6)). The dam-
age distributions (Fig. 7) are obtained after fitting the CP
curves produced by the model with the experimental ones.
4. Conclusions
In this paper, we have reported on a new method for the
quantitative evaluation of the damage profile in LDMOS
devices stressed at high voltages. We have found that the
hot-carrier mechanisms taking place at high drain voltages
lead to exponential distribution of the damage. Verification
of this result was also supported using Silvaco ATLAS sim-
ulations. With this new method, the spatial distributions of
both interface traps and trapped charge can be easily
extracted from the experimental charge pumping measure-
ments. This allows one to improve the understanding of the
degradation mechanisms taking place when the devices
work at high voltages.
References
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technology for 2 GHz RF power amplifier applications. IEDM 1996:
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[3] Moens P, Tack M, Degraeve R, Groeseneken G. A novel hot-hole
injection degradation model for lateral nDMOS transistors. IEDM
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Improvement on P-channel SOI LDMOS transistor by adapting a
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[5] Groeseneken G, Maes HE. Basic and applications of the charge
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Fig. 7. Evolution of the gate dielectric damage profile with increasing
charge injected to the drain as calculated by Eqs. (3) and (4) to fit charge
pumping curves when devices are stressed at Vds = 30 V and Vgs = 3.9 V.
Fig. 8. Evolution of the parameters involved in Eqs. (3) and (4) as a
function of the injected charge at Vds = 30 V. DV thmax and DNitmax are the
maximum values of the damage profiles reported in Fig. 7, while kV th
and
kNit
are the extinction lengths of the same curves.
D. Corso et al. / Microelectronics Reliability 47 (2007) 806–809 809