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[object Object],ADS79XX Analog-to-Digital Converters
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SAR Architecture
Overview of ADS79xx Family ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Product Family Number of Channels Resolution 12 Bit 10 Bit 8 Bit 16 ADS7953 ADS7957 ADS7961 12 ADS7952 ADS7956 ADS7960 8 ADS7951 ADS7955 ADS7959 4 ADS7950 ADS7954 ADS7958
Internal Block Diagram
ADC and MUX Equivalent Circuit
Channel Sequencing Modes ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Power-up Sequence Auto 1 register program Auto 2 register program Alarm register program GPIO register program Operation in manual mode Operation in Auto-1 mode Operation in Auto-2 mode Operation in manual mode, channel 0
Programming Alarm Thresholds SDI: DI15..12 = 11XX (xx indicates group of four channels) Device enters alarm register programming sequence program alarm threshold Device in any operation mode Program alarm thresholds? DI12 = 0? Program another group of four channels? End of alarm programming Yes Yes Yes No No No
Programming GPIO SDI: DI15..12 = 0100 Device in any operation mode Program GPIO thresholds? Yes No End of alarm programming
Reference Design 1 ,[object Object]
Reference Design 2 ,[object Object]
Additional Resource ,[object Object],[object Object],[object Object],[object Object],[object Object],Newark Farnell

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ADS79XX Analog-to-Digital Converters

  • 1.
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  • 4.
  • 5. Product Family Number of Channels Resolution 12 Bit 10 Bit 8 Bit 16 ADS7953 ADS7957 ADS7961 12 ADS7952 ADS7956 ADS7960 8 ADS7951 ADS7955 ADS7959 4 ADS7950 ADS7954 ADS7958
  • 7. ADC and MUX Equivalent Circuit
  • 8.
  • 9. Power-up Sequence Auto 1 register program Auto 2 register program Alarm register program GPIO register program Operation in manual mode Operation in Auto-1 mode Operation in Auto-2 mode Operation in manual mode, channel 0
  • 10. Programming Alarm Thresholds SDI: DI15..12 = 11XX (xx indicates group of four channels) Device enters alarm register programming sequence program alarm threshold Device in any operation mode Program alarm thresholds? DI12 = 0? Program another group of four channels? End of alarm programming Yes Yes Yes No No No
  • 11. Programming GPIO SDI: DI15..12 = 0100 Device in any operation mode Program GPIO thresholds? Yes No End of alarm programming
  • 12.
  • 13.
  • 14.

Editor's Notes

  1. Welcome to the training module on Freescale i.MX31 processor. This training module provides an overview of the ADS79xx ADC family, and introduce their key features and applications.
  2. Successive-approximation register (SAR) converters are frequently the architecture of choice for medium-resolution applications with medium sampling rates. They provide low power consumption and have a small form factor. In more recent designs, the topology of SAR A/D converters use a capacitive redistribution design approach instead its predecessor architecture, the R-2R ladder topology. With the topology shown in the Figure, the analog input voltage is initially sampled by connecting the input signal to the bottom side of sampling capacitors. This configuration is achieved with the sampling switch (S S ). The other ends of these sampling capacitors are connected to the reference voltage. Now that the input signal has been sampled, the bottom side of the MSB capacitor is connected to the reference voltage while the other capacitors are tied to the system ground. With this action, the charge from the MSB capacitor is distributed among the other capacitors. The comparator input moves up or down in voltage according to the way the charge is distributed. If the voltage across the capacitive array is greater than the comparator reference, an MSB equal to zero is generated and the MSB capacitor is left tied to V REF . If this voltage is less than the comparator reference, an MSB bit equal to '1' is generated, and the MSB capacitor is connected to ground.
  3. The ADS79XX is a 12/10/8-bit multichannel analog-to-digital converter family. The devices include a capacitor based SAR analog to digital converter with inherent sample and hold. The devices accept a wide analog supply range from 2.7V to 5.25V. A wide 1.7V to 5.25V I/O supply range facilitates a glue-less interface with the most commonly used CMOS digital hosts. The serial interface is for easy connection with microprocessors and DSPs. The devices offer an attractive power-down feature. This is extremely useful for power saving when the device is operated at lower conversion speeds. Very low power consumption makes these devices suitable for battery-powered and isolated power supply applications. There are two software selectable input ranges, four individually configurable GPIOs, and two programmable alarm level per channel. These features make these devices suitable for most data acquisition applications.
  4. Here lists all 12 devices from this product family.
  5. The ADS79xx device family offers 16/12/8/4 channel multiplexers for analog input. The multiplexer output is available on the MXO pin. AINP is the ADC input pin. Device operation is controlled with CS, SCLK, and SDI. The device outputs its data on SDO. Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected channel is sampled, and the conversion process is initiated. The device has four General Purpose Input / Output (GPIO) pins. These four pins can be individually programmed as GPO or GPI. GPO data can be written into the device through the SDI line, and similarly the device outputs GPI data on the SDO line. The device also has two programmable alarm thresholds per channel. If the input crosses these limits; the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings. The ADS79XX can operate with an external 2.5V ± 10mV reference. A clean, low noise, well-decoupled reference voltage on the REF pin is required to ensure good performance of the converter.
  6. When the converter samples an input, the voltage difference between AINP and AGND is captured on the internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS79XX charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. When the converter goes into hold mode, the input impedance is greater than 1GΩ. To maintain linearity of the converter, the Ch0 to Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications.
  7. There are three modes for channel sequencing, namely Manual mode, Auto-1 mode, Auto-2 mode. Mode selection is done by writing into the control register. A ‘Mode control register’ is configured to operate the device in one of three channel sequencing modes. The 'Program registers’ are used for device configuration settings and are typically programmed once on power-up or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for pre-programming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the sequence. On power-up or after reset the default channel is 'Channel-0' and the device is in Manual mode.
  8. The device power-up sequence is shown in the Figure. Manual mode is the default power-up channel sequencing mode and Channel-0 is the first channel by default. These devices offer Program Registers to configure user programmable features like GPIO, Alarm, and to pre-program the channel sequence for Auto modes. At ‘power-up or on reset’ these registers are set to the default. It is recommended to program these registers on power-up or after reset. Once configured, the device is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2.
  9. There are two Alarm Program Registers per channel, one for setting the high alarm threshold and the other for setting the low alarm threshold. For ease of programming, two alarm programming registers per channel, corresponding to four consecutive channels, are assembled into one group (maximum eight registers). Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the device enters the programming sequence and in each subsequent frame it programs one of the registers from the group. The device offers a feature to program less than eight registers in one programming sequence. The device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm Program’ bit high.
  10. The device has four General Purpose Input and Output (GPIO) pins. Each of the four pins can be independently programmed as General Purpose Output (GPO) or General Purpose Input (GPI). It is also possible to use the GPIOs for some pre-assigned functions. The device refreshes the GPO data on every CS falling edge as per the SDI data written in the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge.
  11. Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be processed independently. The signal inputs may from sensors. In this condition it is recommended to limit source impedance to 50Ω or less. Higher source impedance may affect the signal settling time after a multiplexer channel change. This condition can affect linearity and total harmonic distortion.
  12. Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the restriction on source impedance to a large extent. The typical characteristics show that the device has respectable performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when all channel signals are within the acceptable range of the ADC. In this case the user can save on signal conditioning circuit for each channel.
  13. Thank you for taking the time to view this presentation on TI ADS79xx family ADCs. If you would like to learn more or go on to purchase some of these devices, you can either click on the part list link, or simple call our sales hotline. For more technical information you can either visit the TI site – link shown – or if you would prefer to speak to someone live, please call our hotline number shown, or even use our ‘live chat’ online facility.