The 8086 processor is manufactured using HMOS technology and contains approximately 29,000 transistors housed in a 40-pin DIP package. It has a 16-bit external data bus and 20-bit address bus, allowing it to access up to 1MB of memory. The architecture uses a bus interface unit and execution unit that operate in parallel, improving performance over previous 8-bit processors through pipelining.

1. 8086
It is manufactured using high performance metal-oxide semiconductor
(HMOS) technology. It has approximately 29,000 transistors and housed
in a 40-pin DIP package.
Pradip Saha
HIT

2. Reference Book:
Ramesh S. Goankar, “Microprocessor Architecture, Programming and Applications with 8085”,
5thEdition, Prentice Hall

3. 8085 8086
8085 processor is developed in 1977
using NMOS technology where IC
consists of about 6200 transistors.
8086 processor is developed in 1978
using HMOS technology where IC
consists of about 29000 transistors
8-bit data bus and 16-bit address bus
and is able to access 64KB Memory.
16-bit data bus and 20-bit address bus
and is able to access 1MB Memory.
Instruction queue does not exist in
8085
8086 has a 6-byte instruction queue in
BIU
Pipelining concept is not used in 8085,
sequentially executes instructions.
Pipelining concept is used in 8086.
No segment registers exist in 8085. There are four segment registers, CS,
DE, ES, SS in
8086.
Number of flags are 5. Number of flags are 9.
Only four types of addressing modes
are available.
Eight types of addressing modes are
available.
8085 has less no. of instructions. 8086 has more instructions. Direct
multiplication, division can be done.

4. ❑ Typical Examples of 16 bit processors are:
(i) Intel 8086/8088 and 80186/286
(ii) Zilog Z8001/8002
(iii) Motorola 68000 and
(iv) National Semiconductor NS16000.
❑ The primary objectives of 16 bit processors are:
(i) To increase memory addressing capacity
(ii) increase execution speed
(iii) Provide a powerful instruction set
(iv) Function in a multiprocessor environment

6. 8086 Pin Diagram

7. Minimum Mode Pin Configuration

12. Memory Segmentation
 In 8086, 20 bit address allow us to access 1 MB memory. So each
location of the memory will have 20 bit physical address.
How do we generate 20 bit physical address using 16 bit
registers?
So, we need memory segmentation where the physically
available memory (1MB) is divided into a no. of logical segments.
 Maximum size of each segments should be 64KB as registers are
16 bit.
Thus, there will have 16 no. of logical segments. However, at
any instant 8086 can work only with 4 such segments and i.e. why in
BIU, 4 segment registers are available.
 The address of the segments can be 0000H to F000H and the offset
of each segment can be addressed as 0000H to FFFFH.
Thus, 20 bit physical address would be 00000H to
FFFFFH.
 The physical address of memory is computed by
The content of segment register × (10)16 + offset address

13. Segment memory of an 8086 microprocessor

14. MEMORY SEGMENTATION

15. Memory Segmentation
Segments are ≤ 64K and can overlap.
Note that the Code segment is < 64K since 0FFFFFH is the highest
address.

16. Q1. Determine the physical address when ES is 6500H and offset
address is 4767H.
Ans: The content of the segment register ES is 6500H. When it is left
shifted by 4 bits or multiplied by (16)D or (10)H, the base address is equal to
6500H × (10)H = 65000H.
Physical address = Content of segment register ×(10)H + Offset
address
= 6500H×(10)H + 4567H
= 65000H + 4567H = 69567H
Q2: What is the content of data segment DS to locate the physical
address 43657H? Assume the content of IP = 2057H.
Ans: Physical address = Content of data segment register ×(10)H + IP
address
Therefore,
43657H = Content of data segment register ×(10)H + 2057H
i.e., content of data segment register × (10)H = 43657H – 2057H = 4
1600H
Thus, The content of data segment register (DS) is 4160H.

17.  Physically, the memory can be organized as two banks such as even and odd
bank and each bank consists of 512 KB memory size.
 The data lines D7–D0 are used for data transfer from even bank and D15–D8
are
used for the odd bank.
 The even bank is selected by A0 = 0 and BHE’ = 1 and data bus D7–D0 is
connected.
When A0 = 1 and BHE’ = 0, the odd bank is selected and data bus D15–D8 is
connected.

18. Process to access 16 bit data starting from Even Address
Here, 16-bit data from an even address and an odd address respectively is
accessed within a single bus cycle. The address lines A19–A1 select the
appropriate byte within each bank. While A0 = 0 and BHE’ is low, the even and
odd banks are enabled simultaneously. For example, the 20-bit address is
20002H.
Since A0 = 0 and BHE = 0, one word or two bytes have to be transferred from
memory locations 20002H and 20003H respectively. Data from an odd bank is
transferred to D15–D8 and data from an even bank is transferred to D7 –D0 data
bus. Hence data bus AD15–AD0 contains two byte data from memory. As WR = 0,
M/IO = 1, 16-bit data can be copied into the data bus from the memory bank.

19. Process to access 16 bit data starting
from Odd Address:
Generally, a 16-bit word located at an odd address is accessed using two
bus cycles.
Assume the 20-bit physical address is 20003H and the 8086 transfers
a word in two bus cycles. During the first cycle, A0 = 1 and BHE’ = 0; the odd
bank becomes enabled for data transfer and even bank is disabled. RD = 0
and M/IO = 1 for 8086, the odd memory places data on D15–D8 bus. During
the first bus cycle the lower byte is accessed from memory location 20003H.

20. In the second cycle, A0 = 0 and BHE = 1, the even bank of memory becomes
enabled and the odd bank is disabled. Then processor output RD = 0 and M/IO =
1. The selected even-bank memory location content is on D7–D0 bus. Then data
is to be accessed. Therefore, during the second bus cycle, the upper byte is
accessed from the even address bank of memory location 20004H.

21. Architecture

22. • The architecture of 8086 has two separate functional units—Bus Interface
Unit (BIU) and Execution Unit (EU).
– The BIU fetches instructions, reads and writes data, and computes the
20-bit address.
– The EU decodes and executes the instructions using the 16-bit ALU.
⮚ The BIU contains the following registers:
IP - the Instruction Pointer, CS - the Code Segment Register
DS - the Data Segment Register, SS - the Stack Segment Register
ES - the Extra Segment Register
• The BIU fetches instructions using the CS and IP, written CS:IP, to construct
the 20-bit address. Data is fetched using a segment register (usually the
DS) and an effective address (EA) computed by the EU depending on the
addressing mode.
⮚ The EU contains the following 16-bit registers:
AX - the Accumulator, BX - the Base Register
CX - the Count Register, DX - the Data Register
SP - the Stack Pointer, BP - the Base Pointer
SI - the Source Index Register, DI - the Destination Register
• These are referred to as general-purpose registers, although, as seen by
their names, they often have a special-purpose use for some instructions.

23. • The AX, BX, CX, and DX registers can be consider as two 8-bit
registers, a High byte and a Low byte. This allows byte operations and
compatibility with the previous generation of 8-bit processors, the
8080 and 8085. 8085 source code could be translated in 8086 code
and assembled. The 8-bit registers are:
AX --> AH, AL ; BX --> BH, BL ;
CX --> CH, CL; DX --> DH, DL ;
• The instruction queue is 6-bytes in length, operates on FIFO basis, and
receives the instruction codes from memory. Initially, the queue is
empty and CS : IP is loaded with the required address (from which the
execution is to be started). Microprocessor 8086 starts operation by
fetching 1 (or 2) byte(s) of instruction code(s) if CS : IP address is odd
(even).
• The 1st byte is always an opcode, which when decoded, one byte in
the queue becomes empty and the queue is updated. The filling in
operation of the queue is not started until two bytes of the instruction
queue is empty. The instruction execution cycle is never broken for
fetch operation.

24. • After decoding of the 1st byte, the decoder circuit gets to know
whether the instruction is of single or double opcode byte.
• For a single opcode byte, the next bytes are treated as data bytes
depending upon the decoded instruction length, otherwise the next
byte is treated as the second byte of the instruction opcode.
• For a 2-byte instruction code, the decoding process takes place
taking both the bytes into consideration which then decides on the
decoded instruction length and the number of subsequent bytes
which will be treated as instruction data. Updation of the queue
takes place once a byte is read from the queue.
• 8086 architecture employs parallel processing—i.e., both the units
(BIU and EU) work at the same time. This is Unlike 8085 in which
Sequential fetch and execute operations take place. Thus in case of
8086, efficient use of system bus takes place and higher
performance (because of reduced instruction time) is ensured.
Here, fetching the next instruction when the current instruction is
being executed, is called Pipelining.

26. • BIU has segment registers, instruction pointer, address generation and
bus control logic block, instruction queue while the EU has general
purpose registers, ALU, control unit, instruction register, flag (or
status) register.
• The main jobs performed by BIU are:
i. BIU is the 8086’s interface to the outside world, i.e., all
External bus operations are done by BIU.
ii. It does the job of instruction fetching, reading/writing of
data/operands for memory and also the inputting/outputting of data
for peripheral devices.
iii. It does the job of filling the instruction queue.
iv. Does the job of address generation.
• The main jobs performed by the execution unit are:
i. Decoding/execution of instructions.
ii. It accepts instructions from the output end of instruction
queue (residing in BIU) and data from the general purpose registers or
memory.
iii. It generates operand addresses when necessary, hands them
over to BIU requesting it (BIU) to perform read or write cycle to
memory or I/O devices.
• EU tests the status of flags in the control register and updates them
when executing instructions.
• EU waits for instructions from the instruction queue, when it is empty.

27. WAIT state
• Conditions that cause the EU to enter into WAIT state:
When an instruction requires the access to a memory location not in the
queue.
e.g., When a JUMP instruction is executed. In this case the current queue
contents are aborted and the EU waits until the instructions at the jump address is
fetched from memory.
The instruction AAM (ASCII adjust for multiplication) requires 83 clock
cycles for execution.

28. Registers of 8086

29. Registers of 8086
There are total fourteen numbers of 16-bit registers. The
different groups are
i. Data group: The data group consists of AX
(accumulator), BX (base), CX (count) and DX (data).
ii. Pointers and index group: Pointer and Index group
consist of SP (Stack pointer), BP (Base pointer), SI (Source
Index), DI (Destination index) and IP (Instruction pointer).
iii. Segment group: Segment group consists of ES (Extra
Segment), CS (Code Segment), DS (Data Segment) and SS
(Stack Segment).
iv. Control flag group: consists of a single 16-bit flag
register.

30. Flag Register
❖ Flag register contains information reflecting
the current status of a microprocessor. It also
contains information which controls the
operation of the microprocessor.

31. ❖ M/C Flags:
IF: Interrupt enable flag
DF: Direction flag
TF: Trap flag
❖ Status Flags:
CF: Carry flag
PF: Parity flag
AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
OF:Overflow flag

32. • Trap flag: Once set, a single-step interrupt occurs after the
next instruction executes; TF is cleared by the single-step
interrupt.
• Interrupt-enable flag: When set, maskable interrupts will
cause the CPU to transfer control to an interrupt vector
specified location, IF can be set by executing STI instruction
and cleared by CLI instruction.
• Direction flag: Causes string instructions to auto
decrement the appropriate index register when set;
clearing DF causes auto increment. It can be set by STD
instruction and cleared by CLD.
• Overflow flag: Set if the signed result cannot be expressed
within the number of bits in the destination operand;
cleared otherwise.

33. • Direction Flag (DF) is used to control the way
SI and DI are adjusted during the execution of
a string instruction
– DF=0, SI and DI will auto-increment during the execution; otherwise,
SI and DI auto-decrement
– Instruction to set DF: STD;
– Instruction to clear DF: CLD
– Example: CLD
MOV CX, 05
REP MOVSB
Note: At the beginning of execution, DS=0510H and SI=0000H

34. ❖ Data Registers (AX, BX, CX, DX)
• All the four registers can be used as the source or
destination of an operand during an arithmetic
operation or logical operation.
• Register CX is used as a count register in string
operations and as such is called a ‘count’ register.
Register CX is also used for multibit shift or rotate
instructions.
• Register DX is used to hold the address of I/O port
while register A is used for all I/O operations that
require data to be inputted or outputted.

35. ❖ Index and Pointer Registers:
• SI and DI: contents of SI are added to contents of DS
register to get the actual source address of data, while the
contents of DI are added to the contents of ES to get the
actual destination address of data.
• SP, BP and IP: SP containing the offset address or the stack
top address. The actual stack address is computed by
adding the contents of SP and SS.
Data area(s) may exist in stack. To access such data area
in stack segment, BP register is used which contains the offset
address. BP register is also used as a general purpose register.
IP points to the offset address of the next instruction to
be fetched (from the current code segment) in BIU. IP resides
in BIU but cannot be programmed by the programmer.

36. Instruction Types
• Data transfer instructions
• String instructions
• Arithmetic instructions
• Logical instructions
• Loop and jump instructions
• Subroutine and interrupt instructions
• Processor control instructions

37. The data-transfer instructions are used to transfer data between registers, registers and memory,
registers and immediate data, or memory and immediate data.
Syntax: 1. MOV destination, source ; Copy data from source to destination
Destination Source, Flag affected: None
For example,
i. MOV BX, CX ,,,,,, CX register to BX register data transfer.
ii. MOV AL, 8-bit data ,,,,,,,,, MOV AL, FFH
ii. MOV [0345], 23H ,,,,,, Here, 23H will be loaded into the memory location DS × 10 +0345.
iii. MOV [0345], 2345H ,,,,,, 45H will be loaded into the memory location DS × 10 +
0345 and 23H will be loaded into DS × 10 + 0346.
iv. MOV [reg ], data,,,,,, MOV [BX], 45H…... Here, data 45H will be moved to the
memory location specified by the content of BX i.e., DS × 10 +
BX.
v. MOV AL/AX, [2340] ,,,,Moves the content of offset address 2340H to AL/AX.
vi. MOV [4000], AL/AX ,,,,, Content of AL/AX is stored in the memory location/two
consecutive memory locations represented by offset address
4000H.
Data transfer instructions

38. Data transfer instructions
2. XCHG destination, source; Exchange data between source to destination.
e.g.,
XCHG AX, BX
XCHG [4000], AX
XCHG AL, [BX]
3. LAHF ; Loads the lower flags byte into AH.
4. SAHF; Store AH into lower flags byte.
5. IN AL/AX, 8 bit port/DX; Input data from I/O device to AL/AX for
8/16 bit input data. 8 bit port
address specified directly but 16 bit port address has to be specified by DX register.
6. OUT 02, AL; It sends the content of AL to a port address 02H.
OUT DX, AX; It sends data available in AX to a port address which is specified by
the DX register. If the port address is of 16-bit, it must be in DX.
Destination Source
Accumulator register
Memory register
Register register

39. (i) Move the content of DX register into SS register; MOV SS, DX;
(ii) Load 16-bit data from memory location having offset address 0300
to AX;
MOV AX, [0300];
(iii) Load 8-bit data, FF in the BL register; MOV BL, FF;
(iv) Source index address 0100 is stored in SI; MOV SI, 0100;
(v) Destination index address 0400 is stored in DI; MOV DI, 0400;
Note:
In case of immediate addressing mode, a segment register cannot be
a destination register. Direct loading of the segment registers with
immediate data is not permitted. To load the segment registers with
immediate data, one will have to load any general-purpose register
with data and then it will have to be moved to that particular
segment register.
e.g., Load 16-bit data, C100H to Code Segment Register.
MOV CS, C100………..Not Permitted
Instead Use MOV AX, C100
MOV CS, AX

40. LEA reg16, addr; Loads the effective address or offset of memory into
16 bit register.
e.g.,
LEA SI, address; LEA BX, ADR
16-bit effective address loads in the SI/BX register.
LODSB; Load the content of specified memory location represented by SI into
the AL register.
LODSW; Load the content of specified memory location represented by SI
into the AX register.
Note:
For 80x86 family, directly moving data from one memory location to another memory
location is not allowed
MOV [SI], [5000H] …..This is Wrong

41. Arithmetic and Logical Instruction
The 8086/8088 instructions that handle these operations are ADD, ADC, SUB,
SBB, INC, DEC, NEG, MUL, IMUL, DIV, IDIV, and other instructions such
as AAA, AAD, AAM, AAS, DAA, and DAS.
i. ADD destination, source
Destination (Source + Destination )
e.g.,
ADD AL, 22H; ADD AX, BX; ADD AL, [BX]; ADD [BX],CL; ADD [BX],CX.
ii. ADC destination, source;
Destination (Source + Destination + CF)
iii. SUB destination, source;
Destination (Destination -Source)
iv. INC destination;
Here, the contents of the specified register or memory location increases by1.

42. e.g.,
(i) ADD AX, 2345; Add 2345 to the contents of
the AX register
(ii) ADD [BX], 22; Add 22H to the content of the
specified memory location by the BX register
(iii) SUB AX, BX; Subtract the content of the AX
register from AX register
(iv) SBB AX, 2345; Subtract immediately 2345
from BX register with borrow
(v) SUB [0100], 1000; Subtract immediately
1000 from memory with offset address
0100H

43. INC destination; the contents of the specified register or
memory location increases by 1.
e.g., INC BX; INC CX; INC DX, INC [BX].
DEC destination; the contents of the specified register or
memory location decreased by 1.
NEG destination; This instruction performs 2’s complement
of destination. To obtain 2’s complement, it subtracts the
contents of the destination from zero.
e.g., NEG AX; NEG BX; NEG CX; NEG DX; NEG AL.
CMP destination, source; Compare by subtracting source
from destination.
e.g., CMP BX, 1234; CMP AL, 22; CMP BX, [SI]; CMP [0100], BX and
CMP [BX], CX.

44. (i) Compare 16-bit immediately available data
(4567H) from the AX register……
CMP AX,4567 ;
(ii) Increment the contents of the CX register by
one……… INC CX;
(iii) Decrement the contents of memory
location specified by the BX register……. DEC
[BX];
(iv) 2’s complement of the accumulator…. NEG
AX;
(v) Compare 8-bit data (FFH) with the contents
of memory location specified by source
index….. CMP [SI], FF;

45. MUL source; It Multiplies 8- or 16-bit source by 8-bit (AL) or 16-bit
(AX) value (unsigned).
Here, AX (AL * source 8)
DX : AX (AX * source16).
The Source i.e., unsigned byte or word will be one of the general purpose
registers or memory locations but it cannot be an immediate data.
e.g., MUL CL; MUL BX; MUL CX; MUL DX and MUL [BX+10].
IMUL source; It Multiplies 8-bit or 16-bit source by 8-bit (AL) or 16-
bit (AX) value (signed).
e.g., IMUL CL; IMUL BH; IMUL BX; IMUL CX; IMUL DX and IMUL [BX+10].
DIV source; It Divides 16-bit or 32-bit number available in AX or
DX:AX by 8- or 16-bit number represented by the source. (unsigned).
AL (AX ÷ Source 8) and AH Remainder
AX (DX: AX ÷ Source 16) and DX Remainder
e.g., DIV CL; DIV BX; DIV CX; DIV DX and DIV [BX+10].
IDIV source; It Divides 16-bit or 32-bit number available in AX or DX:AX by 8-
or 16-bit number represented by the source. (signed).

46. e.g., Divide AX by the content of memory location represented by BX……
DIV [BX];
For DIV and IDIV, If the result i.e., quotient is too big to fit in AL, a divide by zero
(type 0) interrupt is generated. Divide by 0 interrupt is generated, if the
result (quotient) is too big to fit in AX, a divide by zero (type 0) interrupt is
generated.
DAA; (Decimal adjustment after addition)
DAS; (Decimal adjust for subtraction)
AAA; (ASCII adjust for addition)
AAS; (ASCII adjust for subtraction)
AAM; (ASCII adjust for multiplication)
NOT destination; …….The NOT instruction is used to generate complement of
the contents of an operand register or a memory location, bit by bit.
e.g., NOT CL NOT DL, NOT AX, NOT BX, NOT CX, and NOT [BX].
AND destination, source; AND CX, DX; AND AX, [BX] and AND AX, [SI].
OR destination, source; OR CX, DX; OR AX, [BX] and OR AX, [SI].
XOR destination, source; XOR CX, DX; XOR AX, [BX]
• TEST destination, source; The TEST instruction performs a nondestructive
bitwise logical AND of source and destination, setting flags and leaving
destination unchanged. The result of this ANDing operation will not be
available, but the flags are affected. Generally, OF, CF, SF, ZF and PF flags are
affected. The source operands may be a register or a memory or immediate
data and the destination operands may be a register or a memory.

47. 1’s complement of the content of the DX register……….NEG DX;
AND 1234H with the content of the AX register…… AND AX, 1234;
SHL/SAL operand1, operand2; ….(Shift Logical/ Arithmetic Left)
These instructions shift each bit in the operand1 (word or byte) to the
left and insert zeros in the newly introduced least significant bits. The
highest order bit shifts into the carry flag. The number of shifts is set by
operand-2. The operand-2 will be an immediate data or content of CL
register.
e.g., SHL AX, 8; Result is equivalent to AX*256.
SHR AX, 8; Result is equivalent to AX/256….. (Shift Logical Right).
• SAR AX, 1; (Shift Arithmetic Right) The SAR instruction performs right
shifts all the bits in the destination operand (word or byte) to the right
one bit. This instruction is replicating the most significant bit of the operand
in the newly inserted positions.

48. If the content of the AX register is = AAAA, after execution of
SAR AX, 1 the content of AX will be D555.
ROR operand1, operand2; …(Rotate right without carry)The ROR
instruction rotates the contents of the destination operand to the right
bit wise either by one or by the count specified in CL without carry. The
least significant bit is stored into the carry flag and simultaneously it is
transferred into the most significant bit position after each shift
operation.
ROL operand1, operand2; …(Rotate left without carry)

49. RCR operand1, operand2; …(Rotate right through carry)
RCL operand1, operand2; …(Rotate Left through carry)

50. Jump and Loop instructions
JMP target; …….Unconditional JUMP TO TARGET/ specified
address using an 8-bit or 16-bit displacement.
The jump instructions have different formats to
specify the jump address.
• Short jumps are within ±128 bytes of JMP instruction–only IP
is affected.
• Near jumps are within same segment–only IP is affected.
Near jump allows a jump within ±32 KB
• Indirect jumps are within the same segment–only IP is
affected.
• Far jumps are to a different segment–both CS and IP are
affected.

51. Name/Alt Meaning Flag setting
JE/JZ Jump equal/zero ZF = 1
JNE/JNZ Jump not equal/zero ZF = 0
JL/JNGE Jump less than/not greater than or = (SF xor OF) = 1
JNL/JGE Jump not less than/greater than or = (SF xor OF) = 0
JG/JNLE Jump greater than/not less than or = ((SF xor OF) or ZF) = 0
JNG/JLE Jump not greater than/ less than or = ((SF xor OF) or ZF) = 1
JB/JNAE Jump below/not above or equal CF = 1
JNB/JAE Jump not below/above or equal CF = 0
JA/JNBE Jump above/not below or equal (CF or ZF) = 0
JNA/JBE Jump not above/ below or equal (CF or ZF) = 1
JS Jump on sign (jump negative) SF = 1
JNS Jump on not sign (jump positive) SF = 0
JO Jump on overflow OF = 1
JNO Jump on no overflow OF = 0
JP/JPE Jump parity/parity even PF = 1
JNP/JPO Jump no parity/parity odd PF = 0
Conditional Jumps

52. If conditional jump instructions are executed, program control can be
transferred
to the address specified by instruction itself. If the condition is not satisfied,
instructions are executed sequentially. Here, condition is the status of flag. After
execution of these instructions, no flags are affected. The address will be
specified in the instruction which will be varied from-80H (-128) bytes to 7FH
(127) bytes. Therefore, only short jumps can be implemented using conditional
Branch instructions.

53. LOOP target;
The LOOP instruction executes the part of the program from the level or
address specified in the instruction up to the loop instruction, CX number of
times. After each iteration, CX is decremented automatically. If the content
of CX is not zero, the LOOP instruction transfers control to starting address of
the LOOP for execution. If CX is zero, the execution of LOOP instruction is
completed and then the next instruction of the program will be executed.
e.g.,
LEA SI, 0100; Load SI with source address of data
LEA DI, 0200; Load DI with destination address of data
MOV CX, 0009; Number of bytes 9 is loaded in CX register
START LODSB; Data byte to AL and increment SI by 1
STOSB; The content of AL is stored in destination address represented by
DI and increment DI by 1.
LOOP START; repeat until CX = 0
• The above example shows how a string of bytes can be shifted from one
memory block specified by SI to other memory block specified by DI using
LOOP instructions.
• LOOP START instruction is equivalent to
DEC CX
JNZ START

54. LOOPE/Z target; The CX register is decremented by 1. If CX is not equal to
0 or if the Z bit is set, the loop is transferred to short target.
LOOPNE/NZ target; The CX register is decremented by 1. If CX is not
equal to 0 or if the Z bit is reset, the loop is transferred to short target.
CALL target; and RET (return) instructions are used to call a
subroutine or a procedure that can be executed several times from a main
program. The starting address of the subroutine or procedure can be pecified
directly or indirectly depending upon the addressing mode. There are two
types of procedures, namely, intrasegment and intersegment. The subroutine
within a segment is known as intrasegment subroutine or NEAR CALL. The
subroutine from one segment to another segment is known as intersegment
subroutine or FAR CALL. These instructions are unconditional branch
instructions. After execution of these instructions, the incremented IP and CS
are stored onto the stack and loads the CS and IP registers with the segment
and offset addresses of the procedure to be called. For NEAR CALL, only the IP
register is stored on stack. But for FAR CALL, both IP and CS are stored onto
the stack. Hence the NEAR and FAR CALLs can be discriminated using opcode.

55. String Instructions
• String instructions can have at most two operands. One is referred
to as source string and the other one is called destination string
• Source string must locate in Data Segment and SI register points to
the current element of the source string
• Destination string must locate in Extra Segment and DI register
points to the current element of the destination string .

56. Repeat Prefix Instructions
 REPZ String Instruction
— Repeat the execution of the string instruction until CX=0 or zero flag is clear
 REPNZ String Instruction
— Repeat the execution of the string instruction until CX=0 or zero flag is set
 REPE String Instruction
— Repeat the execution of the string instruction until CX=0 or zero flag is clear
 REPNE String Instruction
— Repeat the execution of the string instruction until CX=0 or zero flag is set

57. • REP String Instruction
• The prefix instruction makes the microprocessor
repeatedly execute the string instruction until CX
decrements to 0 (During the execution, CX is decreased by
one when the string instruction is executed one time).
For Example:
MOV CX, 5
REP MOVSB
By the above two instructions, the microprocessor
will execute MOVSB 5 times.
– Execution flow of REP MOVSB::
While (CX!=0)
{
CX = CX –1;
MOVSB;
}

58. • MOVSB (MOVSW)
• Move byte (word) at memory location DS:SI to
memory location ES:DI and update SI and DI according
to DF and the width of the data being transferred
– It does not modify flags
• Example:
MOV AX, 0510H
MOV DS, AX
MOV SI, 0
MOV AX, 0300H
MOV ES, AX
MOV DI, 100H
CLD
MOV CX, 5
REP MOVSB

59. • CMPSB (CMPSW)
• Compare bytes (words) at memory locations
DS:SI and ES:DI; update SI and DI according to DF
and the width of the data being compared
– It modifies flags
• Assume: ES = 02A8H
• DI = 2000H
• DS = 0510H
• SI = 0000H
CLD
MOV CX, 09
REPZ CMPSB
What’s the values of CX after The execution?

60. Addressing Modes
• Immediate addressing MOV AL, 12H
• Register addressing MOV AL, BL
• Direct addressing MOV [500H], AL
• Register Indirect addressing MOV DL, [SI]
• Based addressing MOV AX, [BX+4]
• Indexed addressing MOV [DI-8], BL
• Based indexed addressing MOV [BP+SI], AH
• Based indexed with displacement addressing
MOV CL, [BX+DI+2]
• Exceptions
• String addressing
• Port addressing (e.g. IN AL, 79H)

61. Problem

62. Control Word:
 Here In 8086, A2 and A1 address lines are used to
connect with A1 and A0 pins of 8255.
 A0 address line of 8086 is used to select Even Memory
Bank to ensure the transfer through Lower Order data
Bus (D0-D7).
A0 remains Don’t care and so any change in A0
doesn’t affect on the selected port.

64. Port Address:

65. The ALP:

66. Interfacing of ADC0808 with 8086 processor using
8255PPI:

67. Microcontroller (8051, 8 bit)
Microcontroller:
 Intel’s 8 bit Microcontroller Family, Known as
MCS51 family.
 Intel’s 16 bit Microcontroller Family, Known as
MCS96 family.

68. Harvard vs. Princeton Architecture
Many years ago, in the late 1940's, the US Government asked Harvard
and Princeton universities to come up with a computer architecture to
be used in computing distances of Naval artillery shell for defense
applications. Princeton suggested computer architecture with a
single memory interface. It is also known as Von Neumann
architecture after the name of the chief scientist of the project in
Princeton University John Von Neumann (1903 - 1957 Born in
Budapest, Hungary).
Harvard suggested a computer with two different memory
interfaces, one for the data / variables and the other for program /
instructions. Although Princeton architecture was accepted for
simplicity and ease of implementation, Harvard architecture became
popular later, due to the parallelism of instruction execution.

69. A stand alone Microprocessor isn’t self- sufficient.
 To make it functional, requires other components like Memory
and Other Input / Output Devices.
 To have all these Components in a Discrete form and to
assemble them in a PCB isn’t ADVANTAGEOUS.
 Disadvantages are:

70.  To overcome these problems,
Intel Decided to Integrate a Microprocessor along with I/O ports,
Minimum required Memory and programmable Timer into a
Single package/Chip to make it a Self-Sufficient Device.
The Device is Known as
Microcontroller/ Single Chip Microcomputer.

71. Block diagram of Microcontroller

72. Comparisons of 8051 Family:
DEVICE ON-CHIP
DATA
MEMORY
(bytes)
ON-CHIP
PROGRAM
MEMORY
(bytes)
16-BIT
TIMER/COUN
TER
NO. OF
VECTORE
D
INTERUPT
S
FULL
DUPLEX
I/O
8031 128 None 2 5 1
8032 256 none 2 6 1
8051 128 4k ROM 2 5 1
8052 256 8k ROM 3 6 1
8751 128 4k EPROM 2 5 1
8752 256 8k EPROM 3 6 1
AT89C51 128 4k Flash
Memory
2 5 1
AT89C52 256 8k Flash
memory
3 6 1

75. Various features of 8051 microcontroller are given as follows:
 8-bit CPU
 16-bit Program Counter
 8-bit Processor Status Word (PSW)
 8-bit Stack Pointer
 Internal RAM of 128bytes
 Special Function Registers (SFRs) of 128 bytes
 32 I/O pins arranged as four 8-bit ports (P0 - P3)
 Two 16-bit timer/counters : T0 and T1
 Two external and three internal vectored interrupts
 One full duplex serial I/O

76. Architecture of 8051

80. Pin Diagram:

86. In 8051, one instruction cycle consists of twelve (12) clock cycles.
Instruction cycle is sometimes called as Machine cycle by some authors.
In 8051, each instruction cycle has six states (S 1 - S 6 ). Each state has
two pulses (P1 and P2).

90. Among 128 Bytes of RAM,
i. RAM locations 00-1F (32 Bytes)
are assigned to the register Banks
and Stack.
ii. 20-2F (16 Bytes) are Bit Addressable
space to save single bit data.
iii. 30-7F (80Bytes) are available as
a place to save Byte sized data.

92. Internal Data Memory and Special Function Register
(SFR) Map
The special function registers (SFRs) are mapped in the upper 128
bytes of internal data memory address. Hence there is an address
overlap between the upper 128 bytes of data RAM and SFRs. Please
note that the upper 128 bytes of data RAM are present only in the
8052 family. The lower128 bytes of RAM (00H - 7FH) can be
accessed both by direct or indirect addressing while the upper 128
bytes of RAM (80H - FFH) are accessed by indirect addressing. The
SFRs (80H - FFH) are accessed by direct addressing only. This
feature distinguishes the upper 128 bytes of memory from the SFRs.

93. The set of Special Function Registers (SFRs) contains important registers
such as Accumulator, Register B, I/O Port latch registers, Stack pointer, Data
Pointer, Processor Status Word (PSW) and various control registers. Some of
these registers are bit addressable (they are marked with a * in the diagram
below). The detailed map of various registers is shown in the following figure.
F8H
F0H B*
E8H
E0H ACC*
D8H
D0H PSW*
C8H (T2CON)* (RCAP2L) (RCAP2H) (TL2) (TH2)
C0H
B8H IP*
B0H P3*
A8H IE*
A0H P2*
98H SCON* SBUF
90H P1*
88H TCON* TMOD TL0 TL1 TH0 TH1
80H P0* SP DPL DPH PCON

94. Flag Register/PSW

97. 8051 Addressing Modes:
8051 has four addressing modes.
1. Immediate Addressing :
Data is immediately available in the instruction.
For example -
ADD A, #77; Adds 77 (decimal) to A and stores in A
MOV A,#22H
MOV DPTR,#1234H
ADD A, #4DH; Adds 4D (hexadecimal) to A and
stores in A
MOV DPTR, #1000H; Moves 1000 (hexadecimal) to
data pointer

98. 2. Register Addressing or Bank Addressing :
This way of addressing accesses the bytes in the current register bank.
Data is available in the register specified in the instruction. The register
bank is decided by 2 bits of Processor Status Word (PSW).
For example-
ADD A, R0; Adds content of R0 to A and stores in A.
MOV A,R0; MOV R1,A; MOV R4,DPL; MOV R4,R3…INVALID (data transfer
between Rn isn’t allowed.
3. Direct Addressing :
Although entire 128 Bytes of RAM can be access by using Direct
Addressing But most often we access 30-7F as there is no such name like
register bank.
For example -
MOV R0,40H; Moves content of RAM location 40H to R0.
MOV A, 088H; Moves content of SFR TCON (address 088H)to A.
4. Register Indirect Addressing :
The address of data is available in the R0 or R1 registers as specified in
the instruction.
For example -
MOV A, @R0; moves content of address pointed by R0 to A.
5. Indexed Addressing: (Used to access ROM space)
MOVC A, @A+DPTR; Moves content of address pointed by A+DPTR to A

99. External Data Addressing :
Pointer used for external data addressing can be either R0/R1 (256 byte
access) or DPTR (64kbyte access).
For example -
MOVX A, @R0; Moves content of 8-bit address pointed by R0 to A
MOVX A, @DPTR; Moves content of 16-bit address pointed by DPTR to A
External Code Addressing :
Sometimes we may want to store non-volatile data into the ROM e.g. look-
up tables. Such data may require reading the code memory. This may be
done as follows -
MOVC A, @A+DPTR; Moves content of address pointed by A+DPTR to A
MOVC A, @A+PC; Moves content of address pointed by A+PC to A

100. Timers / Counters
8051 has two 16-bit programmable UP timers/counters. They can be
configured to operate either as timers or as event counters. The names of
the two counters are T0 and T1 respectively. The timer content is available
in four 8-bit special function registers, viz, TL0,TH0,TL1 and TH1
respectively.
In the "timer" function mode, the counter is incremented in every machine
cycle. Thus, one can think of it as counting machine cycles. Hence the clock
rate is 1/12 th of the oscillator frequency.
In the "counter" function mode, the register is incremented in response to a 1
to 0 transition at its corresponding external input pin (T0 or T1). It requires 2
machine cycles to detect a high to low transition. Hence maximum count rate
is 1/24 th of oscillator frequency.
The operation of the timers/counters is controlled by two special function
registers, TMOD and TCON respectively.

101. Timer Mode control (TMOD) Special Function Register:
TMOD register is not bit addressable.
TMOD Address: 89 H
Various bits of TMOD are described as follows -
Gate: This is an OR Gate enabled bit which controls the effect of on
START/STOP of Timer. It is set to one ('1') by the program to enable the interrupt to
start/stop the timer. If TR1/0 in TCON is set and signal on pin is high then the
timer starts counting using either internal clock (timer mode) or external pulses
(counter mode).
C/T’ : It is used for the selection of Counter/Timer mode.
M1, M0: Mode Select Bits.

102. Timer control (TCON) Special function register:
TCON is bit addressable. The address of TCON is 88H. It is partly
related to Timer and partly to interrupt.
The various bits of TCON are as follows:
TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when
processor vectors to execute ISR located at address 001BH.
TR1 : Timer1 run control bit. Set to 1 to start the timer / counter.
TF0 : Timer0 overflow flag. (Similar to TF1)
TR0 : Timer0 run control bit.
IE1 : Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is
cleared when interrupt is processed.
IE0 : Interrupt0 edge flag. (Similar to IE1)
IT1 : Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level
triggered external interrupt.
IT0 : Interrupt0 type control bit. (Similar to IT1)

103. As mentioned earlier, Timers can operate in four different modes.
They are as follows:
Timer Mode-0:
In this mode, the timer is used as a 13-bit UP
counter as follows.
The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count. Upper 3
bits of TLX are ignored. When the counter rolls over from all 0's to all 1's, TFX flag
is set and an interrupt is generated.
The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit
is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the
operation of the counter is controlled by input. This mode is useful to measure
the width of a given pulse fed to input.

104. Timer Mode-1:
This mode is similar to mode-0 except for the
fact that the Timer operates in 16-bit mode.
Timer Mode-2: (Auto-Reload Mode)
This is a 8 bit counter/timer operation. Counting is performed in TLX while THX
stores a constant value. In this mode when the timer overflows i.e. TLX becomes
FFH, it is fed with the value stored in THX. For example if we load THX with 50H
then the timer in mode 2 will count from 50H to FFH. After that 50H is again
reloaded. This mode is useful in applications like fixed time sampling.

105. Timer Mode-3:
Timer 1 in mode-3 simply holds its count. The effect is same as
setting TR1=0. Timer0 in mode-3 establishes TL0 and TH0 as
Two separate counters. Control bits TR1 and TF1 are used by
Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are
available to Timer-0 lower 8 bits(TL0).

106. Interrupts
8051 provides 5 vectored interrupts. They are -
i. INT0’ ii. TF0 iii. INT1’ iv. TF1 v. RI/TI
Out of these, INT0’ and INT0’ are external interrupts whereas
Timer and Serial port interrupts are generated internally. The
external interrupts could be negative edge triggered or low
level triggered. All these interrupt, when activated, set the
corresponding interrupt flags. Except for serial interrupt, the
interrupt flags are cleared when the processor branches to the
Interrupt Service Routine (ISR). The external interrupt flags are
cleared on branching to Interrupt Service Routine (ISR),
provided the interrupt is negative edge triggered. For low level
triggered external interrupt as well as for serial interrupt, the
corresponding flags have to be cleared by software by the
programmer.

107. The schematic representation of the interrupts
is as follows -