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Power Electronics Devices
&
Phase Controlled Circuits
(MEPE – 102)
LABORATORY MANUAL
V SEMESTER B.E. (Electrical & Electronics)
(Academic year 2013 -2014 )
Student Name
Roll. Number
Batch No.
Department of Electrical and Electronics Engineering
JAWAHARLAL INSTITUDE OF TECNOLOGY, BORAWAN
(Rajiv Gandhi Proudyogiki Vishwavidyalaya University, Bhopal)
Jawaharlal Institute of Technology
(Experiment List)
Doc. Type – Experiment
List
Faculty Name: -
Subject Name (Code): - Power electronics Devices & Circuits (EX-504)
Session:- Jul-Dec 2012 Batch:- 2010-2014
Branch: - Electrical & Electronics Year- I Semester:-I
Exp.
No.
Experiment list Grade Date Signature
1 VI CHARACTERISTICSOF SCR.
2 VI CHARACTERISTICSOF DIAC.
3 VI CHARACTERISTICSOF BJT.
4 CHARACTERISTICSOF TRIAC.
5 VI CHARACTERISTICS& TRANSFER CHARACTERISTICS OF MOSFET.
6 OUTPUT CHARACTERISTICS&TRANSFER CHARACTERISTICS OF IGBT.
7 SINGLE PHASE SCR HALF CONTROLLED CONVERTER WITH R LOAD.
8 1Φ SCR FULLY CONTROLLED CONVERTER WITH R-LOAD.
9 STUDY OF 3Φ SCR HALF CONTROLLED CONVERTER.
10 STUDY OF 3Φ SCR FULLY CONTROLLED CONVERTER.
11 STUDY OF CLASSES OF COMMUTATIONA,B,C,D,E,F.
Signature of External Signature of Internal
Name ……………………. Name …………………..
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.1
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 1
AIM:-
To study V-I characteristics of S.C.R. and determine the Break over Voltage, Holding current &
Latching current.
EQUIPMENT REQUIRED:-
Setup board, Connecting Wires, Digital Multimeter
THEORY:-
Thyristor (generally known as SCR) is a four layer, three junction, PNPN semiconductor switching
device. It has three terminals, anode cathode and gate. Basically, a Thyristor consists of four layers of
alternate p-type and n-type silicon semiconductors forming three junctions j1, j2and j3 . A gate terminal is
usually kept near the cathode terminal. The terminal connected to outer p region is called anode (A), the
terminated connected to outer n region is called cathode and that connected to inner p region is called the
gate (G). The symbol of SCR is shown in figure.
Fig - 1(a) Fig-1(b) Fig-1(c)
Fig -1(d) V-I Characteristic
A circuit diagram for obtaining static V-I characteristics of a Thyristor is shown in fig.
Fig-1(e)
Fig-1(f)
The anode and cathode are connected to main source through the load. The gate and cathode are fed from
a source Vs which gives positive gate current from gate to cathode. Fig. shown static V-I characteristics
of Thyristor .Va is the anode voltage across Thyristor terminals A, K and Ia is the anode current. Fig
reveals that a Thyristor has three basic modes of operation, namely, reverse blocking mode, forward
blocking mode (off-state) and forward conduction mode (on-state) .These three modes of operation are
now discussed below.
(a). When cathode is made positive with respect to anode with gate open, Thyristor is reverse biased.
Junction j1,j3 are reverse biased whereas junction j2 is forward biased .
The device behaves like two diodes connected in series with reverse voltage appearing across them. A
small leakage current of the order of a few milliampeares or few microamperes flows depending upon the
SCR rating. This is reverse blocking mode, called reverse breakdown voltage Vbr , an avalanche occurs at
j1 and j3 and the reverse current increases rapidly. A large current associated with Vbb gives rise to more
losses in the Thyristor. This may lead to Thyristor damage as the junction temperature may exceed its
permissible temperature rise . It should, therefore, be ensured that maximum working reverse voltage
across a SCR does not exceed Vbr.
(b). Forward blocking mode: When anode is positive with respect to the cathode with gate circuit open,
SCR is said to be forward biased. During this mode, junction j1, j3 are forward biased but junction j2 is
reversed biased. In this mode, a small current, called forward leakage current, flows.
In case the forward voltage is increased, then the reverse biased junction j2 will have an avalanche
breakdown at a voltage called forward break over voltage Vbo.
When forward voltage is less than Vbo, Thyristor offers high impedance. Therefore, a SCR can be treated
as an open switch even in the forward blocking mode.
(C). Forward conduction mode: In this mode, SCR conducts currents from anode to cathode with a very
small voltage drop across it. A SCR is brought from forward blocking mode to forward conduction mode
by turning it on by exceeding the forward break over voltage or by applying a gate4 pulse between gate
and cathode. In this mode, SCR is on state and behaves like a closed switch. Voltage drop across
Thyristor in the on state is of the order of 1 to 2 volt depending on the rating of Thyristor . This voltage
drop increases slightly with UN-Increase in anode current. In conduction mode anode current is limited
by load impedance alone as voltage drop across Thyristor quite small. This small voltage drop Vt across
the device is due holmic drop in four layers.
SPECIFIC TERMINOLOGY:-
Break over Current (Ibo) - Principal current at break over point
Break over Voltage (Vbo) - Principal voltage at the break over point
Gate Trigger current (Igt) - Minimum gate current required to maintain the SCR in the on State.
Holding Current (Ih) - Minimum principal current required to maintain SCR in the on state.
Latching Current (IL) - Minimum principal current required to maintain SCR in the on state
Immediately after the switching from off state to on state has occurred and the triggering
Signal has been removed
ON- State Voltage (Vt) - Principal voltage when the SCR is in on state
Gate trigger Voltage (VGT) - Gate voltage required to produce the gate trigger current
ON-State Current (IT) - Principal current when the SCR is in the on state
PROCEDURE:-
1) Connection as made as per the circuit diagram.
2) Connect multimeter across the Thyristor (anode- cathode), across the supply terminal Vsto measure
gate voltage Vg, Va and Vs (all in DC mode). An ammeter of the mA range is connected to measure the
load current IL.
3) Keep initially the gate potential Vg at very low value. Vary the supply voltage Vs in steps and note
whether ammeter shows any reading. For every step of Vs note the ammeter. Also note corresponding
readings of Va respectively.
4) If ammeter doesn’t indicate any reading, increase the gate potential Vg to some higher value and
follow the step no. (3).
5) Further increase the gate potential to some higher values and repeat the procedure followed in step
no(3).
6) Tabulate the reading in the observation column.
7).Finally a graph is drawn between anode current (Ia=IL = Load current) and the device voltage Vs
respectively.
OBSERVATION TABLE:-
For Ig1 =……….. = constant.
S.n. Anode to Cathode voltage
(Vak)volt
Anode current (Ia)amp.
For Ig2 =……….. = constant.
S.No Anode to Cathode voltage
(Vak)volt
Anode current (Ia)amp.
GRAPH-
PANAL DIAGRAM-
RESULT-
Thus the V-I characteristics of SCR and the Break over Voltage, Holding current & Latching
current have been determined.
QUESTIONS-
1. Define Holding current, Latching current, Breakdown voltage.?
2. What is meant by leakage current.?
3. Mention the applications of SCR?
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.2
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 2
AIM:-
To study V-I characteristics of Diac with both A.C. & D.C. input voltages.
EQUIPMENT REQUIRED:-
Setup board, Connecting Wires, Digital Multi meter
INTRODUCTION:-
It is two terminal three layer semiconductor device as shown in FIG.1 (a). It is a bidirectional
diode i.e. it can be made to conduct in either direction. It has no gate terminal. FIG. 1(b) shown circuit
symbol. Switching from off state to on state may be done by simply exceeding the avalanche breakdown
voltage in either direction. The two p-regions have similar doping characteristics resulting in symmetrical
switching characteristics for both positive and negative voltages. Applied voltage of either polarity results
in a small saturation. Current across reveres biased pn junction when the applied voltage is exceed the
avalanche break down voltage ., The Diac current rises sharply as shown in FIG.2 .In this on condition
,the voltage across the Diac decreases with .Increasing current and the device therefore, offers negative
differential resistance. Diac is mainly used a trigger device power control systems.
Fig.2(a) Junction diagram of daic Fig.2 (b). Symbol of Diac
Fig.2(c) V.I characterstics of Diac
Fig.2(d) AC phase control Fig.2(e) Output Waveform
HARDWARE SPECIFICATIONS:-
1. Diac characteristics circuit arrangement.
2. Variable D.C. power supply 0 – +35V & 500mA provided on board
3. A.C. source 36 v 50 Hz provide on board.
4. User manual set of patch cord –stackable(4) & non stackable (2)
EXPERIMENTAL PROCEDURE:-
Switch on the experimental board by connecting the power card to the ac mains.
1. Connect the circuit as shown in fig .2(a) .
2. By vairing the input voltage, not down the reading of out put voltmeter and current
meter.(make sure that potentiometer is in minimum position)
3. Draw a graph between voltage v and current i .(it is shown in fig.2(b)
4. Reverse the Diac and connect the input voltage and repeat the steps 2, 3&4.
5. Also observe the waveforms by giving A.C. voltage provided on the board as shown in fig.3 (a)
and observe the wave form as shown in fig.3(b)
OBSERVATION TABLE:-
S.N. VOLTAGE
(DIAC)
CURRENT(OUT)
GRAPH:-
RESULT:-
QUESTION:-
1. What is DIAC & explain with its relative diagram ?
2. Draw the VI characterstics of DIAC?
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.3
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 3
AIM :-
To study V-I characteristics of BJT
EQUIPMENT REQUIRED:-
Setup Board, Ammeter,Volt Meter, Connecting cords.
THEORY:-
Transistors are known as a three terminals semiconductor devices. There are two main types:
bipolar junction transistors (BJT) and Field-effect transistors (FET). The BJT is made of either
germanium or silicon. Each of these materials is "doped" to give the n-type (in which electrons are the
majority carriers) and p-type ( holes are the majority carriers). The BJT device is made as follows: a thin
region of n-type material is sandwiched between two regions of p-type material to make a pnp transistor.
The same method is used to make a npn transistor. The boundaries between the n and p regions in a BJT
are called junctions and the corresponding user terminal names for the npn regions are the Collector, the
Base, and the Emitter. BJTs are current controlled devices. In silicon BJT, the forward bias on the base-
emitter junction must exceed 0.7 V to activate the device and to allow the majority carriers (current) to
flow across the junction with little resistance. In germanium transistors the forward bias must exceed 0.3
V. Fig.3(a) shows the BJT symbol for npn and pnp-type. The second type of the three terminal
semiconductor devices is the field-effect transistors FET. Metal-Oxide semiconductor Field-Effect
Transistor (MOSFET) is the most popular kind of the field-effect transistors. It is characterized as a
voltage controlled device. The source and drain of a MOSFET are formed by diffusing impurities into a
substrate of one type (n-type or p-type) to make regions of opposite type. The gate consists of a layer of
aluminum evaporated on to a very thin layer of silicon dioxide, which insulates it from the substrate. The
main advantages of the MOSFET over the BJT are: easy to manufacture, small size, high input
impedance, and less power consumption.
MSOFET is considered the basic building cell in most of the VLSI applications, such as, digital
logic, memories, microprocessors, microcontrollers, buffer amplifiers, and analog switches. However the
BJT maintains its position in the applications that require high power and high frequencies. Fig.3(b)
shows the MOSFET symbol for N-channel, and P-channel MOSFET transistors (depletion type).
Fig. 3.(a) Fig. 3(b)
The DC bias, and circuits configurations are the two main issues that concern the first time circuit
designer. The DC bias establishes the static operating point for the device, while the decision of using a
certain configuration depends mainly on the type of application for example, a current source or voltage
amplifier with high input impedance. In the following sections you will practice a simple approach to
establish the operating point of the BJT by looking at the V-I characteristics or maximum rating of the
device used in the design. Also you will explore the different types of transistor circuit configurations and
amplifier classes.
a) DC Bias and Operating Point
The DC bias is used to establish a starting point in the V-I characteristic of any active device
such as BJTs and MOSFETs. The bias is made possible by using DC power source, and a number of
resistive elements. Therefore, the simple electronic circuit will be consisting of the three terminal device
surrounded by a resistive circuit and all attached to a single or double DC power supply. The location of
the operating point in a BJT ( Q ) depends on the following values CI , CEV , BI , and can be written as
fQ  ( CI , CEV , BI ). The temperature variation will cause a change in the DC current gain , and in the
collector reverse saturation current COI . Consequently this thermal drift will increment the current CI
and change the location of the operating point. If the thermal drift continues, the device could be driven
into the saturation region without applying any input signal. A number of biasing schemes have been used
in designing BJT circuits to avoid such instability. The self-bias CE with single power supply is shown in
fig. 3(b). The resistor ER is used to stabilize the bias by providing a DC negative feedback in the input
circuit. Adding a bypass capacitor EC across ER can eliminate the effect of ER at signal frequencies.
One quick choice of 1R , and 2R can be achieved using the ratio 1/3 for example if you choose kR 121  ,
then kR 42  , and all related values can be computed. The operating point location can be chosen the
same way for example if you want to locate the Q point at the middle of the V-I characteristics simply
choose
2
CC
CE
V
V  , and
)(*22 EC
CCsaturationC
C
RR
VI
I

 , obviously these initial choices are subject to
change till the desired response of the circuits is obtained. The value of CEV is used to check if the
operating point has gone into the saturation or the cut-off region. If 0CEV this, will be an indication
that the transistor is operating in the saturation region. If CCCE VV  this, will be an indication that the
transistor is operating in the cutoff region. In the MOSFET circuits, biasing technique that stabilize or
controls the deviations in the Q point is similar to those used in BJT circuits see figure 3(b).
C C
B B
E E
NPN PNP
Gate
Source
Drain D
G
S
N-ChannelP-Channel
VDD
Vout
Vin
D
S
G
RG1
RG2 Cs
RD
Rs
Vcc
Vout
Vin
R1
R2
Rc
RE
CE
C
E
B
VCE
Fig.3(c)
b) Single -Stage Amplifier configurations
Three different amplifier circuit configurations can be obtained by selecting one of the
transistor terminals as a common between input circuit and output circuit. In the BJT circuits, figure 3(c)
shows these configurations, which are known as Common Base (CB), Common Emitter (CE), and
Common Collector (CC). These amplifier circuit configurations lead to significant changes in the
amplifier characteristics. The most noticeable changes in CC (emitter follower) configurations are: the
input resistance becomes very high and the gain is close to the unity. These specific characteristics are
translated into a useful application known as buffer amplifier. Therefore amplifier configurations are
employed to widen the scope of the amplifier circuit applications.
Input Output
CB
Input
Output
CC
Input
Output
CE
VccVccVcc
R R R
Fig. 3.(d)
c) Transistors As A switch
The initial location of the operating point Q within the V-I characteristics of the transistors is
chosen according to the type of applications. Some voltage amplifier require that the Q point to be in
the middle of the V-I characteristic (active region) so that when a signal applied to the amplifier the Q
point would swing evenly with the positive and the negative portions. This type of amplifier application is
called class AB amplifier. In another type of amplifier the initial location of the Q point is in the cutoff
region. In this case the amplifier will be off when no signal is applied to its input and on when the signal
of the right polarity is applied. This type of amplifier is classified as a class B amplifier and one example
is push-pull power amplifier. The push-pull amplifier uses the full span of the V-I characteristics to
amplify the positive or the negative half of the input signal. Another application requires the Q point to
swing between the cutoff and the saturation. This means that the transistor initial Q point is in the cutoff
region. A positive input signal will drive the transistor to the saturation region. This extreme swing of the
operating point Q is needed in some applications such as switching circuits. Figure 3(d)shows the digital
logic inverter using the BJT and the MOSFET operating in Cutoff-Saturation mode. The truth table for
both circuits is shown below.
Fig. 3(e)V I Characteristics of Bipolar Junction Transister
Vout
Vout
VDD
Vin
Vin
VCC
RC
RB
Input BJT output MOSFET Output
0 or ground Vcc Vdd
High or Vin 0 or ground 0 or ground
Fig 3.(f) Ohmic regions
RESULT:-
QUESTIONS :-
1. What is BJT ?
2. Draw the VI characteristics of BJT?
3. What are the advantages of BJT?
4. What are the application of BJT?
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.4
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 4
AIM :-
To Study the volt ampere characteristics of the TRIC.
EQUIPMENT REQUIRED:-
Setup Board, Ammeter, Volt Meter,Connecting cords.
INTRODUCTION :-
In the Thyristor family, after the SCR, the TRIAC is the most widely used device
for power control. Fig-a gives the structure of the TRIAC while Fig -b, gives its circuit symbol. In
similarity with an SCR, TRIAC is also a four layer semiconductor device with three terminals.
Main Terminal 1(MT1)
Main Terminal 2(MT2)
Gate Terminal G.
THEORY:-
However unlike SCR, a TRIC is bidirectional device i.e. ,it can block voltages of either polarity and
conduct in either direction. A pulse of either polarity can switch A TRIC form OFF state to ON state.
Accordingly a TRIC may be considered as to SCR’S connected in parallel but in opposite direction.
This becomes obvious from the study of the structure shown Fig 4(a). Gate terminal makes ohmic
(non rectifying) contacts with both n and p material, thus permitting either a positive or a negative trigger
pulse to causes current flow. Fig-gives volt ampere characteristics of a TRIAC .It may be seen that
TRIAC has same ON state and OFF state areas as SCR but this is true for positive and negative applied
voltage. Positive bias operation of TRIAC is taken as one when the terminal 2 is positive with respect to
terminal 1. This is shown in the first quadrant in Fig2. On the other hand negative bias operation of
TRIAC is one in which terminal w is negative with respect to terminal 1 as shown in third quadrant . In
similarly with an SCR and TRIAC change state from OFF to ON AT THE breakdown voltage Vbo.
Gate triggering may occur in one of the following diodes.
Quadrant I operation : V21 positive : Vg1 positive.
Quadrant II operation : V21 positive : Vg1 negative.
Quadrant III operation : V21 negative : Vg1 negative.
Quadrant IV operation : V21 negative : Vg1 positive.
Fig. 4(a)V-I characteristics
Fig.4 (b) Symbol Fig.4(c) Structure of Triac
EXPERIMENTAL PROCEDURE :-
1). Switch on the experimental kit.
2). Connect the circuit diagram as shown in fig-2.
3). Connect ammeter in MT2 ckt. and voltmeter across TRIAC and DMM IN GATE CIRCUIT.
4).Adjust gate current Ig =3.10 Ma WITH dc2 POT and series resistance pot in the gate circuit .
5). Vary DC1 from its minimum and not down the reading of volt meter Vt and current meter
It and tabulate these value in the following table.
Ig = 3.10
s.no Vt volts It mA
Find Vbo from the above table
6). Put Ig = 3.3 mA and again tabulate these values
Ig = 3.3 mA
S.No. Vt volts It mA
7). Reverse the connection of DC1 volt meter and current meter and repeat the step from 3 to 5.
8). Draw a graph between TRIAC voltage Vt and TRIAC current It at different gate current Ig.
GRAPH:-
RESULT:-
QUESTIONS :-
1. Explain the construction of TRIAC ?
2. Draw the V-I characteristics of TRIAC & explain it ?
3. Differentiate between TRIAC & SCR ?
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.5
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 5
AIM :-
To Study the volt ampere characteristics of the MOSFET.
EQUIPMENT REQUIRED :-
Setup Board, Ammeter, Volt Meter, Connecting cords.
THEORETICAL BACKGROUND :-
Metal oxide semiconductor field effect transistor is an important. Semiconductor device and is
widely used in many circuit application. The impedance of a MOSFET is much more than that of a FET
because a very small gate leakage current. The p-channel MOSFET consist of a lightly doped n-type
substrate into which to highly doped p-region are diffused as shown in fig1 this p+ section ,which will act
as the sources and drain , are separated by about 5-10 µ. A thin (1000°-2000°A) layer of insulating silicon
dioxide (SiO2) is grown over the surface of the structure, and holes are cut in to the oxide layer allowing
contact with the source and drain . Than the gate metal area is overlap on the oxide, covering the entire
channel region. Simultaneously, metal contacts are made to drain and source, as shown in fig1.the contact
to the metal over the channel area is the gate terminal. The chip area of a MOSFET is three square miles
or less, which is only about five percent of the reacquired by a bipolar junction transistor. The metal are a
of the gate, in conjunction with the insulating dielectric oxide layer and the semiconductor channel, from
a parallel plate capacitor. The insulating layer of the silicon dioxide is the reason why this device is the
insulator gate field effect transistor. This layer result in an extremely high input resistance 1010Ω -
1015Ω for the MOSFET. The p-channel enhancement MOSFET is the most commonly available filed
effect device and its characteristics will now be described.
The enhancement MOSFET
If we ground the substrate for the structure of fig., apply a negative volt. At the gate , an electric field will
be directed perpendicularly through the oxide . the field will end on “induced” positive charges on the
semiconductor site a shown in fig1 the positive charge, witch are minority career in the n-type substrate ,
from an inversion , layer . as the magnitude of the negative volt. All the gate increase, the induced +Ve
charge in the semiconductor increases. the region beneath the oxide now has p type career , the
conductivity increases and current flow source to drain through the induced channel.Thus the drain
current is enhanced by the negative gate volt.and such a device is called an enhancement type MOSFET.
Fig.5 (a) n channel depletion type MOSFET
Fig.5 (b) p channel depletion type MOSFET
THRESHOLD VOLTAGE:-
The volt. Ampere drain characteristic of a p channel enhancement mode MOSFET are given in fig.2(a).
And its transfer in fig.2(b) the current loss at Vgs>o is very small of Oder few neno-ampere. As Vgs is
made negative current (id) increases slowly at first and them much more rapidly with an increases in Vgs .
The manufactures often indicate the gate source threshold volt. Vgst or vt at witch id which some defined
small values, say 10micro ampere a. current id, on corresponding approximately to the max. Value given
on the drain characteristics and the value of Vgs needed to obtain this current area is usually given on the
manufacturers, specification. The of vt for the p channel standard or MOSFET is typically 4 volt. . it is
common to power supply volt. To typically 5 volt. Used in bipolar integrated circuit, thus various
manufacturing technique have been developed to reduce vt. In general.a low threshold volt allow.
1. The use of a small power supply voltage.
2. Compatible operation with bipolar device.
3. Smaller switching time due to the smaller voltage swing during switching and higher packing
densities.
4.
Three method are use to lower the magnitude of Vt
1. The high threshold MOSFET describe above uses a silicon crystal with (111) orientation. If a
crystal utilized in the (100) direction it is found that a value of Vt result which is above one half
that obtain with (111) orientation.
2. The silicon nitride approaches makes use of a layer of Si3N4 and SiO2 whose dielectric constant
is about twice that of SiO2 along. A fit constructed in this manner decrease Vt to approx – 2V.
3. Polycrystalline silicon doped with boron is used as the gate electrode instead of aluminum. This
reduction in the deference in contact potential between the gate electrode and the gate diectric
reduces Vt .Such devices are called silicon gate MOSTRANSISTOR. All three of fabrication
method described above result in a low threshold MOS has a Vt of approximately 4-6V.
POWER SUPPLY REQUIREMENT
Table-1 gives the voltage customarily used with high-threshold and low-threshold p-channel
MOSFETS. Note that Vss refers to the source. Vdd to the drain and Vgg to the gate supply voltages. The
subscript 1 denotes that the source is grounded and the subscript 2 designates that5 the drain is at ground
potential.
The low-threshold MOS circuits require low power supply voltages and this means less expensive
system power supplies. In addition the input voltages, and this means faster operation another very
desirable feature of low-threshold MOS circuits is that they are directly compatible with bipolar ICCs.
They require and produce essentially the same input and out put signal swing and the system designer has
the flexibility of using MOS and bipolar circuit in the same system.
Fig. 5(c) Depletion type MOSFET
Fig. 5(d) Enhancement type MOSFET
ION IMPLANTATION
The ion implementation technique demonstrated in fig 3 provides very precise control f doping ions of
the proper do pant such as phosphorus or boron accelerated to a high energy of up to 300,000 eV and are
use to bombard the silicon wafer target. The energy of ion determines the depth of penetration in to the
target.In those area where ions implementation is not desired, an aluminum mask or thick (12000°A)
oxide layer absorbs the ion. Virtually any value of Vt can be obtain using ion implementation. In addition,
we see form consequently, due to ion implantation; there is a reduction in Cgd and Cgs.
THE DEPLETION MOSFET
A second type of MOSFET can be made if, to the basic structure of fig1, a channel is defuse between
the source and drain , with same type of impurity as used in source to drain diffusion . Let us now
conceded such an n-channel structure as shown in fig 4 with this device an appreciable drain current Idss
flows for zero gate to source voltage Vgs = o . If the gate voltage –ve , +ve charge are induced in channel
through SiO2 of the gate capacitor. Since the current in an FET is due to majority carrier s (Electron for n-
type material ), the induced +ve charge make the channel less conductivity and the drain current drop as
Vgs is made more –ve .The redistribution of accounts for the designation depletion MOSFET. Note in fug
4b that because of the voltage drop Dew to the drain current, the channel region near the drain is more
depleted than is the volume near the sources. This phenomenon is analogs to that of pinch of occurring in
a jfet at the drain end of the channel. As a matter of fact, the volt ampere characteristics of the depletion
mod MOS and the JFET are to quite smaller.
MOSFET GATE PROTECTION
Since the SiO2 layer of the gate is extremely thin, it may easily be damaged by excessive voltage. An
accumulation of charge on an open circuited gate may result in a large enough field to punch through the
dielectric to prevedent this damage some MOS device are fabricated with a ZENER diode between gate
and substrate. A normal operation this diode is open and has no effect upon the ckt., however , if the
voltage at the gate becomes excessive, than the diode brakes down and the gate potential is limited to a
maximum value equal to the ZENER voltage .
Fig. 5(e) output charactertics of enhancement type MOSFET
CIRCUIT SYMBOLS:-
It is possible to bring out the connection to the substrate axtemilly so as to have a TETRODE device.
Most of the MOSFET however, are triodes, with the substrate internally connected to the source .fig 6
shows the circuit symbol.
Fig. 5(f) Circuit symbol
PROCEDURE:-
1). Connect the circuit as shown in fig 7b for enhancement mode.
2). To draw drain characteristic, keep Vgs= o , and vary Vds and note down the values of drain current
Id for corresponding Vds values tabulate as per table 3a .
3). Keep Vgs = -1V .repeat the above procedure .draw a graph between Vds and Id at deferent values
Of Vgs.
4). To draw the transfer characteristics, keep Vds = 1Vand vary V from 0 -5V and note down the value
of drain current Id corresponding value Vgs and tabulate as per table 3b .
5). Repeat the step 5 for various value of Vds . Draw graph between the Vgs and Id at deferent values
ofVds.
6). Repeat the step 1-5 for various values of Vds . Draw graph between Vgs and Id at deferent values
Of Vgs.
GRAPH:-
RESULT :-
QUESTIONS:-
1). What is power MOSFET ?
2). What are the supplication of power MOSFET?
3). Compare MOSFET and BJT ?
4). Explain out put and transfer characteristic of MOSFET?
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.6
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 6
AIM :-
To Study the output & transfer characteristics of the IGBT .
EQUIPMENT REQUIRED :-
Setup Board, Ammeter, Volt Meter, Connecting cords.
THEORETICAL BACKGROUND :-
The insulated gate bipolar transistor combines the positive attributes of BJTs and MOSFETs
BJT have lower conduction losses in the on-state especially in devices with larger blocking voltages, but
have longer switching times, especially at turn – off while MOSFETs can be turned on off much faster,
but their on-state conduction losses are larger, especially in devices rated for higher blocking voltage
capabilities in addition to fast switching speeds.
IGBTs have vertical structure as shown infig1 .this structure is quite similar to that of the vertical
diffused MOSFET except for the presence of the p+ layer that forms the drain of the IGBT. This layer
forms a pn junction (labeled j1 in the figure),which injects minority carriers into what would appear to be
the drain drift region of the vertical MOSFET. The gate and source of the IGBT are laid out in an inter
digitized geometry similar to the used for the vertical MOSFET.
CIRCUIT DIAGRAM:-
Fig.6(a) Circuit diagram
The IGBT structure shown in fig has a parasitic Thyristor which could latch up in IGBT s if it is turned
on. Then n+ buffer layer between the p+drain contact and the n+ drift layer, with proper doing density
and thickness, can significantly improve the operation of the IGBT, in two important respects .it lower to
the on state voltage drop of the device and, shortens the turn off time. On the other hand, the presence of
this layer greatly reduces the reverse blocking capability of the IGBT.
Fig.6(b) Output characteristics of IGBT
Fig.6(c) transfer characteristic
EXPERIMENTAL PROCEDURE :-
To draw output characteristics of IGBT
1. Connect the circuit as shown in fig.3.
2. To draw out put characteristics keep VGE = 5.6V and slowly increasing Vce and not the point at which
the collector current Ic starts to flow increase VCE and not the values of Ic at every step and plot the
characteristics between VCE &IC
S.NO. VCE IC
TO DRAW TRANSFER CHARACTERISTICS OF IGBT
1. Connect the circuit as shown in fig3.
2. Set VCE = 10V.
3. VGE = 0V then IC will be zero .increase VGE and the voltage at which IC start flowing this is
the threshold voltage and this points.
4. Increase VGE un steps 0.5v till about 7v .note IC at every step and these points.
S.No. vge ic
GRAPH:-
RESULT:-
QUESTIONS:
1. What is IGBT?
2. What is the application of IGBT?
3. Compare MOSFET BJT & IGBT?
4. Explain the working principle of IGBT?
5. Explain output & transfer characteristic of IGBT?
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.7
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 7
AIM :-
To Study the single phase half wave controlled rectifier with R & RL loads and with free
wheeling diode.
EQUIPMENT REQUIRED:-
Single phase half wave rectifier setup board, Patch cords oscilloscope.
THEORY:-
Line commuted controlled rectifiers from the back bone of static control of electric power in
modern industries. although the half wave controlled rectifier configurations, but its study helps in
understanding the behavior of full wave configuration.
CIRCUIT DIAGRAM:
Fig.7(a) single phase half wave controlled rectifier is resistive load
Let the Acvoltage fed to controlled rectifier is given by
Vs = Vm Sin ωt ………………………………………….(1)
Where Vm =peak value of source voltage
ω = angular frequency of source voltage, t = time
at ωt = 0 , the source voltage Vs starts increasing in positive direction making the anode voltage above its
cathode voltage. thus after ωt = 0,SCR is forward biased .under this condition ,if a gate pulse of suitable
magnitude is applied the SCR will be triggered into conduction . the SCR fails to block the voltage and
almost entire source voltage appears across load . αis the angle in radians at which the gate pulse is
applied . this is measured from the moment the SCR has become forward biased. During the period of
conduction the load current is given by
𝑖𝑙=
𝑉 𝑚
𝑅
𝑆𝑖𝑛𝜔𝑡
…………………..(2)
at ωt = π, the source voltage becomes zero hence the load current is also reduced to zero and SCR turns
off. The turn off process is assisted by the reversal of source voltage. Turn off or commutation of SCR is
achieved naturally by reversalof source /line voltage is called natural or line commutation.
The mean out put voltage cane be evaluated as follows:
𝑉𝑑𝑐 =
𝑉 𝑚
2𝜋
(1 + cos 𝛼)…………(3)
Effect of load inductance
The natural effect of inductance is to delay the change in current at ωt = α .the load current for resistive
load is given by
𝑉 𝑚
𝑅
𝑆𝑖𝑛 𝛼………………………..(4)
When the load inductance is present the load current does not build up to his value but increase slowly .at
ωt = π,the current rise to fall to zero but the energy stored in the load inductance develops an EMF
E=
𝑑𝑖
𝑑𝑡
… … … … … (5)
Such that when added to source voltage ,causes the SCR to be forward biased. Thus SCR keeps on
conducting beyond ωt = π up to ωt = π+σ at ωt = π+σSCR current reduce zero and SCR turned off . the
source remains contend to load from αtoπ +σ. this results in negative voltage appearing across load .the
associated wave forms and circuit are shown as follows:
Figure. Single phase half wave controlled rectifier with RL load
The mean load voltage can now be obtained as:
𝑉𝑑𝑐=
1
2𝜋
𝑉𝑚sin( 𝜔𝑡) 𝑑𝜔𝑡
𝑉𝑑𝑐=
1
2𝜋
𝑉𝑚 (–cos(𝜔𝑡))
𝑉𝑑𝑐=
1
2𝜋
𝑉𝑚 𝑐𝑜𝑠𝛼+𝑐𝑜𝑠𝜎
Thus for the same firing angle α the output voltage Vac for inductive load is less than the same for
resistive load. the calculation of is not straight forward ,as it involves the solution of transcendental
equation. This equation is given as follows:
i = Vm/Z sin(𝜔𝑡 − 𝑓)+ sin ∅𝑒(−𝜔𝑡/ tan ∅)
Z = R2 +ω2 L2
∅ = 𝜔𝐿/𝑅
By substituting I =0, ωt =φ can be obtained.
PROCEDURE: for R load
1. connect the setup board as shown in the figure1.
2. Adjust Rt for delay angle of 30.
3. Measure Vs.
4. Measure Vdc with a multimeter.
5. Observe and trace source voltage, SCR current, SCR voltage, load voltage and load current wave
forms.
6. Repeat step 2 to 5 for different delay angles record the observation in table.
OBSERVATION TABLE:-
S.No. Delay Angle
Mean output voltage Vdc
Remarks
Measured Calculated
For RL Load
1. Connect the setup as shown in figure 2.
2. Adjust the resistance Rt for a delay angle of 30 degree.
3. Measure Vs.
4. Measure Vdc with a multimeter.
5. Observe and trace source voltage , SCR voltage, SCR current, load voltage &load current
wave forms.
6. Repeat steps 2 through 4 for different delay angles. Record the observations in the table.
S.No. Delay Angle
Mean output voltage Vdc
Remarks
Measured Calculated
PROCEDURE
1.Calculate Vdc for measured vaues of Vm ,and for each of the thee configurations.
2.Comment on wave forms obtained.
3.Sketch the supply primary current for each configurations neglecting the transformer
excitation current .
4.Comment on the Vdc obtained for the same angle for each of the three configurations.
RESULT
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.8
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 8
AIM :-
To Study the single phase full wave controlled rectifier with R loads .
EQUIPMENT REQUIRED:-
Single phase full wave rectifier setup board, patch cords oscilloscope.
THEORY:-
Once of the types of controlled rectifier is fully controlled and semiconductor rectifier. A fully-
controlled circuit contains only thyristers (semiconductor controlled rectifiers (SCR)), whereas a semi-
controlled rectifier circuit is made up of both SCR and diodes as shown in Fig.(1). Due to presence of
diodes, free-wheeling operation takes place without allowing the bridge output voltage to become
negative..
CIRCUIT DIAGRAM:
Fig.8(a) Single-phase fully controlled bridge rectifier
Fig.8(b) Waveforms of a fully controlled bridge rectifier with resistive load.
As shown in Fig. thyristor T1can be fired into the ON state at any time provided that voltage VT1> 0. The
firing pulses are delayed by an angle a with respect to the instant where diodes would conduct. Thyristor
T1remains in the ON state until the load current tries to go to a negative value. Thyristor T2is fired into
the ON state when VT2> 0, which corresponds in Fig. to the condition at which V2> 0. The mean value
of the load voltage with resistive load is given by
Figure 2 presents the behavior of the fully controlled rectifier with resistive-inductive load (with L→∞).
The high-load inductance generates a perfectly filtered current and the rectifier behaves like a current
source. With continuous load current, thyristors T1and T2remain in the on-state beyond the positive half-
wave of the source voltage Vs. For this reason, the load voltage vdcan have a negative instantaneous
value. The firing of thyristors T3and T4has two effects:
a. they turn off thyristors T1and T2; and
b. After the commutation, they conduct the load current.
This is the main reason why this type of converter is called a ‘‘naturally commutated’’ or ‘‘line
commutated’’ rectifier. The supply current iShas the square waveform shown in Fig.(2) for continuous
conduction. In this case, the average load voltage is given by:
PROCEDURE :-
1. Connect the single phase full wave controlled rectifier circuit shown in Fig.8(a) on the power electronic
trainer.
2. Turn on the power
3. Plot the input and output waveforms on the same graph paper.
4. Measure the average and RMS output voltage by connect the AVO meter across load resistance.
5. Turn off the power
6. Add the inductive load on the output as shown in Fig.8(b). With L=10mH measure the output voltage
and plot the output waveform.
7. Repeat step 6 with L=100mH measure the output voltage and plot the output waveforms.
8. Repeat step 6 & 7 with connect the freewheeling diode across the load.
OBSERVATION TABLE:
S.No. Delay Angle
Mean output voltage Vdc
Remarks
Measured Calculated
GRAPH:-
DISCUSSION AND CALCULATIONS :-
1. Compare between the practical and theoretical results for input and output voltages and currents.
2. What does parameters of the single phase full wave controlled rectifiers.
3. Give same application of the single phase controlled rectifiers .
RESULT:-
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.9
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 9
AIM:-
Study of 3Φ SCR half controlled converter
THEORY:-
Phase controlled AC-DC converters employing thyristor are extensively used for changing
constant ac input voltage to controlled dc output voltage. In phase-controlled rectifiers, a thyristor is tuned
off as AC supply voltage reverse biases it, provided anode current has fallen to level below the holding
current.
Controlled rectifiers have a wide range of applications, from small rectifiers to large high voltage
direct current (HVDC) transmission systems. They are used for electrochemical processes, many kinds of
motor drives, traction equipment, controlled power supplies, and many other applications.
Three- phase half wave controlled rectifier:-
Fig.(1) shows the half-wave rectifier uses three common-cathode thyristor arrangements. In this figure,
the power supply and the transformer are assumed ideal. The thyristor will conduct (ON state), when the
anode-to-cathode voltage VAKis positive, and a firing current pulse iGis applied to the gate terminal. To
controls the load voltage delaying the firing pulse by an angle (α). As shown in Fig. (a), the firing angle α
is measured from the crossing point between the phase supply voltages. At that point, the anode-to-
cathode thyristor voltage VAKbegins to be positive.
CIRCUIT DIGRAM:-
Fig.9(a): Three-phase half-wave rectifier
With the help of Fig. the load average voltage can be evaluated and is given by
Where Vmax is the secondary phase-to-neutral peak voltage, its root mean square (rms) value, and ω
is the angular frequency of the main power supply. rmsNfV
Fig.9 (b):Instantaneous ds voltaghVD, average dc voltage VD,and firing angle
PROCEDURE:-
1. Connect the three-phase half wave controlled rectifier circuit shown in Fig.(1) on the power
electronic trainer.
2. Turn on the power.
3. By use oscilloscope, plot the input and output waveforms on the same graph paper" same axis".
4. Measure the average and RMS output voltage by connect the AVO meter across load resistance.
5. Turn off the power
6. Use an inductive load. With L=10mH measure the output voltage and plot the output waveform.
7. Repeat step 6 with L=100mH measure the output voltage and plot the output waveforms.
8. Repeat step 6 & 7 with connect the freewheeling diode across the load.
DISCUSSION AND CALCULATIONS :
1. Compare between the practical and theoretical results for input and output voltages and currents.
2. Design a high voltage power supply for CO2laser, when the optical output power is 8watt. The
current and voltage electronically highly stabilized DC power unit has a nominal output 50mA and
5kV. Pumping under optimal conditions (maximum laser output), a current of 18mA at 3.0 kV is
observed.
3. Design three-phase half wave controlled rectifier.
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.10
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 10
AIM:-
Study of 3Φ fully controlled converter
THEORY:-
Phase controlled AC-DC converters employing thyristor are extensively used for changing
constant ac input voltage to controlled dc output voltage. In phase-controlled rectifiers, a thyristor is tuned
off as AC supply voltage reverse biases it, provided anode current has fallen to level below the holding
current. Fig. shows the three-phase bridge rectifier. The configuration does not need any special
transformer, and works as a 6-pulse rectifier. The series characteristic of this rectifier produces a dc
voltage twice the value of the half-wave rectifier .
CIRCUIT DIGRAM:-
Fig.10 (a) Three-phase full-wave rectifier
The load average voltage is given by:-
Fig.10 (b) output wave form
PROCEDURE:-
1. Connect the three-phase full wave controlled rectifier circuit shown in Fig.on the power
2. Turn on the power.
3. By use oscilloscope, plot the input and output waveforms on the same graph paper" same axis".
4. Measure the average and RMS output voltage by connect the AVO meter across load resistance.
5. Turn off the power
6. Use an inductive load. With L=100mH measure the output voltage and plot the output waveform.
7. Repeat step 6 with L=100mH measure the output voltage and plot the output waveforms.
8. Repeat step 6 & 7 with connect the freewheeling diode across the load.
9. Connect the three-phase bridge half-control rectifier circuit shown in Fig.
10. Repeat steps (2-7).
DISCUSSION AND CALCULATIONS:-
1. Compare between the practical and theoretical results for input and output voltages and currents.
2. Design a high voltage power supply for CO2laser, when the optical output power is 12 watt.
3. The current and voltage electronically highly stabilized DC power unit has a nominal Output 70mA
and 6kV. Pumping under optimal conditions (maximum laser output), a current
of 20mA at 4 kV is observed.
4. Compare between the three-phase half-wave controlled rectifier and three-phase full-wave controlled
rectifier.
Jawaharlal Institute of Technology
Laboratory Manual (MEPE – 102)
Doc. Type –
Experiment No.11
Faculty Name: -
Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits
Branch: -Electrical & Electronics Year- I Semester:-I
EXPERIMENT NO. 11
AIM
Study of classes of commutation A, B, C, D ,E, F.
EQUIPMENT REQUIRED
Setup Board, Oscilloscope, Ammeter, Volt Meter,Connecting cords,30/2A DC Regulated
Power Supply.
THEORETICAL BACKGROUND
Class A, Self commutated by resonating the load
When the SCR is triggered, anode current flows and charges up C with the dot
as positive. The L-C-R form a second order under-damped circuit. The current through the SCR
builds up and completes a half cycle. The inductor current will then attempt to flow through the SCR
in the reverse direction and the SCR will be turned off.
Fig.11(a) resonant load commutated SCR and the corresponding waveforms.
The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into the
resistance in an exponential manner. The SCR is reverse-biased till the capacitor voltages returns to
the level of the supply voltage V.
Class B, Selfcommutated by an L-C circuit:-
The Capacitor C charges up in the dot as positive before a gate pulse is applied to the
SCR. When SCR is triggered, the resulting current has two components.
The constant load current I
load
flows through R - L load. This is ensured by the large reactance
in series with the load and the freewheeling diode clamping it. A sinusoidal current flows through the
resonant L-C circuit to charge-up C with the dot as negative at the end of the half cycle. This current
will then reverse and flow through the SCR in opposition to the load current for a small fraction of
the negative swing till the total current through the SCR becomes zero. The SCR will turn off when
the resonant–circuit (reverse) current is just greater than the load current.
The SCR is turned off if the SCR remains reversed biased for t
q
> t
off
, and the rate of rise of the
reapplied voltage < the rated value.
Fig.11(b) Class B, L-C turn-off
Class C, C or L-C switched by another load–carrying SCR:-
This configuration has two SCRs. One of them may be the main SCR and the
other auxiliary. Both may be load current carrying main SCRs. The configuration may have four
SCRs with the load across the capacitor, with the integral converter supplied from a current source.
Assume SCR
2
is conducting. C then charges up in the polarity shown. When SCR
1
is triggered, C is
switched across SCR
2
via SCR
1
and the discharge current of C opposes the flow of load current in
SCR
2
.
Fig.11(c) Class C turn-off, SCR switched off by another load-carring SCR
Class D, L-C or C switched by an auxiliary SCR:-
The circuit shown in Figure (Class C) can be converted to Class D if the load current is
carried by only one of the SCR’s, the other acting as an auxiliary turn-off SCR. The auxiliary SCR
would have a resistor in its anode lead of say ten times the load resistance.
SCR
A
must be triggered first in order to charge the upper terminal of the capacitor as
positive. As soon as C is charged to the supply voltage, SCR
A
will turn off. If there is substantial
inductance in the input lines, the capacitor may charge to voltages in excess of the supply voltage.
This extra voltage would discharge through the diode-inductor-load circuit.
When SCR
M
is triggered the current flows in two paths: Load current flows through the load and the
commutating current flows through C- SCR
M
-L-D network. The charge on C is reversed and held at
that level by the diode D. When SCR
A
is re-triggered, the voltage across C appears across SCR
M
via
SCR
A
and SCR
M
is turned off. If the load carries a constant current as in Fig. 3.4, the capacitor again
charges linearly to the dot as positive.
Fig.11(d) Class D turn-off. Class D commutation by a C (or LC) switched by an Auxiliary SCR.
Class E – External pulse source for commutation:-
The transformer is designed with sufficient iron and air gap so as not to saturate. It is
capable of carrying the load current with a small voltage drop compared with the supply voltage.
When SCR1 is triggered, current flows through the load and pulse transformer. To turn SCR
1
off a
positive pulse is applied to the cathode of the SCR from an external pulse generator via the pulse
transformer. The capacitor C is only charged to about 1 volt and for the duration of the turn-off pulse
it can be considered to have zero impedance. Thus the pulse from the transformer reverses the
voltage across the SCR, and it supplies the reverse recovery current and holds the voltage negative
for the required turn-off time.
Fig.11(e) Class E commutation
Fig.11(f) wave form of Class E commutation
Class F, AC line commutated:-
If the supply is an alternating voltage, load current will flow during the positive half cycle. With a
highly inductive load, the current may remain continuous for some time till the energy trapped in the load
inductance is dissipated.
Fig.11 (g) Class F, natural commutation by supply voltage
During the negative half cycle, therefore, the SCR will turn off when the load current becomes zero
'naturally'. The negative polarity of the voltage appearing across the outgoing SCR turns it off if the
voltage persists for the rated turn-off period of the device. The duration of the half cycle must be
definitely longer than the turn-off time of the SCR.
QUESTIONS:-
1. How to turn ON and turn OFF time of switch decide the maximum switching frequency?
2. How the reverse recovery current of free wheeldiodes affects the switch current rating?

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238218643 jit final-manual-of-power-elx

  • 1. Get Homework/Assignment Done Homeworkping.com Homework Help https://www.homeworkping.com/ Research Paper help https://www.homeworkping.com/ Online Tutoring https://www.homeworkping.com/ click here for freelancing tutoring sites Power Electronics Devices & Phase Controlled Circuits (MEPE – 102)
  • 2. LABORATORY MANUAL V SEMESTER B.E. (Electrical & Electronics) (Academic year 2013 -2014 ) Student Name Roll. Number Batch No. Department of Electrical and Electronics Engineering JAWAHARLAL INSTITUDE OF TECNOLOGY, BORAWAN (Rajiv Gandhi Proudyogiki Vishwavidyalaya University, Bhopal) Jawaharlal Institute of Technology (Experiment List) Doc. Type – Experiment List Faculty Name: - Subject Name (Code): - Power electronics Devices & Circuits (EX-504) Session:- Jul-Dec 2012 Batch:- 2010-2014 Branch: - Electrical & Electronics Year- I Semester:-I
  • 3. Exp. No. Experiment list Grade Date Signature 1 VI CHARACTERISTICSOF SCR. 2 VI CHARACTERISTICSOF DIAC. 3 VI CHARACTERISTICSOF BJT. 4 CHARACTERISTICSOF TRIAC. 5 VI CHARACTERISTICS& TRANSFER CHARACTERISTICS OF MOSFET. 6 OUTPUT CHARACTERISTICS&TRANSFER CHARACTERISTICS OF IGBT. 7 SINGLE PHASE SCR HALF CONTROLLED CONVERTER WITH R LOAD. 8 1Φ SCR FULLY CONTROLLED CONVERTER WITH R-LOAD. 9 STUDY OF 3Φ SCR HALF CONTROLLED CONVERTER. 10 STUDY OF 3Φ SCR FULLY CONTROLLED CONVERTER. 11 STUDY OF CLASSES OF COMMUTATIONA,B,C,D,E,F. Signature of External Signature of Internal Name ……………………. Name ………………….. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.1 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 1 AIM:- To study V-I characteristics of S.C.R. and determine the Break over Voltage, Holding current & Latching current.
  • 4. EQUIPMENT REQUIRED:- Setup board, Connecting Wires, Digital Multimeter THEORY:- Thyristor (generally known as SCR) is a four layer, three junction, PNPN semiconductor switching device. It has three terminals, anode cathode and gate. Basically, a Thyristor consists of four layers of alternate p-type and n-type silicon semiconductors forming three junctions j1, j2and j3 . A gate terminal is usually kept near the cathode terminal. The terminal connected to outer p region is called anode (A), the terminated connected to outer n region is called cathode and that connected to inner p region is called the gate (G). The symbol of SCR is shown in figure. Fig - 1(a) Fig-1(b) Fig-1(c)
  • 5. Fig -1(d) V-I Characteristic A circuit diagram for obtaining static V-I characteristics of a Thyristor is shown in fig. Fig-1(e)
  • 6. Fig-1(f) The anode and cathode are connected to main source through the load. The gate and cathode are fed from a source Vs which gives positive gate current from gate to cathode. Fig. shown static V-I characteristics of Thyristor .Va is the anode voltage across Thyristor terminals A, K and Ia is the anode current. Fig reveals that a Thyristor has three basic modes of operation, namely, reverse blocking mode, forward blocking mode (off-state) and forward conduction mode (on-state) .These three modes of operation are now discussed below. (a). When cathode is made positive with respect to anode with gate open, Thyristor is reverse biased. Junction j1,j3 are reverse biased whereas junction j2 is forward biased . The device behaves like two diodes connected in series with reverse voltage appearing across them. A small leakage current of the order of a few milliampeares or few microamperes flows depending upon the SCR rating. This is reverse blocking mode, called reverse breakdown voltage Vbr , an avalanche occurs at j1 and j3 and the reverse current increases rapidly. A large current associated with Vbb gives rise to more losses in the Thyristor. This may lead to Thyristor damage as the junction temperature may exceed its permissible temperature rise . It should, therefore, be ensured that maximum working reverse voltage across a SCR does not exceed Vbr. (b). Forward blocking mode: When anode is positive with respect to the cathode with gate circuit open, SCR is said to be forward biased. During this mode, junction j1, j3 are forward biased but junction j2 is reversed biased. In this mode, a small current, called forward leakage current, flows. In case the forward voltage is increased, then the reverse biased junction j2 will have an avalanche breakdown at a voltage called forward break over voltage Vbo. When forward voltage is less than Vbo, Thyristor offers high impedance. Therefore, a SCR can be treated as an open switch even in the forward blocking mode. (C). Forward conduction mode: In this mode, SCR conducts currents from anode to cathode with a very small voltage drop across it. A SCR is brought from forward blocking mode to forward conduction mode by turning it on by exceeding the forward break over voltage or by applying a gate4 pulse between gate and cathode. In this mode, SCR is on state and behaves like a closed switch. Voltage drop across Thyristor in the on state is of the order of 1 to 2 volt depending on the rating of Thyristor . This voltage drop increases slightly with UN-Increase in anode current. In conduction mode anode current is limited by load impedance alone as voltage drop across Thyristor quite small. This small voltage drop Vt across the device is due holmic drop in four layers.
  • 7. SPECIFIC TERMINOLOGY:- Break over Current (Ibo) - Principal current at break over point Break over Voltage (Vbo) - Principal voltage at the break over point Gate Trigger current (Igt) - Minimum gate current required to maintain the SCR in the on State. Holding Current (Ih) - Minimum principal current required to maintain SCR in the on state. Latching Current (IL) - Minimum principal current required to maintain SCR in the on state Immediately after the switching from off state to on state has occurred and the triggering Signal has been removed ON- State Voltage (Vt) - Principal voltage when the SCR is in on state Gate trigger Voltage (VGT) - Gate voltage required to produce the gate trigger current ON-State Current (IT) - Principal current when the SCR is in the on state PROCEDURE:- 1) Connection as made as per the circuit diagram. 2) Connect multimeter across the Thyristor (anode- cathode), across the supply terminal Vsto measure gate voltage Vg, Va and Vs (all in DC mode). An ammeter of the mA range is connected to measure the load current IL. 3) Keep initially the gate potential Vg at very low value. Vary the supply voltage Vs in steps and note whether ammeter shows any reading. For every step of Vs note the ammeter. Also note corresponding readings of Va respectively. 4) If ammeter doesn’t indicate any reading, increase the gate potential Vg to some higher value and follow the step no. (3). 5) Further increase the gate potential to some higher values and repeat the procedure followed in step no(3). 6) Tabulate the reading in the observation column. 7).Finally a graph is drawn between anode current (Ia=IL = Load current) and the device voltage Vs respectively.
  • 8. OBSERVATION TABLE:- For Ig1 =……….. = constant. S.n. Anode to Cathode voltage (Vak)volt Anode current (Ia)amp. For Ig2 =……….. = constant. S.No Anode to Cathode voltage (Vak)volt Anode current (Ia)amp.
  • 10. PANAL DIAGRAM- RESULT- Thus the V-I characteristics of SCR and the Break over Voltage, Holding current & Latching current have been determined. QUESTIONS- 1. Define Holding current, Latching current, Breakdown voltage.? 2. What is meant by leakage current.? 3. Mention the applications of SCR?
  • 11. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.2 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 2 AIM:- To study V-I characteristics of Diac with both A.C. & D.C. input voltages. EQUIPMENT REQUIRED:- Setup board, Connecting Wires, Digital Multi meter INTRODUCTION:- It is two terminal three layer semiconductor device as shown in FIG.1 (a). It is a bidirectional diode i.e. it can be made to conduct in either direction. It has no gate terminal. FIG. 1(b) shown circuit symbol. Switching from off state to on state may be done by simply exceeding the avalanche breakdown voltage in either direction. The two p-regions have similar doping characteristics resulting in symmetrical switching characteristics for both positive and negative voltages. Applied voltage of either polarity results in a small saturation. Current across reveres biased pn junction when the applied voltage is exceed the avalanche break down voltage ., The Diac current rises sharply as shown in FIG.2 .In this on condition ,the voltage across the Diac decreases with .Increasing current and the device therefore, offers negative differential resistance. Diac is mainly used a trigger device power control systems. Fig.2(a) Junction diagram of daic Fig.2 (b). Symbol of Diac
  • 12. Fig.2(c) V.I characterstics of Diac Fig.2(d) AC phase control Fig.2(e) Output Waveform HARDWARE SPECIFICATIONS:- 1. Diac characteristics circuit arrangement. 2. Variable D.C. power supply 0 – +35V & 500mA provided on board 3. A.C. source 36 v 50 Hz provide on board. 4. User manual set of patch cord –stackable(4) & non stackable (2)
  • 13. EXPERIMENTAL PROCEDURE:- Switch on the experimental board by connecting the power card to the ac mains. 1. Connect the circuit as shown in fig .2(a) . 2. By vairing the input voltage, not down the reading of out put voltmeter and current meter.(make sure that potentiometer is in minimum position) 3. Draw a graph between voltage v and current i .(it is shown in fig.2(b) 4. Reverse the Diac and connect the input voltage and repeat the steps 2, 3&4. 5. Also observe the waveforms by giving A.C. voltage provided on the board as shown in fig.3 (a) and observe the wave form as shown in fig.3(b) OBSERVATION TABLE:- S.N. VOLTAGE (DIAC) CURRENT(OUT)
  • 15. RESULT:- QUESTION:- 1. What is DIAC & explain with its relative diagram ? 2. Draw the VI characterstics of DIAC?
  • 16. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.3 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 3 AIM :- To study V-I characteristics of BJT EQUIPMENT REQUIRED:- Setup Board, Ammeter,Volt Meter, Connecting cords. THEORY:- Transistors are known as a three terminals semiconductor devices. There are two main types: bipolar junction transistors (BJT) and Field-effect transistors (FET). The BJT is made of either germanium or silicon. Each of these materials is "doped" to give the n-type (in which electrons are the majority carriers) and p-type ( holes are the majority carriers). The BJT device is made as follows: a thin region of n-type material is sandwiched between two regions of p-type material to make a pnp transistor. The same method is used to make a npn transistor. The boundaries between the n and p regions in a BJT are called junctions and the corresponding user terminal names for the npn regions are the Collector, the Base, and the Emitter. BJTs are current controlled devices. In silicon BJT, the forward bias on the base- emitter junction must exceed 0.7 V to activate the device and to allow the majority carriers (current) to flow across the junction with little resistance. In germanium transistors the forward bias must exceed 0.3 V. Fig.3(a) shows the BJT symbol for npn and pnp-type. The second type of the three terminal semiconductor devices is the field-effect transistors FET. Metal-Oxide semiconductor Field-Effect Transistor (MOSFET) is the most popular kind of the field-effect transistors. It is characterized as a voltage controlled device. The source and drain of a MOSFET are formed by diffusing impurities into a substrate of one type (n-type or p-type) to make regions of opposite type. The gate consists of a layer of aluminum evaporated on to a very thin layer of silicon dioxide, which insulates it from the substrate. The main advantages of the MOSFET over the BJT are: easy to manufacture, small size, high input impedance, and less power consumption. MSOFET is considered the basic building cell in most of the VLSI applications, such as, digital logic, memories, microprocessors, microcontrollers, buffer amplifiers, and analog switches. However the BJT maintains its position in the applications that require high power and high frequencies. Fig.3(b) shows the MOSFET symbol for N-channel, and P-channel MOSFET transistors (depletion type).
  • 17. Fig. 3.(a) Fig. 3(b) The DC bias, and circuits configurations are the two main issues that concern the first time circuit designer. The DC bias establishes the static operating point for the device, while the decision of using a certain configuration depends mainly on the type of application for example, a current source or voltage amplifier with high input impedance. In the following sections you will practice a simple approach to establish the operating point of the BJT by looking at the V-I characteristics or maximum rating of the device used in the design. Also you will explore the different types of transistor circuit configurations and amplifier classes. a) DC Bias and Operating Point The DC bias is used to establish a starting point in the V-I characteristic of any active device such as BJTs and MOSFETs. The bias is made possible by using DC power source, and a number of resistive elements. Therefore, the simple electronic circuit will be consisting of the three terminal device surrounded by a resistive circuit and all attached to a single or double DC power supply. The location of the operating point in a BJT ( Q ) depends on the following values CI , CEV , BI , and can be written as fQ  ( CI , CEV , BI ). The temperature variation will cause a change in the DC current gain , and in the collector reverse saturation current COI . Consequently this thermal drift will increment the current CI and change the location of the operating point. If the thermal drift continues, the device could be driven into the saturation region without applying any input signal. A number of biasing schemes have been used in designing BJT circuits to avoid such instability. The self-bias CE with single power supply is shown in fig. 3(b). The resistor ER is used to stabilize the bias by providing a DC negative feedback in the input circuit. Adding a bypass capacitor EC across ER can eliminate the effect of ER at signal frequencies. One quick choice of 1R , and 2R can be achieved using the ratio 1/3 for example if you choose kR 121  , then kR 42  , and all related values can be computed. The operating point location can be chosen the same way for example if you want to locate the Q point at the middle of the V-I characteristics simply choose 2 CC CE V V  , and )(*22 EC CCsaturationC C RR VI I   , obviously these initial choices are subject to change till the desired response of the circuits is obtained. The value of CEV is used to check if the operating point has gone into the saturation or the cut-off region. If 0CEV this, will be an indication that the transistor is operating in the saturation region. If CCCE VV  this, will be an indication that the transistor is operating in the cutoff region. In the MOSFET circuits, biasing technique that stabilize or controls the deviations in the Q point is similar to those used in BJT circuits see figure 3(b). C C B B E E NPN PNP Gate Source Drain D G S N-ChannelP-Channel
  • 18. VDD Vout Vin D S G RG1 RG2 Cs RD Rs Vcc Vout Vin R1 R2 Rc RE CE C E B VCE Fig.3(c) b) Single -Stage Amplifier configurations Three different amplifier circuit configurations can be obtained by selecting one of the transistor terminals as a common between input circuit and output circuit. In the BJT circuits, figure 3(c) shows these configurations, which are known as Common Base (CB), Common Emitter (CE), and Common Collector (CC). These amplifier circuit configurations lead to significant changes in the amplifier characteristics. The most noticeable changes in CC (emitter follower) configurations are: the input resistance becomes very high and the gain is close to the unity. These specific characteristics are translated into a useful application known as buffer amplifier. Therefore amplifier configurations are employed to widen the scope of the amplifier circuit applications. Input Output CB Input Output CC Input Output CE VccVccVcc R R R Fig. 3.(d)
  • 19. c) Transistors As A switch The initial location of the operating point Q within the V-I characteristics of the transistors is chosen according to the type of applications. Some voltage amplifier require that the Q point to be in the middle of the V-I characteristic (active region) so that when a signal applied to the amplifier the Q point would swing evenly with the positive and the negative portions. This type of amplifier application is called class AB amplifier. In another type of amplifier the initial location of the Q point is in the cutoff region. In this case the amplifier will be off when no signal is applied to its input and on when the signal of the right polarity is applied. This type of amplifier is classified as a class B amplifier and one example is push-pull power amplifier. The push-pull amplifier uses the full span of the V-I characteristics to amplify the positive or the negative half of the input signal. Another application requires the Q point to swing between the cutoff and the saturation. This means that the transistor initial Q point is in the cutoff region. A positive input signal will drive the transistor to the saturation region. This extreme swing of the operating point Q is needed in some applications such as switching circuits. Figure 3(d)shows the digital logic inverter using the BJT and the MOSFET operating in Cutoff-Saturation mode. The truth table for both circuits is shown below. Fig. 3(e)V I Characteristics of Bipolar Junction Transister Vout Vout VDD Vin Vin VCC RC RB Input BJT output MOSFET Output 0 or ground Vcc Vdd High or Vin 0 or ground 0 or ground
  • 20. Fig 3.(f) Ohmic regions RESULT:- QUESTIONS :- 1. What is BJT ? 2. Draw the VI characteristics of BJT? 3. What are the advantages of BJT? 4. What are the application of BJT?
  • 21. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.4 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 4 AIM :- To Study the volt ampere characteristics of the TRIC. EQUIPMENT REQUIRED:- Setup Board, Ammeter, Volt Meter,Connecting cords. INTRODUCTION :- In the Thyristor family, after the SCR, the TRIAC is the most widely used device for power control. Fig-a gives the structure of the TRIAC while Fig -b, gives its circuit symbol. In similarity with an SCR, TRIAC is also a four layer semiconductor device with three terminals. Main Terminal 1(MT1) Main Terminal 2(MT2) Gate Terminal G. THEORY:- However unlike SCR, a TRIC is bidirectional device i.e. ,it can block voltages of either polarity and conduct in either direction. A pulse of either polarity can switch A TRIC form OFF state to ON state. Accordingly a TRIC may be considered as to SCR’S connected in parallel but in opposite direction. This becomes obvious from the study of the structure shown Fig 4(a). Gate terminal makes ohmic (non rectifying) contacts with both n and p material, thus permitting either a positive or a negative trigger pulse to causes current flow. Fig-gives volt ampere characteristics of a TRIAC .It may be seen that TRIAC has same ON state and OFF state areas as SCR but this is true for positive and negative applied voltage. Positive bias operation of TRIAC is taken as one when the terminal 2 is positive with respect to terminal 1. This is shown in the first quadrant in Fig2. On the other hand negative bias operation of TRIAC is one in which terminal w is negative with respect to terminal 1 as shown in third quadrant . In similarly with an SCR and TRIAC change state from OFF to ON AT THE breakdown voltage Vbo. Gate triggering may occur in one of the following diodes. Quadrant I operation : V21 positive : Vg1 positive. Quadrant II operation : V21 positive : Vg1 negative. Quadrant III operation : V21 negative : Vg1 negative. Quadrant IV operation : V21 negative : Vg1 positive.
  • 22. Fig. 4(a)V-I characteristics Fig.4 (b) Symbol Fig.4(c) Structure of Triac
  • 23. EXPERIMENTAL PROCEDURE :- 1). Switch on the experimental kit. 2). Connect the circuit diagram as shown in fig-2. 3). Connect ammeter in MT2 ckt. and voltmeter across TRIAC and DMM IN GATE CIRCUIT. 4).Adjust gate current Ig =3.10 Ma WITH dc2 POT and series resistance pot in the gate circuit . 5). Vary DC1 from its minimum and not down the reading of volt meter Vt and current meter It and tabulate these value in the following table. Ig = 3.10 s.no Vt volts It mA Find Vbo from the above table 6). Put Ig = 3.3 mA and again tabulate these values Ig = 3.3 mA S.No. Vt volts It mA 7). Reverse the connection of DC1 volt meter and current meter and repeat the step from 3 to 5. 8). Draw a graph between TRIAC voltage Vt and TRIAC current It at different gate current Ig.
  • 25. RESULT:- QUESTIONS :- 1. Explain the construction of TRIAC ? 2. Draw the V-I characteristics of TRIAC & explain it ? 3. Differentiate between TRIAC & SCR ?
  • 26. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.5 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 5 AIM :- To Study the volt ampere characteristics of the MOSFET. EQUIPMENT REQUIRED :- Setup Board, Ammeter, Volt Meter, Connecting cords. THEORETICAL BACKGROUND :- Metal oxide semiconductor field effect transistor is an important. Semiconductor device and is widely used in many circuit application. The impedance of a MOSFET is much more than that of a FET because a very small gate leakage current. The p-channel MOSFET consist of a lightly doped n-type substrate into which to highly doped p-region are diffused as shown in fig1 this p+ section ,which will act as the sources and drain , are separated by about 5-10 µ. A thin (1000°-2000°A) layer of insulating silicon dioxide (SiO2) is grown over the surface of the structure, and holes are cut in to the oxide layer allowing contact with the source and drain . Than the gate metal area is overlap on the oxide, covering the entire channel region. Simultaneously, metal contacts are made to drain and source, as shown in fig1.the contact to the metal over the channel area is the gate terminal. The chip area of a MOSFET is three square miles or less, which is only about five percent of the reacquired by a bipolar junction transistor. The metal are a of the gate, in conjunction with the insulating dielectric oxide layer and the semiconductor channel, from a parallel plate capacitor. The insulating layer of the silicon dioxide is the reason why this device is the insulator gate field effect transistor. This layer result in an extremely high input resistance 1010Ω - 1015Ω for the MOSFET. The p-channel enhancement MOSFET is the most commonly available filed effect device and its characteristics will now be described. The enhancement MOSFET If we ground the substrate for the structure of fig., apply a negative volt. At the gate , an electric field will be directed perpendicularly through the oxide . the field will end on “induced” positive charges on the semiconductor site a shown in fig1 the positive charge, witch are minority career in the n-type substrate , from an inversion , layer . as the magnitude of the negative volt. All the gate increase, the induced +Ve charge in the semiconductor increases. the region beneath the oxide now has p type career , the conductivity increases and current flow source to drain through the induced channel.Thus the drain current is enhanced by the negative gate volt.and such a device is called an enhancement type MOSFET.
  • 27. Fig.5 (a) n channel depletion type MOSFET Fig.5 (b) p channel depletion type MOSFET THRESHOLD VOLTAGE:- The volt. Ampere drain characteristic of a p channel enhancement mode MOSFET are given in fig.2(a). And its transfer in fig.2(b) the current loss at Vgs>o is very small of Oder few neno-ampere. As Vgs is made negative current (id) increases slowly at first and them much more rapidly with an increases in Vgs . The manufactures often indicate the gate source threshold volt. Vgst or vt at witch id which some defined small values, say 10micro ampere a. current id, on corresponding approximately to the max. Value given on the drain characteristics and the value of Vgs needed to obtain this current area is usually given on the manufacturers, specification. The of vt for the p channel standard or MOSFET is typically 4 volt. . it is common to power supply volt. To typically 5 volt. Used in bipolar integrated circuit, thus various manufacturing technique have been developed to reduce vt. In general.a low threshold volt allow. 1. The use of a small power supply voltage. 2. Compatible operation with bipolar device. 3. Smaller switching time due to the smaller voltage swing during switching and higher packing densities.
  • 28. 4. Three method are use to lower the magnitude of Vt 1. The high threshold MOSFET describe above uses a silicon crystal with (111) orientation. If a crystal utilized in the (100) direction it is found that a value of Vt result which is above one half that obtain with (111) orientation. 2. The silicon nitride approaches makes use of a layer of Si3N4 and SiO2 whose dielectric constant is about twice that of SiO2 along. A fit constructed in this manner decrease Vt to approx – 2V. 3. Polycrystalline silicon doped with boron is used as the gate electrode instead of aluminum. This reduction in the deference in contact potential between the gate electrode and the gate diectric reduces Vt .Such devices are called silicon gate MOSTRANSISTOR. All three of fabrication method described above result in a low threshold MOS has a Vt of approximately 4-6V. POWER SUPPLY REQUIREMENT Table-1 gives the voltage customarily used with high-threshold and low-threshold p-channel MOSFETS. Note that Vss refers to the source. Vdd to the drain and Vgg to the gate supply voltages. The subscript 1 denotes that the source is grounded and the subscript 2 designates that5 the drain is at ground potential. The low-threshold MOS circuits require low power supply voltages and this means less expensive system power supplies. In addition the input voltages, and this means faster operation another very desirable feature of low-threshold MOS circuits is that they are directly compatible with bipolar ICCs. They require and produce essentially the same input and out put signal swing and the system designer has the flexibility of using MOS and bipolar circuit in the same system. Fig. 5(c) Depletion type MOSFET
  • 29. Fig. 5(d) Enhancement type MOSFET ION IMPLANTATION The ion implementation technique demonstrated in fig 3 provides very precise control f doping ions of the proper do pant such as phosphorus or boron accelerated to a high energy of up to 300,000 eV and are use to bombard the silicon wafer target. The energy of ion determines the depth of penetration in to the target.In those area where ions implementation is not desired, an aluminum mask or thick (12000°A) oxide layer absorbs the ion. Virtually any value of Vt can be obtain using ion implementation. In addition, we see form consequently, due to ion implantation; there is a reduction in Cgd and Cgs. THE DEPLETION MOSFET A second type of MOSFET can be made if, to the basic structure of fig1, a channel is defuse between the source and drain , with same type of impurity as used in source to drain diffusion . Let us now conceded such an n-channel structure as shown in fig 4 with this device an appreciable drain current Idss flows for zero gate to source voltage Vgs = o . If the gate voltage –ve , +ve charge are induced in channel through SiO2 of the gate capacitor. Since the current in an FET is due to majority carrier s (Electron for n- type material ), the induced +ve charge make the channel less conductivity and the drain current drop as Vgs is made more –ve .The redistribution of accounts for the designation depletion MOSFET. Note in fug 4b that because of the voltage drop Dew to the drain current, the channel region near the drain is more depleted than is the volume near the sources. This phenomenon is analogs to that of pinch of occurring in a jfet at the drain end of the channel. As a matter of fact, the volt ampere characteristics of the depletion mod MOS and the JFET are to quite smaller. MOSFET GATE PROTECTION Since the SiO2 layer of the gate is extremely thin, it may easily be damaged by excessive voltage. An accumulation of charge on an open circuited gate may result in a large enough field to punch through the dielectric to prevedent this damage some MOS device are fabricated with a ZENER diode between gate and substrate. A normal operation this diode is open and has no effect upon the ckt., however , if the voltage at the gate becomes excessive, than the diode brakes down and the gate potential is limited to a maximum value equal to the ZENER voltage .
  • 30. Fig. 5(e) output charactertics of enhancement type MOSFET CIRCUIT SYMBOLS:- It is possible to bring out the connection to the substrate axtemilly so as to have a TETRODE device. Most of the MOSFET however, are triodes, with the substrate internally connected to the source .fig 6 shows the circuit symbol. Fig. 5(f) Circuit symbol
  • 31. PROCEDURE:- 1). Connect the circuit as shown in fig 7b for enhancement mode. 2). To draw drain characteristic, keep Vgs= o , and vary Vds and note down the values of drain current Id for corresponding Vds values tabulate as per table 3a . 3). Keep Vgs = -1V .repeat the above procedure .draw a graph between Vds and Id at deferent values Of Vgs. 4). To draw the transfer characteristics, keep Vds = 1Vand vary V from 0 -5V and note down the value of drain current Id corresponding value Vgs and tabulate as per table 3b . 5). Repeat the step 5 for various value of Vds . Draw graph between the Vgs and Id at deferent values ofVds. 6). Repeat the step 1-5 for various values of Vds . Draw graph between Vgs and Id at deferent values Of Vgs.
  • 33. RESULT :- QUESTIONS:- 1). What is power MOSFET ? 2). What are the supplication of power MOSFET? 3). Compare MOSFET and BJT ? 4). Explain out put and transfer characteristic of MOSFET?
  • 34. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.6 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 6 AIM :- To Study the output & transfer characteristics of the IGBT . EQUIPMENT REQUIRED :- Setup Board, Ammeter, Volt Meter, Connecting cords. THEORETICAL BACKGROUND :- The insulated gate bipolar transistor combines the positive attributes of BJTs and MOSFETs BJT have lower conduction losses in the on-state especially in devices with larger blocking voltages, but have longer switching times, especially at turn – off while MOSFETs can be turned on off much faster, but their on-state conduction losses are larger, especially in devices rated for higher blocking voltage capabilities in addition to fast switching speeds. IGBTs have vertical structure as shown infig1 .this structure is quite similar to that of the vertical diffused MOSFET except for the presence of the p+ layer that forms the drain of the IGBT. This layer forms a pn junction (labeled j1 in the figure),which injects minority carriers into what would appear to be the drain drift region of the vertical MOSFET. The gate and source of the IGBT are laid out in an inter digitized geometry similar to the used for the vertical MOSFET. CIRCUIT DIAGRAM:- Fig.6(a) Circuit diagram
  • 35. The IGBT structure shown in fig has a parasitic Thyristor which could latch up in IGBT s if it is turned on. Then n+ buffer layer between the p+drain contact and the n+ drift layer, with proper doing density and thickness, can significantly improve the operation of the IGBT, in two important respects .it lower to the on state voltage drop of the device and, shortens the turn off time. On the other hand, the presence of this layer greatly reduces the reverse blocking capability of the IGBT. Fig.6(b) Output characteristics of IGBT Fig.6(c) transfer characteristic
  • 36. EXPERIMENTAL PROCEDURE :- To draw output characteristics of IGBT 1. Connect the circuit as shown in fig.3. 2. To draw out put characteristics keep VGE = 5.6V and slowly increasing Vce and not the point at which the collector current Ic starts to flow increase VCE and not the values of Ic at every step and plot the characteristics between VCE &IC S.NO. VCE IC TO DRAW TRANSFER CHARACTERISTICS OF IGBT 1. Connect the circuit as shown in fig3. 2. Set VCE = 10V. 3. VGE = 0V then IC will be zero .increase VGE and the voltage at which IC start flowing this is the threshold voltage and this points. 4. Increase VGE un steps 0.5v till about 7v .note IC at every step and these points. S.No. vge ic
  • 38. RESULT:- QUESTIONS: 1. What is IGBT? 2. What is the application of IGBT? 3. Compare MOSFET BJT & IGBT? 4. Explain the working principle of IGBT? 5. Explain output & transfer characteristic of IGBT?
  • 39. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.7 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 7 AIM :- To Study the single phase half wave controlled rectifier with R & RL loads and with free wheeling diode. EQUIPMENT REQUIRED:- Single phase half wave rectifier setup board, Patch cords oscilloscope. THEORY:- Line commuted controlled rectifiers from the back bone of static control of electric power in modern industries. although the half wave controlled rectifier configurations, but its study helps in understanding the behavior of full wave configuration. CIRCUIT DIAGRAM: Fig.7(a) single phase half wave controlled rectifier is resistive load Let the Acvoltage fed to controlled rectifier is given by Vs = Vm Sin ωt ………………………………………….(1)
  • 40. Where Vm =peak value of source voltage ω = angular frequency of source voltage, t = time at ωt = 0 , the source voltage Vs starts increasing in positive direction making the anode voltage above its cathode voltage. thus after ωt = 0,SCR is forward biased .under this condition ,if a gate pulse of suitable magnitude is applied the SCR will be triggered into conduction . the SCR fails to block the voltage and almost entire source voltage appears across load . αis the angle in radians at which the gate pulse is applied . this is measured from the moment the SCR has become forward biased. During the period of conduction the load current is given by 𝑖𝑙= 𝑉 𝑚 𝑅 𝑆𝑖𝑛𝜔𝑡 …………………..(2) at ωt = π, the source voltage becomes zero hence the load current is also reduced to zero and SCR turns off. The turn off process is assisted by the reversal of source voltage. Turn off or commutation of SCR is achieved naturally by reversalof source /line voltage is called natural or line commutation. The mean out put voltage cane be evaluated as follows: 𝑉𝑑𝑐 = 𝑉 𝑚 2𝜋 (1 + cos 𝛼)…………(3) Effect of load inductance The natural effect of inductance is to delay the change in current at ωt = α .the load current for resistive load is given by 𝑉 𝑚 𝑅 𝑆𝑖𝑛 𝛼………………………..(4) When the load inductance is present the load current does not build up to his value but increase slowly .at ωt = π,the current rise to fall to zero but the energy stored in the load inductance develops an EMF E= 𝑑𝑖 𝑑𝑡 … … … … … (5) Such that when added to source voltage ,causes the SCR to be forward biased. Thus SCR keeps on conducting beyond ωt = π up to ωt = π+σ at ωt = π+σSCR current reduce zero and SCR turned off . the source remains contend to load from αtoπ +σ. this results in negative voltage appearing across load .the associated wave forms and circuit are shown as follows: Figure. Single phase half wave controlled rectifier with RL load The mean load voltage can now be obtained as: 𝑉𝑑𝑐= 1 2𝜋 𝑉𝑚sin( 𝜔𝑡) 𝑑𝜔𝑡 𝑉𝑑𝑐= 1 2𝜋 𝑉𝑚 (–cos(𝜔𝑡))
  • 41. 𝑉𝑑𝑐= 1 2𝜋 𝑉𝑚 𝑐𝑜𝑠𝛼+𝑐𝑜𝑠𝜎 Thus for the same firing angle α the output voltage Vac for inductive load is less than the same for resistive load. the calculation of is not straight forward ,as it involves the solution of transcendental equation. This equation is given as follows: i = Vm/Z sin(𝜔𝑡 − 𝑓)+ sin ∅𝑒(−𝜔𝑡/ tan ∅) Z = R2 +ω2 L2 ∅ = 𝜔𝐿/𝑅 By substituting I =0, ωt =φ can be obtained. PROCEDURE: for R load 1. connect the setup board as shown in the figure1. 2. Adjust Rt for delay angle of 30. 3. Measure Vs. 4. Measure Vdc with a multimeter. 5. Observe and trace source voltage, SCR current, SCR voltage, load voltage and load current wave forms. 6. Repeat step 2 to 5 for different delay angles record the observation in table. OBSERVATION TABLE:- S.No. Delay Angle Mean output voltage Vdc Remarks Measured Calculated For RL Load 1. Connect the setup as shown in figure 2. 2. Adjust the resistance Rt for a delay angle of 30 degree. 3. Measure Vs. 4. Measure Vdc with a multimeter.
  • 42. 5. Observe and trace source voltage , SCR voltage, SCR current, load voltage &load current wave forms. 6. Repeat steps 2 through 4 for different delay angles. Record the observations in the table. S.No. Delay Angle Mean output voltage Vdc Remarks Measured Calculated PROCEDURE 1.Calculate Vdc for measured vaues of Vm ,and for each of the thee configurations. 2.Comment on wave forms obtained. 3.Sketch the supply primary current for each configurations neglecting the transformer excitation current . 4.Comment on the Vdc obtained for the same angle for each of the three configurations. RESULT
  • 43. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.8 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 8 AIM :- To Study the single phase full wave controlled rectifier with R loads . EQUIPMENT REQUIRED:- Single phase full wave rectifier setup board, patch cords oscilloscope. THEORY:- Once of the types of controlled rectifier is fully controlled and semiconductor rectifier. A fully- controlled circuit contains only thyristers (semiconductor controlled rectifiers (SCR)), whereas a semi- controlled rectifier circuit is made up of both SCR and diodes as shown in Fig.(1). Due to presence of diodes, free-wheeling operation takes place without allowing the bridge output voltage to become negative.. CIRCUIT DIAGRAM: Fig.8(a) Single-phase fully controlled bridge rectifier
  • 44. Fig.8(b) Waveforms of a fully controlled bridge rectifier with resistive load. As shown in Fig. thyristor T1can be fired into the ON state at any time provided that voltage VT1> 0. The firing pulses are delayed by an angle a with respect to the instant where diodes would conduct. Thyristor T1remains in the ON state until the load current tries to go to a negative value. Thyristor T2is fired into the ON state when VT2> 0, which corresponds in Fig. to the condition at which V2> 0. The mean value of the load voltage with resistive load is given by Figure 2 presents the behavior of the fully controlled rectifier with resistive-inductive load (with L→∞). The high-load inductance generates a perfectly filtered current and the rectifier behaves like a current source. With continuous load current, thyristors T1and T2remain in the on-state beyond the positive half- wave of the source voltage Vs. For this reason, the load voltage vdcan have a negative instantaneous value. The firing of thyristors T3and T4has two effects: a. they turn off thyristors T1and T2; and b. After the commutation, they conduct the load current.
  • 45. This is the main reason why this type of converter is called a ‘‘naturally commutated’’ or ‘‘line commutated’’ rectifier. The supply current iShas the square waveform shown in Fig.(2) for continuous conduction. In this case, the average load voltage is given by: PROCEDURE :- 1. Connect the single phase full wave controlled rectifier circuit shown in Fig.8(a) on the power electronic trainer. 2. Turn on the power 3. Plot the input and output waveforms on the same graph paper. 4. Measure the average and RMS output voltage by connect the AVO meter across load resistance. 5. Turn off the power 6. Add the inductive load on the output as shown in Fig.8(b). With L=10mH measure the output voltage and plot the output waveform. 7. Repeat step 6 with L=100mH measure the output voltage and plot the output waveforms. 8. Repeat step 6 & 7 with connect the freewheeling diode across the load. OBSERVATION TABLE: S.No. Delay Angle Mean output voltage Vdc Remarks Measured Calculated
  • 47. DISCUSSION AND CALCULATIONS :- 1. Compare between the practical and theoretical results for input and output voltages and currents. 2. What does parameters of the single phase full wave controlled rectifiers. 3. Give same application of the single phase controlled rectifiers . RESULT:-
  • 48. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.9 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 9 AIM:- Study of 3Φ SCR half controlled converter THEORY:- Phase controlled AC-DC converters employing thyristor are extensively used for changing constant ac input voltage to controlled dc output voltage. In phase-controlled rectifiers, a thyristor is tuned off as AC supply voltage reverse biases it, provided anode current has fallen to level below the holding current. Controlled rectifiers have a wide range of applications, from small rectifiers to large high voltage direct current (HVDC) transmission systems. They are used for electrochemical processes, many kinds of motor drives, traction equipment, controlled power supplies, and many other applications. Three- phase half wave controlled rectifier:- Fig.(1) shows the half-wave rectifier uses three common-cathode thyristor arrangements. In this figure, the power supply and the transformer are assumed ideal. The thyristor will conduct (ON state), when the anode-to-cathode voltage VAKis positive, and a firing current pulse iGis applied to the gate terminal. To controls the load voltage delaying the firing pulse by an angle (α). As shown in Fig. (a), the firing angle α is measured from the crossing point between the phase supply voltages. At that point, the anode-to- cathode thyristor voltage VAKbegins to be positive. CIRCUIT DIGRAM:- Fig.9(a): Three-phase half-wave rectifier
  • 49. With the help of Fig. the load average voltage can be evaluated and is given by Where Vmax is the secondary phase-to-neutral peak voltage, its root mean square (rms) value, and ω is the angular frequency of the main power supply. rmsNfV Fig.9 (b):Instantaneous ds voltaghVD, average dc voltage VD,and firing angle PROCEDURE:- 1. Connect the three-phase half wave controlled rectifier circuit shown in Fig.(1) on the power electronic trainer. 2. Turn on the power. 3. By use oscilloscope, plot the input and output waveforms on the same graph paper" same axis". 4. Measure the average and RMS output voltage by connect the AVO meter across load resistance. 5. Turn off the power 6. Use an inductive load. With L=10mH measure the output voltage and plot the output waveform. 7. Repeat step 6 with L=100mH measure the output voltage and plot the output waveforms. 8. Repeat step 6 & 7 with connect the freewheeling diode across the load. DISCUSSION AND CALCULATIONS : 1. Compare between the practical and theoretical results for input and output voltages and currents. 2. Design a high voltage power supply for CO2laser, when the optical output power is 8watt. The current and voltage electronically highly stabilized DC power unit has a nominal output 50mA and 5kV. Pumping under optimal conditions (maximum laser output), a current of 18mA at 3.0 kV is observed. 3. Design three-phase half wave controlled rectifier.
  • 50. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.10 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 10 AIM:- Study of 3Φ fully controlled converter THEORY:- Phase controlled AC-DC converters employing thyristor are extensively used for changing constant ac input voltage to controlled dc output voltage. In phase-controlled rectifiers, a thyristor is tuned off as AC supply voltage reverse biases it, provided anode current has fallen to level below the holding current. Fig. shows the three-phase bridge rectifier. The configuration does not need any special transformer, and works as a 6-pulse rectifier. The series characteristic of this rectifier produces a dc voltage twice the value of the half-wave rectifier . CIRCUIT DIGRAM:- Fig.10 (a) Three-phase full-wave rectifier The load average voltage is given by:-
  • 51. Fig.10 (b) output wave form PROCEDURE:- 1. Connect the three-phase full wave controlled rectifier circuit shown in Fig.on the power 2. Turn on the power. 3. By use oscilloscope, plot the input and output waveforms on the same graph paper" same axis". 4. Measure the average and RMS output voltage by connect the AVO meter across load resistance. 5. Turn off the power 6. Use an inductive load. With L=100mH measure the output voltage and plot the output waveform. 7. Repeat step 6 with L=100mH measure the output voltage and plot the output waveforms. 8. Repeat step 6 & 7 with connect the freewheeling diode across the load. 9. Connect the three-phase bridge half-control rectifier circuit shown in Fig. 10. Repeat steps (2-7). DISCUSSION AND CALCULATIONS:- 1. Compare between the practical and theoretical results for input and output voltages and currents. 2. Design a high voltage power supply for CO2laser, when the optical output power is 12 watt. 3. The current and voltage electronically highly stabilized DC power unit has a nominal Output 70mA and 6kV. Pumping under optimal conditions (maximum laser output), a current of 20mA at 4 kV is observed. 4. Compare between the three-phase half-wave controlled rectifier and three-phase full-wave controlled rectifier.
  • 52. Jawaharlal Institute of Technology Laboratory Manual (MEPE – 102) Doc. Type – Experiment No.11 Faculty Name: - Subject Name (Code): - Power Electronics Devices & Phase Controlled Circuits Branch: -Electrical & Electronics Year- I Semester:-I EXPERIMENT NO. 11 AIM Study of classes of commutation A, B, C, D ,E, F. EQUIPMENT REQUIRED Setup Board, Oscilloscope, Ammeter, Volt Meter,Connecting cords,30/2A DC Regulated Power Supply. THEORETICAL BACKGROUND Class A, Self commutated by resonating the load When the SCR is triggered, anode current flows and charges up C with the dot as positive. The L-C-R form a second order under-damped circuit. The current through the SCR builds up and completes a half cycle. The inductor current will then attempt to flow through the SCR in the reverse direction and the SCR will be turned off. Fig.11(a) resonant load commutated SCR and the corresponding waveforms. The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into the resistance in an exponential manner. The SCR is reverse-biased till the capacitor voltages returns to the level of the supply voltage V.
  • 53. Class B, Selfcommutated by an L-C circuit:- The Capacitor C charges up in the dot as positive before a gate pulse is applied to the SCR. When SCR is triggered, the resulting current has two components. The constant load current I load flows through R - L load. This is ensured by the large reactance in series with the load and the freewheeling diode clamping it. A sinusoidal current flows through the resonant L-C circuit to charge-up C with the dot as negative at the end of the half cycle. This current will then reverse and flow through the SCR in opposition to the load current for a small fraction of the negative swing till the total current through the SCR becomes zero. The SCR will turn off when the resonant–circuit (reverse) current is just greater than the load current. The SCR is turned off if the SCR remains reversed biased for t q > t off , and the rate of rise of the reapplied voltage < the rated value. Fig.11(b) Class B, L-C turn-off
  • 54. Class C, C or L-C switched by another load–carrying SCR:- This configuration has two SCRs. One of them may be the main SCR and the other auxiliary. Both may be load current carrying main SCRs. The configuration may have four SCRs with the load across the capacitor, with the integral converter supplied from a current source. Assume SCR 2 is conducting. C then charges up in the polarity shown. When SCR 1 is triggered, C is switched across SCR 2 via SCR 1 and the discharge current of C opposes the flow of load current in SCR 2 . Fig.11(c) Class C turn-off, SCR switched off by another load-carring SCR Class D, L-C or C switched by an auxiliary SCR:- The circuit shown in Figure (Class C) can be converted to Class D if the load current is carried by only one of the SCR’s, the other acting as an auxiliary turn-off SCR. The auxiliary SCR would have a resistor in its anode lead of say ten times the load resistance. SCR A must be triggered first in order to charge the upper terminal of the capacitor as positive. As soon as C is charged to the supply voltage, SCR A will turn off. If there is substantial inductance in the input lines, the capacitor may charge to voltages in excess of the supply voltage. This extra voltage would discharge through the diode-inductor-load circuit. When SCR M is triggered the current flows in two paths: Load current flows through the load and the commutating current flows through C- SCR M -L-D network. The charge on C is reversed and held at that level by the diode D. When SCR A is re-triggered, the voltage across C appears across SCR M via SCR A and SCR M is turned off. If the load carries a constant current as in Fig. 3.4, the capacitor again charges linearly to the dot as positive.
  • 55. Fig.11(d) Class D turn-off. Class D commutation by a C (or LC) switched by an Auxiliary SCR. Class E – External pulse source for commutation:- The transformer is designed with sufficient iron and air gap so as not to saturate. It is capable of carrying the load current with a small voltage drop compared with the supply voltage. When SCR1 is triggered, current flows through the load and pulse transformer. To turn SCR 1 off a positive pulse is applied to the cathode of the SCR from an external pulse generator via the pulse transformer. The capacitor C is only charged to about 1 volt and for the duration of the turn-off pulse it can be considered to have zero impedance. Thus the pulse from the transformer reverses the voltage across the SCR, and it supplies the reverse recovery current and holds the voltage negative for the required turn-off time. Fig.11(e) Class E commutation
  • 56. Fig.11(f) wave form of Class E commutation Class F, AC line commutated:- If the supply is an alternating voltage, load current will flow during the positive half cycle. With a highly inductive load, the current may remain continuous for some time till the energy trapped in the load inductance is dissipated. Fig.11 (g) Class F, natural commutation by supply voltage
  • 57. During the negative half cycle, therefore, the SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turn-off period of the device. The duration of the half cycle must be definitely longer than the turn-off time of the SCR. QUESTIONS:- 1. How to turn ON and turn OFF time of switch decide the maximum switching frequency? 2. How the reverse recovery current of free wheeldiodes affects the switch current rating?