Describes characteristics of SCR ,turn on methods,triggering methods of SCR

1. Thyristors
Zahira Tabassum
Associate Professor, Dept of
ECE,HKBKCE
1

2. Objectives
 Study thyristor static and switching
characteristics
 Study and analysis of thyristor circuits with
different triggering conditions
2

3. Outcomes
 Determine the output response of a thyristor
circuit with various triggering options
3

4. Introduction
 Thyristors are one of the most important types of power
semiconductor devices.
 They are operated as bistable switches, operating from
nonconducting state to conducting state.
 Thyristors can be assumed as ideal switches for many
applications. In reality, thyristors exhibit certain
characteristics, and they have some limitations.
 Conventional thyristors are designed without gate-
controlled turn-off capability.
 The thyristor will turn off when the current is brought to
zero.
4

5.  Gate turn-off thyristors (GTO) are designed to have
controlled turn-on and controlled turn-off
capability.
 Thyristors have lower on-state conduction losses
and higher power handling capability compared to
transistors.
 However, transistors have higher switching speeds
and lower switching losses.
5

6. Thyristor Characteristics
 A thyristor is a four-layer semiconductor device
of pnpn structure with three pn junctions.
 The following figure shows the thyristor symbol
and the sectional view of the three pn junctions.
6

7.  When the anode voltage is positive with respect to
cathode, the junctions J1 and J3 are forward-biased.
 However, the junction J2 is reverse-biased.
 Only a small leakage current flows from anode to
cathode.
 Thyristor is in forward blocking or off state.
 If the anode-to-cathode voltage VAK is increased to
a sufficiently large value, the reverse-biased junction
will break.
 This is known as the avalanche breakdown and the
corresponding voltage is called forward breakover
voltage VBO. 7

8.  Since J1 and J3 are already forward biased, there will
be free movement of carriers across all three
junctions, resulting in a large forward anode current.
 The device will be in a conducting state or on-state.
 The voltage drop would be due to the ohmic drop
in four layers and it is small, typically 1V.
 In the on-state, the current is limited by the external
impedance.
 The current must be greater than the latching
current in order for the device to conduct;
otherwise, the device will go into the blocking mode
as the anode-cathode voltage is reduced. 8

9.  If the current is reduced below a value which is known as
the holding current the thyristor will go into the blocking
state.
 The holding current is in the range of milliamperes.
9

10.  When the cathode voltage is positive with respect to the
anode, the junctions J1 and J3 are reversed-biased and J2
is forward-biased.
 This is like two series-connected diodes being reverse-
biased.
 The reverse leakage current is known as the reverse
current IR.
 A thyristor can be turned on by increasing the forward
voltage beyond VBO, but such a turn on can destroy the
thyristor.
10

11.  In practice, the forward voltage is maintained below
VBO and the thyristor is turned on by applying a
positive voltage between its gate and cathode.
 This was shown on the previous figure by dashed
lines.
 Once a thyristor is turned on by a gating signal, the
device continues even if the gate signal is removed.
 Therefore, a thyristor is a latching device.
11

12. Two Transistor Model of
Thyristor
 The latching action can be demonstrated by
using a two-transistor model of thyristor.
12

13.  The collector current IC of a thyristor is related to the
emitter current IE and the leakage current of the
collector-base junction, ICBO.
 The common-base current gain is defined as:
Therefore,
CBOEC III  
E
C
I
I

13

14. 14
I I IC A CBO1 1 1 
I I IC K CBO2 2 2 
)1(221121 CBOKCBOACCA IIIIIII  

15.  But,
 Substituting (2) into (1) and solving for IA:
)2(GAK III 
)(1 21
212




 CBOCBOG
A
III
I
15

16.  The α varies with the emitter current, and the
variation is shown below.
 If , then the denominator will
approach 0 and IA will be infinite.
 Consequently, the thyristor will turn on.
121 
16

17.  Under transient conditions, the capacitances of
the pn junctions will influence the characteristics
of the thyristor.
17

18.  If a thyristor is in a blocking state, a rapidly
rising voltage applied across the device would
cause high current flow through the junction
capacitors.
 If the dv/dt is large, ij2 would be large and this
would result in increased leakage current ICBO1
and ICBO2. The high value of the leakage
currents may cause α1 + α2 to approach unity
and turn the device on.
 This large current through the junction
capacitors may damage the device.
18

19. Thyristor Turn-On
 A thyristor is turned on by increasing the anode current.
 This is accomplished in one of the following ways.
1. Thermals
 If the temperature of a thyristor is high, there will be an
increase in the number of electron-hole pairs.
 This will increase α1 and α2 and the thyristor may be turned
on.
 2. Light
 If light is allowed to strike the junction, the electron-hole
pairs will increase and the thyristor may be turned on.
 The light activated thyristors (LASCR) are turned on by
allowing light to strike the silicon wafer.
19

20. 3. High Voltage
 If the forward anode-to-cathode voltage is greater than
the VBO, the thyristor will turn on.
4. dv/dt
 If the rate-of-rise of the anode-cathode voltage is high,
the charging current of the capacitive junctions will turn
on the thyristor.
5. Gate Current
 If a thyristor is forward biased, the injection of the gate
current by applying a positive gate voltage between the
gate and the cathode terminals would turn on the
thyristor.
20

21. 21

22.  The following points should be considered in
designing the gate control circuit.
 The gate signal should be removed after the
thyristor is turned on. A continuous gating signal
would increase the power loss in the gate junction.
 While the thyristor is reversed biased, there should
be no gate signal; otherwise, the thyristor may fail
due to an increased leakage current.
 The width of gate pulse tG must be longer than the
time required for the anode current to rise to the
holding current value IH. In practice, the pulse
width is made more than the turn-on time ton of
the thyristor.
22

23.  DYNAMIC CHARACTERISTICS OF SCR
TURN ON CHARACTERISTICS:
23

24. Thyristor Turn-Off
 A thyristor which is in the on-state can be turned
off by reducing the forward current to a level
below the holding current.
 The anode current is maintained below the holding
current sufficiently for a long duration such that
excess charge carriers in the four layers are
removed.
 In a line-commutated converter circuit where the
input voltage is alternating, a reverse voltage
appears across the thyristor immediately after the
forward current goes through the zero value.
24

25. 25

26.  The turn-off time tq is the minimum value of time
interval between the instant when the on state
current has decreased to zero and the instant when
the thyristor is capable of withstanding forward
voltage without turning on.
 tq=trr+trc
 trr =reverse recovery time of j1 & j3
 trc= recombination time of j2
26

27. 27
A forced-commutated circuit is shown next.

28. di/dt Protection
 A thyristor requires a minimum time to spread the
current conduction uniformly throughout the
junction.
 If the rate-of-rise of anode current is very fast
compared to the spreading velocity of a turn-on
process, a hot spot will occur.
 As a result of the excessive temperature, the device
may fail.
 Therefore, in practical circuits the device must be
protected against high di/dt.
28

29.  Let us consider the following circuit.
 Dm will conduct when thyristor T1 is off.
 If T1 is fired when Dm is still conducting, di/dt can be
very high.
 In practice, the di/dt is limited by adding a series
inductor Ls.
29
s
s
ss
L
V
dt
di
dt
di
LV 

30. dv/dt Protection
 If the switch S1 is closed at t = 0, a step voltage will be
applied across the thyristor T1.
 The dv/dt may be high enough to turn on the device.
 The dv/dt can be limited by connecting a capacitor Cs
across T1.
 When the thyristor T1 is turned on, the discharge current of
capacitor is limited by resistor Rs. 30

31.  The RC circuit is known as a snubber circuit, and the
voltage across the thyristor will rise exponentially.
 The circuit dv/dt can be found approximately from:
 The snubber circuit can be designed based on the
known value of the dv/dt for a device.
 The value of Rs is found from the discharge current
ITD.
ss
ss
CR
VV
dt
dv 632.0632.0


31
TD
s
s
I
V
R 

32.  The load can form a series circuit with the snubber
network as shown below.
32

33. Gate Triggering Methods
 The different methods of gate triggering are the
following
1. R-triggering.
2. RC triggering.
3. UJT triggering
33

34. Resistance Triggering
 A simple resistance triggering circuit is as shown.
 The resistor R1 limits the current through the gate of the
SCR.
 R2 is the variable resistance added to the circuit to achieve
control over
the triggering angle of SCR.
 Resistor ‘R’ is a stabilizing
resistor.
 The diode D is required
to ensure that no negative
voltage reaches the gate of
the SCR. 34

35. Design:
 With R2= 0 , we need to ensure that Vm/ R1<Igm , where Igm
is the maximum or peak gate current of the SCR.
Therefore R1 = Vm/Igm
 Also with R2= 0 , we need to ensure that the voltage drop
across resistor ‘R’ does not exceed Vgm , the maximum gate
voltage
 Vgm =Vm R/(R1+ R)
Vgm R1 +Vgm R= Vm R
Vgm R1 =R( Vm- Vgm)
R=Vgm R1/( Vm- Vgm)
35

36. Operation
Case 1: Vgp<Vgt Vgp ,
 The peak gate voltage is less then Vgt since R2 is very large.
 Therefore, current ‘I’ flowing through the gate is very small.
 SCR will not turn on and therefore the load voltage is zero and
Vscr is equal to Vs . This is because we are using only a resistive
network. Therefore, output will be in phase with input.
Case 2: Vgp=Vgt ,
R2= optimum value.
 When R2 is set to an optimum value such that Vgp=Vgt , we
see that the SCR is triggered at 900 (since Vgp reaches its peak at
900 only).
 The waveforms shows that the load voltage is zero till 900 and
the voltage across the SCR is the same as input voltage till it is
triggered at 900
36

37.  Case 3: Vgp>Vgt ,
 R2=small value.
 The triggering value Vgt is reached much earlier than 900.
 Hence the SCR turns on earlier than VS reaches its peak
value.
 The waveforms as shown with respect to
Vs =Vm sinwt .
 Therefore at Vgt =Vgp sin
 = sin -1(Vgt/Vgp)
But Vgp =Vm R/(R1+ R2+ R)
37

38. 38

39. RC Triggering-Half wave
39

40. Operation and Design
Case 1:
 When the resistor ‘R’ is large, the time taken for the
capacitance to charge from large, resulting in larger firing
angle and lower load voltage.
Case 2: When ‘R’ is set to a smaller value,
 Capacitor charges at a faster rate towards Vgt resulting in
early triggering of SCR and hence VL is more.
 When the SCR triggers, the voltage drop across it falls to 1
– 1.5V. This in turn lowers, the voltage across R & C.
 Low voltage across the SCR during conduction period
keeps the capacitor discharge during the positive half cycle
40

41.  From the circuit VC =Vgt+Vd1.
 Considering the source voltage and the gate circuit,
we can write Vs= Igt R +VC.
 SCR fires when Vs =Igt R+ VC
i.e Vs = Igt R +Vgt +Vd1.
 Therefore R= Vs -Vgt - Vd1/Igt
 The RC time constant for zero output voltage that
is maximum firing angle for power frequencies is
empirically gives as
RC>1.3 T/2
41

42. RC Full Wave
 A simple circuit giving full wave output is shown in figure below
 In this circuit the initial voltage
from which the capacitor ‘C’
charges is essentially zero.
 The capacitor ‘C’ is reset to this voltage by the clamping action
of the thyristor gate.
 For this reason the charging
time constant RC must be chosen
longer than for half wave RC
circuit in order to delay the
triggering.
42

43.  The RC value is empirically chosen as RC
43

44. UNI JUNCTION TRANSISTOR(UJT)
44

45. Operation
 UJT is an n-type silicon bar in which p-type emitter is embedded. It
has three terminals base1, base2 and emitter ‘E’.
 Between B1 and B2 UJT behaves like ordinary resistor and the
internal resistances are given as RB1and RB 2 with emitter open
 RBB=RB1+ RB2.
 Usually the p-region is heavily doped and n-region is lightly doped.
 When VBB is applied across B1 and B2, we find that potential at A is
VAB1 =VBB RB1 / (RB2+ RB1) =VBB
  =RB1/( RB1+RB 2)
 Where  is intrinsic stand off ratio of UJT and ranges between 0.51
and 0.82.
 Resistor RBB is 5 to 10K .
45

46. UJT Relaxation Oscillator
46
 A synchronized UJT triggering circuit is as shown in figure below.
 The diodes rectify the input ac to dc, resistor Rd lowers Vdc to a
suitable value for the zener diode and UJT.
 The zener diode ‘Z’ functions to clip the rectified voltage to a standard
level VZ which remains constant except near Vdc =0.

47.  This voltage VZ is applied to the charging RC circuit.
 The capacitor ‘C’ charges at a rate determined by the RC time constant.
When the capacitor reaches the peak point VP the UJT starts
conducting and capacitor discharges through the primary of the pulse
transformer.
 As the current through the primary is in the form of a pulse the
secondary windings have pulse voltages at the output.
 The pulses at the two secondaries feed SCRs in phase.
 As the zener voltage VZ goes to zero at the end of each half cycle the
synchronization of the trigger circuit with the supply voltage across the
SCRs is archived, small variations in supply voltage and frequency are
not going to effect the circuit operation.
 In case the resistor ‘R’ is reduced so that the capacitor voltage reaches
UJT threshold voltage twice in each half cycle there will be two pulses in
each half cycle with one pulse becoming redundant.
47

48. Expression for period of oscillation
 Using initial and final value theorem for voltage
across a capacitor, we get VC= VBB(1-e-t/RC)
 @t=T, VC=Vp=  VBB+VD and capacitor charges
from VV,
Therefore VBB+VD= VV+ VBB(1-e-t/RC)
Let VD= VV simplifying
T=RC ln(1/1- )
48

49. Design
 Resistor ‘R’ is limited to a value between 3 kilo ohms and 3 mega ohms.
 If the load line fails to pass to the right of the peak point the UJT will not turn
on, this condition will be satisfied if
VBB =IP R+ VP ,
therefore R=VBB –VP/Ip .
 At the valley point IE =IV and VE=VV, so the condition for the lower limit on
‘R’ to ensure turnoff is
VBB =IV R+ VV ,
therefore R =VBB- VV/IV .
The recommended range of supply voltage is from 10 to 35V.
The width of the triggering pulse tg=RB1C .
RB1 is limited to a value of 100 ohm
and RB2 has a value of 100 ohm or greater and can be approximately determined
as
RB2 =104/VBB . 49

50. THYRISTOR COMMUTATION (Turn Off)
TECHNIQUES
 Thyristors are used as switches to turn on and off power to the
load
 The process of turning off a conducting thyristor is called
commutation.
 The principle involved is that either the anode should be made
negative with respect to cathode (voltage commutation)
 or the anode current should be reduced below the holding current
value (current commutation).
Types of Commutation
 Natural Commutation
 Forced Commutation
50

51. Natural Commutation
 This type of commutation takes place when supply voltage is AC,
because a negative voltage will appear across the SCR in the
negative half cycle of the supply voltage and the SCR turns off by
itself.
 No special circuits are required to turn off the SCR.
 This type of commutation is called Natural or Line Commutation.
51

52. Forced Commutation
 When supply is DC, natural commutation is not possible because the
polarity of the supply remains unchanged.
 Hence special methods must be used to reduce the SCR current below
the holding value or to apply a negative voltage across the SCR for a
time interval greater than the turn off time of the SCR.
 This technique is called FORCED COMMUTATION and is applied in
all circuits where the supply voltage is DC - namely, choppers (fixed DC
to variable DC), inverters (DC to AC).
 Forced commutation techniques are as follows:
Self Commutation
Resonant Pulse Commutation
Complementary Commutation
Impulse Commutation
External Pulse Commutation.
52

53. Self Commutation or Load Commutation or Class A
Commutation:
 In this type of commutation the current through the SCR is
reduced below the holding current value by resonating the load.
 i.e., the load circuit is so designed that even though the supply
voltage is positive, an oscillating current tends to flow and when
the current through the SCR reaches zero, the device turns off.
 This is done by including an inductance and a capacitor in series
with the load and keeping the
circuit under-damped.
53

54. Resonant Pulse Commutation (Class B
Commutation)
54

55. Summary
 Two transistor model of thyristor
 Turn on and turn off characteristics
 Triggering circuits and their comparsion
 Commutation or Turn off of a thyristor.
55
)(1 21
212




 CBOCBOG
A
III
I

56. Problems
 A UJT is used to trigger the thyristor whose minimum gate triggering voltage is
6.2V,The UJT ratings are: =0.66 , I p= 0.5mA , Iv =3mA , RB1+ RB 2= 5k , leakage
current = 3.2mA, Vp=14v and Vv =1V . Oscillator frequency is 2 kHz and capacitor C
= 0.04µ F. Design the complete circuit.
Soln: T= RC ln 1/1-
Here, T =1/2 kHz, since f =2 kHz and putting other values, R=11.6k
The peak voltage is given as, Vp=  VBB+ VD
Let VD =0.8, then putting other values,
14=0.66VBB+ 0.8 Hence VBB=20V
R2 = 0.7(RB1 +RB2)/  VBB Therefore R2=265Ω
VBB =Ileakage (R1 +R2 +RB1 +RB2 )
20=3.2m(R1+265+5K) Therefore R1=985Ω
The value of Rcmax is given by equation
Rcmax =VBB – Vp/I p
Rcmax =20 -14 /0.5 *10-3 Rcmax =12k
Similarly Rcmin =VBB- Vv /Iv
Rcmin=20 -1 /3 10-3 Rcmin= 6.33k
56

57. Topics for Discussion
 Various types of thyristors and their applications
57

58. Activity
 Plot VI characteristics of SCR using Pspice
 Implement RC HWR using Pspice.
 Implement RC FWR using Pspice.
 Implement UJT HWR using Pspice.
58

59. Assignment
1 . Distinguish between i. latching current and holding current. ii. Converter grade
and inverter grade thyristors iii. Thyristor turn off and circuit turn off time iv.
Peak repetitive forward blocking voltage i2 t rating
2. Explain the turn on and turn of dynamic characteristics of thyristor
3. A SCR is to operate in a circuit where the supply voltage is 200 VDC. The
dv/dt should be limited to 100 V/ μs. Series R and C are connected across the
SCR for limiting dv/dt. The maximum discharge current from C into the SCR,
if and when it is turned ON is to be limited to 100 A. using an approximate
expression, obtain the values of R and C.
4. With the circuit diagram and relevant waveforms, discuss the operation of
synchronized UJT firing circuit for a full wave SCR semi converter.
5. Explain gate to cathode equivalent circuit and draw the gate characteristics.
Mark the operating region.
6. Mention the different turn on methods employed for a SCR 10. A SCR is
having a dv/dt rating of 200 V/μs and a di/dt rating of 100 A/μs. This SCR is
used in an inverter circuit operating at 400 VDC and has 1.5Ω source
resistance. Find the values of snubber circuit components.
59

60. 7. With the circuit diagram and relevant waveforms, discuss the operation of
synchronized UJT firing circuit for a full wave SCR semi converter.
8. Explain gate to cathode equivalent circuit and draw the gate characteristics.
Mark the operating region.
9. Mention the different turn on methods employed for a SCR
10. A SCR is having a dv/dt rating of 200 V/μs and a di/dt rating of 100 A/μs.
This SCR is used in an inverter circuit operating at 400 VDC and has 1.5Ω
source resistance. Find the values of snubber circuit components.
11. Explain the following gate triggering circuits with the help of waveforms:
1) R – triggering 2) RC – triggering.
60