Equipment and Materials for 3D TSV Applications - 2017 Report by Yole Develop...Yole Developpement
Driven today mostly by BSI CIS, the 3D TSV equipment & materials business will be supported by 3D stacked memory’s expansion
Technology and application drivers will change over the years, but TSV integration will continue growing
Currently supported mostly by 3D stacked BSI CIS, TSV integration growth will be led mainly by 3D memory applications and new products integrating TSV interconnects in the imaging segment.
Indeed, 3D stacked BSI has been the TSV market’s real driver for a couple of years now. However, with the entrance of 3D hybrid technology (which does not require any TSV interconnects), we expect a decrease of 3D stacked BSI in the TSV market by 2019.
This potential TSV decrease within BSI CIS could be hastened by the 3D single-photon avalanche diodes (SPAD) developed by STMicroelectronics. This is a new approach in time-of-flight that will benefit from 3D hybrid technology by moving the digital pixel into the secondary chip.
While Sony is the current CIS leader and the pioneer of the hybrid stacking method (which was adopted for the first time in the Samsung Galaxy S7 rear camera module), it is too early to fully describe the strategy of other key actors like TSMC/Omnivision and ON Semiconductor, and whether their path will lead to 3D stacked BSI or 3D hybrid stacked.
Another scenario could happen in the next few years and impact the TSV market in a different way. With more complex structures in the BSI CIS field being considered today, some CIS manufacturers might remain on 3D stacked BSI by combining this technology with 3D hybrid stacked for the next generation of products based on multi-stack structure. In this case, 3D hybrid stacked will not compete with 3D stacked BSI, leading to a continuous increase of 3D stacked BSI and 3D hybrid stacked.
For more information please visit our website: http://www.i-micronews.com/reports.html
【Intern Case Study_矽智財】
矽智財 (IP) 是 IC 設計所使用的智慧財產權，是一組事前設計好並驗證完畢、可重複使用的功能組塊，屬於半導體產業的上游，隨著 IC 產業垂直分工化的趨勢而崛起，具有高進入門檻、無庫存、高毛利等特色。
矽智財產業的商業模式為將設計好的 IP 模組授權給買家使用，初次會收取授權金 (License)，往後開始量產則轉為收取權利金 (Royalty)。隨著先進製程不斷演進，全球矽智財市場也高速成長，終端市場以消費性電子為大宗，車用與 AI 應用則為主要成長動能。
矽智財在產業鏈、需求面、供給面、相關個股，還有什麼是我們需要注意的呢？一起來看看 Collaborator 的 Intern 們：梁維珉、黃微茹、蔡博獻、謝恩慈、曾筠婷詳盡分析的矽智財產業報告吧！
#Collaborator
#Intern_CaseStudy
#FX編
【Intern Case Study_矽智財】
矽智財 (IP) 是 IC 設計所使用的智慧財產權，是一組事前設計好並驗證完畢、可重複使用的功能組塊，屬於半導體產業的上游，隨著 IC 產業垂直分工化的趨勢而崛起，具有高進入門檻、無庫存、高毛利等特色。
矽智財產業的商業模式為將設計好的 IP 模組授權給買家使用，初次會收取授權金 (License)，往後開始量產則轉為收取權利金 (Royalty)。隨著先進製程不斷演進，全球矽智財市場也高速成長，終端市場以消費性電子為大宗，車用與 AI 應用則為主要成長動能。
Equipment and Materials for 3D TSV Applications - 2017 Report by Yole Develop...Yole Developpement
Driven today mostly by BSI CIS, the 3D TSV equipment & materials business will be supported by 3D stacked memory’s expansion
Technology and application drivers will change over the years, but TSV integration will continue growing
Currently supported mostly by 3D stacked BSI CIS, TSV integration growth will be led mainly by 3D memory applications and new products integrating TSV interconnects in the imaging segment.
Indeed, 3D stacked BSI has been the TSV market’s real driver for a couple of years now. However, with the entrance of 3D hybrid technology (which does not require any TSV interconnects), we expect a decrease of 3D stacked BSI in the TSV market by 2019.
This potential TSV decrease within BSI CIS could be hastened by the 3D single-photon avalanche diodes (SPAD) developed by STMicroelectronics. This is a new approach in time-of-flight that will benefit from 3D hybrid technology by moving the digital pixel into the secondary chip.
While Sony is the current CIS leader and the pioneer of the hybrid stacking method (which was adopted for the first time in the Samsung Galaxy S7 rear camera module), it is too early to fully describe the strategy of other key actors like TSMC/Omnivision and ON Semiconductor, and whether their path will lead to 3D stacked BSI or 3D hybrid stacked.
Another scenario could happen in the next few years and impact the TSV market in a different way. With more complex structures in the BSI CIS field being considered today, some CIS manufacturers might remain on 3D stacked BSI by combining this technology with 3D hybrid stacked for the next generation of products based on multi-stack structure. In this case, 3D hybrid stacked will not compete with 3D stacked BSI, leading to a continuous increase of 3D stacked BSI and 3D hybrid stacked.
For more information please visit our website: http://www.i-micronews.com/reports.html
【Intern Case Study_矽智財】
矽智財 (IP) 是 IC 設計所使用的智慧財產權，是一組事前設計好並驗證完畢、可重複使用的功能組塊，屬於半導體產業的上游，隨著 IC 產業垂直分工化的趨勢而崛起，具有高進入門檻、無庫存、高毛利等特色。
矽智財產業的商業模式為將設計好的 IP 模組授權給買家使用，初次會收取授權金 (License)，往後開始量產則轉為收取權利金 (Royalty)。隨著先進製程不斷演進，全球矽智財市場也高速成長，終端市場以消費性電子為大宗，車用與 AI 應用則為主要成長動能。
矽智財在產業鏈、需求面、供給面、相關個股，還有什麼是我們需要注意的呢？一起來看看 Collaborator 的 Intern 們：梁維珉、黃微茹、蔡博獻、謝恩慈、曾筠婷詳盡分析的矽智財產業報告吧！
#Collaborator
#Intern_CaseStudy
#FX編
【Intern Case Study_矽智財】
矽智財 (IP) 是 IC 設計所使用的智慧財產權，是一組事前設計好並驗證完畢、可重複使用的功能組塊，屬於半導體產業的上游，隨著 IC 產業垂直分工化的趨勢而崛起，具有高進入門檻、無庫存、高毛利等特色。
矽智財產業的商業模式為將設計好的 IP 模組授權給買家使用，初次會收取授權金 (License)，往後開始量產則轉為收取權利金 (Royalty)。隨著先進製程不斷演進，全球矽智財市場也高速成長，終端市場以消費性電子為大宗，車用與 AI 應用則為主要成長動能。
Comparison of main players AP: Apple A10 with inFO vs. Qualcomm Snapdragon 820 with MCeP packaging technology vs. HiSilicon Kirin 955 & Samsung Exynos 8 with standard Package-on-Package
Five major players are sharing the smartphone application processors (AP) market. Among them, Qualcomm, Apple, Samsung and HiSilicon propose the most powerful AP. They use almost the same technology node for the die, and the innovation is now at the packaging level. During this year, we observed different technologies inside the four main smartphone flagships: classic Package-on-Package (PoP) developed by Amkor for the Kirin 955 and for the Exynos 8, Molded Core Embedded Package (MCeP) technology developed by Shinko for the Snapdragon 820 and integrated Fan-Out packaging (inFO) developed by TSMC for the A10.
Located under the DRAM chip on the main board, the AP are packaged using PoP technology. The Apple A10 can be found in the iPhone 7 series. The HiSilicon Kirin 955 can be found in the Huawei P9 and the Samsung Exynos 8 as the Qualcomm Snapdragon 820 can be found in the Samsung Galaxy S7 series depending on the world version (US and Asia for the Snapdragon and International for the Exynos).
In this report, we highlight the differences and the innovations of the packages chosen by the end-user OEMs. Whereas some AP providers like for HiSilicon or Samsung choose to consider conventional PoP with embedded land-side capacitor (LSC), others like Apple or Qualcomm use innovative technologies like Fan-Out PoP and silicon based Deep Trench LSC or embedded die packaging with advanced PCB substrate. The detailed comparison between the four players will give the pros and the cons of the packaging technologies.
This report also compares the costs of the different approaches and includes a detailed technical comparison between the packaging structure of the Qualcomm Snapdragon 820, the Samsung Exynos 8, the HiSilicon Kirin 955 and the Apple A10.
More information on: http://www.i-micronews.com/reports.html
Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole De...Yole Developpement
Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?
Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology...
How to Make Awesome SlideShares: Tips & TricksSlideShare
Turbocharge your online presence with SlideShare. We provide the best tips and tricks for succeeding on SlideShare. Get ideas for what to upload, tips for designing your deck and more.
1.91 Inch OLED Display Module Resolution 240*536 MIPI Interface for Wearable ...Shawn Lee
This is a 1.91" AMOLED-Display has 240x536 high resolution with a MIPI interface. It`s designed for wearable devices, in addition, it also can be used in other industries, such as handheld pulse Oximeter in the medical industry, smart home products, etc.
The key technology of this AMOLED-Display is LTPS, Real RGB, Thinning.
Whatsapp: 86 18566294218
Skype: panoxshawn@outlook.com
Email: shawn.lee@panoxdisplay.com
OLED/LCD supplier: www.panoxdisplay.com
8. Fab 10 TSMC Headquarters & Fab 2, 3, 5, 8, 12 Fab 6 & 14 TSMC North America WaferTech TSMC Europe TSMC Japan SSMC TSMC China TSMC India TSMC Korea TSMC Worldwide Operations & Affiliates
![[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],半導體產業介紹](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)