Threads in Operating System | Multithreading | Interprocess CommunicationShivam Mitra
1.Interprocess communication ( IPC )
2. Introduction to threads
3. Difference between threads and process
4. Multiprocessing vs multithreading
5. Multithreading challenges
Threads in Operating System | Multithreading | Interprocess CommunicationShivam Mitra
1.Interprocess communication ( IPC )
2. Introduction to threads
3. Difference between threads and process
4. Multiprocessing vs multithreading
5. Multithreading challenges
This Presentation is for Memory Management in Operating System (OS). This Presentation describes the basic need for the Memory Management in our OS and its various Techniques like Swapping, Fragmentation, Paging and Segmentation.
Pipeline processing - In this slide you will come to know the processor works to pass the instructions.
Instructions in multi core processor works parallel. Parallelism is another description of pipeline processing.
This slide is very useful for Computer Architecture students.I have tried to define in most easiest way that a new reader can also understand about the topic
Register Reference Instructions are those instructions that refer the registers to retrieve data from or to deposit data at. Copy the link given below and paste it in new browser window to get more information on Register Reference Instructions:- http://www.transtutors.com/homework-help/computer-science/computer-architecture/register-reference-instructions/
This Presentation is for Memory Management in Operating System (OS). This Presentation describes the basic need for the Memory Management in our OS and its various Techniques like Swapping, Fragmentation, Paging and Segmentation.
Pipeline processing - In this slide you will come to know the processor works to pass the instructions.
Instructions in multi core processor works parallel. Parallelism is another description of pipeline processing.
This slide is very useful for Computer Architecture students.I have tried to define in most easiest way that a new reader can also understand about the topic
Register Reference Instructions are those instructions that refer the registers to retrieve data from or to deposit data at. Copy the link given below and paste it in new browser window to get more information on Register Reference Instructions:- http://www.transtutors.com/homework-help/computer-science/computer-architecture/register-reference-instructions/
Reduced instruction set computing, or RISC (pronounced 'risk', /ɹɪsk/), is a CPU design strategy based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction.
Edhole School provides best Information about Schools in India, Delhi, Noida, Gurgaon. Here you will get about the school, contact, career, etc. Edhole Provides best study material for school students.
Various processor architectures are described in this presentation. It could be useful for people working for h/w selection and processor identification.
digital signal processing
Computer Architectures for signal processing
Harvard Architecture, Pipelining, Multiplier
Accumulator, Special Instructions for DSP, extended
Parallelism,General Purpose DSP Processors,
Implementation of DSP Algorithms for var
ious operations,Special purpose DSP
Hardware,Hardware Digital filters and FFT processors,
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2024.06.01 Introducing a competency framework for languag learning materials ...Sandy Millin
http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
The Roman Empire A Historical Colossus.pdfkaushalkr1407
The Roman Empire, a vast and enduring power, stands as one of history's most remarkable civilizations, leaving an indelible imprint on the world. It emerged from the Roman Republic, transitioning into an imperial powerhouse under the leadership of Augustus Caesar in 27 BCE. This transformation marked the beginning of an era defined by unprecedented territorial expansion, architectural marvels, and profound cultural influence.
The empire's roots lie in the city of Rome, founded, according to legend, by Romulus in 753 BCE. Over centuries, Rome evolved from a small settlement to a formidable republic, characterized by a complex political system with elected officials and checks on power. However, internal strife, class conflicts, and military ambitions paved the way for the end of the Republic. Julius Caesar’s dictatorship and subsequent assassination in 44 BCE created a power vacuum, leading to a civil war. Octavian, later Augustus, emerged victorious, heralding the Roman Empire’s birth.
Under Augustus, the empire experienced the Pax Romana, a 200-year period of relative peace and stability. Augustus reformed the military, established efficient administrative systems, and initiated grand construction projects. The empire's borders expanded, encompassing territories from Britain to Egypt and from Spain to the Euphrates. Roman legions, renowned for their discipline and engineering prowess, secured and maintained these vast territories, building roads, fortifications, and cities that facilitated control and integration.
The Roman Empire’s society was hierarchical, with a rigid class system. At the top were the patricians, wealthy elites who held significant political power. Below them were the plebeians, free citizens with limited political influence, and the vast numbers of slaves who formed the backbone of the economy. The family unit was central, governed by the paterfamilias, the male head who held absolute authority.
Culturally, the Romans were eclectic, absorbing and adapting elements from the civilizations they encountered, particularly the Greeks. Roman art, literature, and philosophy reflected this synthesis, creating a rich cultural tapestry. Latin, the Roman language, became the lingua franca of the Western world, influencing numerous modern languages.
Roman architecture and engineering achievements were monumental. They perfected the arch, vault, and dome, constructing enduring structures like the Colosseum, Pantheon, and aqueducts. These engineering marvels not only showcased Roman ingenuity but also served practical purposes, from public entertainment to water supply.
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It is possible to hide or invisible some fields in odoo. Commonly using “invisible” attribute in the field definition to invisible the fields. This slide will show how to make a field invisible in odoo 17.
Students, digital devices and success - Andreas Schleicher - 27 May 2024..pptxEduSkills OECD
Andreas Schleicher presents at the OECD webinar ‘Digital devices in schools: detrimental distraction or secret to success?’ on 27 May 2024. The presentation was based on findings from PISA 2022 results and the webinar helped launch the PISA in Focus ‘Managing screen time: How to protect and equip students against distraction’ https://www.oecd-ilibrary.org/education/managing-screen-time_7c225af4-en and the OECD Education Policy Perspective ‘Students, digital devices and success’ can be found here - https://oe.cd/il/5yV
Welcome to TechSoup New Member Orientation and Q&A (May 2024).pdfTechSoup
In this webinar you will learn how your organization can access TechSoup's wide variety of product discount and donation programs. From hardware to software, we'll give you a tour of the tools available to help your nonprofit with productivity, collaboration, financial management, donor tracking, security, and more.
2. Major Advances in Computers(1)
• The family concept
—IBM System/360 1964
—DEC PDP-8
—Separates architecture from implementation
• Microporgrammed control unit
—Idea by Wilkes 1951
—Produced by IBM S/360 1964
• Cache memory
—IBM S/360 model 85 1969
3. Major Advances in Computers(2)
• Solid State RAM
—(See memory notes)
• Microprocessors
—Intel 4004 1971
• Pipelining
—Introduces parallelism into fetch execute cycle
• Multiple processors
4. The Next Step - RISC
• Reduced Instruction Set Computer
• Key features
—Large number of general purpose registers
—or use of compiler technology to optimize
register use
—Limited and simple instruction set
—Emphasis on optimising the instruction
pipeline
6. Driving force for CISC
• Software costs far exceed hardware costs
• Increasingly complex high level languages
• Semantic gap
• Leads to:
—Large instruction sets
—More addressing modes
—Hardware implementations of HLL statements
– e.g. CASE (switch) on VAX
7. Intention of CISC
• Ease compiler writing
• Improve execution efficiency
—Complex operations in microcode
• Support more complex HLLs
8. Execution Characteristics
• Operations performed
• Operands used
• Execution sequencing
• Studies have been done based on
programs written in HLLs
• Dynamic studies are measured during the
execution of the program
9. Operations
• Assignments
—Movement of data
• Conditional statements (IF, LOOP)
—Sequence control
• Procedure call-return is very time
consuming
• Some HLL instruction lead to many
machine code operations
10. Weighted Relative Dynamic Frequency of HLL
Operations [PATT82a]
Machine-Instruction Memory-Reference
Weighted Weighted
Dynamic Occurrence
Pascal C Pascal C Pascal C
ASSIGN 45% 38% 13% 13% 14% 15%
LOOP 5% 3% 42% 32% 33% 26%
CALL 15% 12% 31% 33% 44% 45%
IF 29% 43% 11% 21% 7% 13%
GOTO — 3% — — — —
OTHER 6% 1% 3% 1% 2% 1%
11. Operands
• Mainly local scalar variables
• Optimisation should concentrate on
accessing local variables
Pascal C Average
Integer Constant 16% 23% 20%
Scalar Variable 58% 53% 55%
Array/Structure 26% 24% 25%
12. Procedure Calls
• Very time consuming
• Depends on number of parameters passed
• Depends on level of nesting
• Most programs do not do a lot of calls
followed by lots of returns
• Most variables are local
• (c.f. locality of reference)
13. Implications
• Best support is given by optimising most
used and most time consuming features
• Large number of registers
—Operand referencing
• Careful design of pipelines
—Branch prediction etc.
• Simplified (reduced) instruction set
14. Large Register File
• Software solution
—Require compiler to allocate registers
—Allocate based on most used variables in a
given time
—Requires sophisticated program analysis
• Hardware solution
—Have more registers
—Thus more variables will be in registers
15. Registers for Local Variables
• Store local scalar variables in registers
• Reduces memory access
• Every procedure (function) call changes
locality
• Parameters must be passed
• Results must be returned
• Variables from calling programs must be
restored
16. Register Windows
• Only few parameters
• Limited range of depth of call
• Use multiple small sets of registers
• Calls switch to a different set of registers
• Returns switch back to a previously used
set of registers
17. Register Windows cont.
• Three areas within a register set
—Parameter registers
—Local registers
—Temporary registers
—Temporary registers from one set overlap
parameter registers from the next
—This allows parameter passing without moving
data
20. Operation of Circular Buffer
• When a call is made, a current window
pointer is moved to show the currently
active register window
• If all windows are in use, an interrupt is
generated and the oldest window (the one
furthest back in the call nesting) is saved
to memory
• A saved window pointer indicates where
the next saved windows should restore to
21. Global Variables
• Allocated by the compiler to memory
—Inefficient for frequently accessed variables
• Have a set of registers for global variables
22. Registers v Cache
Large Register File Cache
All local scalars Recently-used local scalars
Individual variables Blocks of memory
Compiler-assigned global variables Recently-used global variables
Save/Restore based on procedure nesting depth Save/Restore based on cache replacement algorithm
Register addressing Memory addressing
25. Compiler Based Register Optimization
• Assume small number of registers (16-32)
• Optimizing use is up to compiler
• HLL programs have no explicit references
to registers
—usually - think about C - register int
• Assign symbolic or virtual register to each
candidate variable
• Map (unlimited) symbolic registers to real
registers
• Symbolic registers that do not overlap can
share real registers
• If you run out of real registers some
variables use memory
26. Graph Coloring
• Given a graph of nodes and edges
• Assign a color to each node
• Adjacent nodes have different colors
• Use minimum number of colors
• Nodes are symbolic registers
• Two registers that are live in the same
program fragment are joined by an edge
• Try to color the graph with n colors, where
n is the number of real registers
• Nodes that can not be colored are placed
in memory
28. Why CISC (1)?
• Compiler simplification?
—Disputed…
—Complex machine instructions harder to
exploit
—Optimization more difficult
• Smaller programs?
—Program takes up less memory but…
—Memory is now cheap
—May not occupy less bits, just look shorter in
symbolic form
– More instructions require longer op-codes
– Register references require fewer bits
29. Why CISC (2)?
• Faster programs?
—Bias towards use of simpler instructions
—More complex control unit
—Microprogram control store larger
—thus simple instructions take longer to execute
• It is far from clear that CISC is the
appropriate solution
30. RISC Characteristics
• One instruction per cycle
• Register to register operations
• Few, simple addressing modes
• Few, simple instruction formats
• Hardwired design (no microcode)
• Fixed instruction format
• More compile time/effort
31. RISC v CISC
• Not clear cut
• Many designs borrow from both
philosophies
• e.g. PowerPC and Pentium II
32. RISC Pipelining
• Most instructions are register to register
• Two phases of execution
—I: Instruction fetch
—E: Execute
– ALU operation with register input and output
• For load and store
—I: Instruction fetch
—E: Execute
– Calculate memory address
—D: Memory
– Register to memory or memory to register operation
34. Optimization of Pipelining
• Delayed branch
— Does not take effect until after execution of following
instruction
— This following instruction is the delay slot
• Delayed Load
— Register to be target is locked by processor
— Continue execution of instruction stream until register
required
— Idle until load complete
— Re-arranging instructions can allow useful work whilst
loading
• Loop Unrolling
— Replicate body of loop a number of times
— Iterate loop fewer times
— Reduces loop overhead
— Increases instruction parallelism
— Improved register, data cache or TLB locality
35. Loop Unrolling Twice
Example
do i=2, n-1
a[i] = a[i] + a[i-1] * a[i+l]
end do
Becomes
do i=2, n-2, 2
a[i] = a[i] + a[i-1] * a[i+i]
a[i+l] = a[i+l] + a[i] * a[i+2]
end do
if (mod(n-2,2) = i) then
a[n-1] = a[n-1] + a[n-2] * a[n]
end if
36. Normal and Delayed Branch
Address Normal Branch Delayed Branch Optimized
Delayed Branch
100 LOAD X, rA LOAD X, rA LOAD X, rA
101 ADD 1, rA ADD 1, rA JUMP 105
102 JUMP 105 JUMP 106 ADD 1, rA
103 ADD rA, rB NOOP ADD rA, rB
104 SUB rC, rB ADD rA, rB SUB rC, rB
105 STORE rA, Z SUB rC, rB STORE rA, Z
106 STORE rA, Z
38. Controversy
• Quantitative
—compare program sizes and execution speeds
• Qualitative
—examine issues of high level language support
and use of VLSI real estate
• Problems
—No pair of RISC and CISC that are directly
comparable
—No definitive set of test programs
—Difficult to separate hardware effects from
complier effects
—Most comparisons done on “toy” rather than
production machines
—Most commercial devices are a mixture