Microprocessor 8085

1. MICROPROCESSOR 8086
LECTURE 31
8086 INTRODUCTION & PIN DIAGRAM
PROF. SANDIP DAS

2. INTRODUCTION
• 8086 is a 16 bit microprocessor
• It uses 20 address lines and 16 data lines
• The 20 address lines are time multiplexed lines out of which 16
lower order address lines are time multiplexed with data and 4
higher order address lines are time multiplexed with status
signals.

3. PIN DIAGRAM
AD0-AD15: (Bidirectional) Low order
address bus. They are multiplexed with
data.
A16-A19: (Output) Higher order address
lines. These are multiplexed with status
signals.
A16/S3, A17/S4: A16 and A17 are
multiplexed with segment identifier
signals S3 and S4.
A18/S5: A18 is multiplexed with interrupt
status S5
A19/S6: A19 is multiplexed with status
signal S6.
𝐵𝐻𝐸/𝑆7: (Output) Bus High Enable/Status.
During T1 it is low. It is used to enable
data onto the most significant half of data
bus, D8-D15. 8 bit device connected to

4. OPERATING MODES
There are two modes:
Minimum Mode and Maximum Mode
• When only one 8086 is to be used it is used in the minimum
mode of operation. In this mode the microprocessor issues the
control signals required by memory and I/O devices.
• In case of Maximum mode of operation control signals are
issued by 8288 bus controller for this purpose.
When 𝑀𝑁/𝑀𝑋 is high the microprocessor operates in the
minimum mode. When it is low the microprocessor operates in
the maximum mode.

5. PIN DESCRIPTION FROM MINIMUM MODE
For the minimum mode of operation the pin 𝑀𝑁/𝑀𝑋 is connected to 5V d.c. supply.
The description of the pins 24 to 31 for the minimum mode is as follows:
𝐼𝑁𝑇𝐴: (Output) Interrupt acknowledge.
ALE: (Output) Address Latch Enable. It goes HIGH during T1 and microprocessor send
the signal to latch the address.
𝐷𝐸𝑁: (Output) Data Enable. When octal bus transceiver is used this signal acts as an
output enable signal.
𝐷𝑇/ 𝑅: (Output) Data Transmit/Receiver. When Octal bus transceiver is used this signal
controls the direction of flow through the transceiver. When it is HIGH data are sent
out. When it is LOW data are received.
M/𝐼𝑂: (Output) When it is HIGH microprocessor wants to access memory. When it is
LOW microprocessor wants to access I/O device.
𝑊𝑅: (Output) Write. When it is LOW the microprocessor performs memory or I/O write
operation.
HLDA: (Output) HOLD Acknowledge.

6. PIN DESCRIPTION OF MAXIMUM MODE
For the minimum mode of operation the pin 𝑀𝑁/𝑀𝑋 is grounded.
The description of the pins 24 to 31 for the minimum mode is as
follows:
QS1, QS0: (Output) Instruction Queue Status. Logics are given
below.
QS1 QS0 OPERATION
0 0 No Operation
0 1 1st byte of opcode
from Queue
1 0 Empty the Queue
1 1 Subsequent byte from
queue

7. PIN DESCRIPTION OF MAXIMUM MODE
𝑆0, 𝑆1, 𝑆2: (Output) These signals are connected to the bus
controller. The bus controller generates memory and I/O access
control signals.𝑆2 𝑆1 𝑆0 Operation
0 0 0 Interrupt Acknowledge
0 0 1 Read data from I/O
0 1 0 Write data into I/O
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory Read
1 1 0 Memory write
1 1 1 Passive State

8. 𝐿𝑂𝐶𝐾: (Output) When it is LOW all interrupts are masked and no
HOLD request is granted.
𝑅𝑄/𝐺𝑇1, 𝑅𝑄/𝐺𝑇0: (Output) Local Bus Priority Control. Other
processors ask the microprocessor through these lines to release
the local bus.
PIN DESCRIPTION OF MAXIMUM MODE