Pin description of 8086

1. Pin Description of 8086

2. Pin Diagram

3. Pins and Signals
• AD15- AD0 ( Input /Output)
ADDRESS /DATA BUS: These lines constitute the time
multiplexed memory/IO address and data bus.
During T1 clock cycle of the bus cycle, they carry lower
order 16-bit address.
During T2, T3 and T4, they carry 16-bit data.
• A16/S3-- A19/S6 (Output):
Address/status lines are used as address lines during
the first T state of a machine cycle.
& acts as status lines later to indicate which register is
used for accessing data as given next..

4. Pins and Signals
• A16/S3 -- A19/S6 (Output):
• S5 is a Interrupt enable status signal & S6 -0.
S4 S3 Segment
Register
0 0 ES
0 1 SS
1 0 CS
1 1 DS

5. Pins and Signals
• BHE / S7 (Output):
Bus High Enable / Status is used to enable data
onto most significant half of the data bus.
This signal with A0 also signifies the byte which is
read from even address or odd address.
S7 is used in Interrupt acknowledge cycle.
BHE A0 Word/Byte Access
0 0 Whole word from even address
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even
address
1 1 None

6. Pins and Signals
• RD (Output)
This indicates that the processor is performing a
memory or I/O read cycle.
• READY (Input)
Ready signal is the acknowledgement from the
slower I/O device or memory. When high, it indicates
that the peripheral device is ready to transfer data.
• RESET (Input)
This causes the processor to immediately terminate
its present activity.
When this goes High, processor enters into reset
state and start execution from FFFF0H. The signal must
be active HIGH for at least four clock cycles.

7. Pins and Signals
• INTR (Input)
INTERRUPT REQUEST is a level triggered input which is
sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt
acknowledge operation.
A subroutine is vectored to via an interrupt vector
lookup table located in system memory.
It can be internally masked by software resetting the
interrupt enable bit.
INTR is internally synchronized. This signal is active
HIGH.
• TEST (Input)
This signal is used to test the status of math co-processor
8087. The BUSY pin of 8087 is connected to this. This input is
examined by the WAIT instruction. If this is low, execution
continues otherwise processor waits in idle state.

8. Pins and Signals
• NMI (Input)
NON-MASKABLE INTERRUPT is an edge triggered input
which causes an interrupt request to the MP. A subroutine is
vectored to via an interrupt vector lookup table located in
system memory. NMI is not maskable internally by software.
• MN/MX (Input)
MINIMUM/MAXIMUM indicates the operating mode of
the processor.
If high, processor is in minimum mode & if low, it is in
maximum mode.
• CLK (Input)
Provides basic timing for the processor & bus controller.
It is a symmetric square wave with 33% duty cycle. The range
of frequency is 5 MHz to 10MHz.
• VCC : +5V power supply pin
• GND : Ground.

9. Minimum Mode
The following pin
descriptions are
for 8086 in
minimum mode
(MN /MX = VCC.)
MN/MX =1
Active
Signals

10. Minimum Mode
• HOLD (Input)
HOLD pin is used by external devices to gain
control of the buses.
• HLDA (Output)
When the HOLD signal is activated by an
external device, the 8086 stops executing
instructions and stops using the buses.
This would allow external devices to control
the information on the buses.

11. Minimum Mode
• M/IO (Output)
Differentiates between the Memory and I/O
operation.
A LOW on this pin indicates I/O operation
and a HIGH indicates a Memory Operation
• WR ( Output)
Indicates that the processor is performing a
write memory or write I/O operation.

12. Minimum Mode
• INTA (Output)
Interrupt Acknowledge is an active low signal.
When mp receives INTR signal, interrupt
acknowledge given by the microprocessor.
• ALE (Output)
Address Latch Enable- A HIGH on this line
during T1 causes the lower order 16bit address bus
to be latched that stores the addresses and then
later , the lower order 16bit of the address bus can
be used as data bus.
This pin is connected to latch enable pin of
latches 8282 or 74LS373.

13. Minimum Mode
• DT/R (Output)
Data Transmit / Receive. It is used to control
the direction of data flow through the transceiver
8286 or 74LS245.
When the processor sends the data out, this
signal is high and when this signal is low the data is
received.
• DEN (Output)
Data Enable is Output enable for the data
transceiver in the minimum mode.
This is an active low signal during the middle of
T2 until the middle of T4 to indicate the availability
of valid data over AD0 – AD15.

14. Maximum Mode
The following pin
descriptions are
for 8086 in
maximum mode
(MN /MX = GND.)
MN/MX =0
Active
Signals

15. Maximum Mode
• S2, S1, S0 (Output)
Status is used by
8288 bus controller
to generate all
memory & I/O
access control
signals.
S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read Memory
1 1 0 Write memory
1 1 1 Passive

16. Maximum Mode
• RQ/GT0, RQ/GT1 (Input/ Output)
These pins are used by other local bus
masters to force the processor to release the
local bus at the end of the current operation.
• LOCK (Output)
This indicates that the other system bus
masters are not to gain control of the system
bus while LOCK is active LOW. It is activated by
LOCK prefix instruction.

17. Maximum Mode
• QS1, QS0 (Output)
Queue Status provides status to allow
external tracking of the internal 8086
instruction queue.
QS1 QS0 Status
0 0 No operation
0 1 1st byte of op-code from queue
1 0 Empty queue
1 1 Subsequent byte from queue