EE6008 MICROCONTROLLER BASED
SYSTEM DESIGN
MR.G.SIVAKUMAR AP/ECE
RAMCO INSTITUTE OF TECHNOLOGY
RAJAPALAYAM.
Introduction to PIC
Microcontroller
Introduction to PIC Microcontroller
• Introduction to PIC Microcontroller
• PIC 16C6x Architecture
• PIC16C7x Architecture
• PIC16Cxx–Pipelining
• Program Memory considerations
• Register File Structure
• Addressing modes
• Instruction Set
• Simple Operations
Why PIC has become popular ???
• Low cost
• Wide availability
• Large user base
• Easy of availability of its supporting hardware
and software tools like assemblers, debuggers
and simulators
• Re-programming with flash memory capability
• Easy to interface with other peripherals
PIC - Introduction
PIC- Peripheral Interface Controller
• Harvard architecture
• RISC Architecture
• Low end Architecture and Mid-range
Architecture
• Speed (20 Mhz) (0.2 microseconds)
• Watch dog timer
• Brown-out protection
PIC - Introduction
• Power on Reset
• ROM/OTP/EPROM/ROM/Flash
• 8 level stack
• Powerful output pin control
• Up to 12 independent interrupt sources
• Direct and Indirect addressing modes
• Timers
• Serial Programming
PIC 16C6x Architecture
• High performance RISC CPU
• 8 bit microcontroller
• Low cost, High performance, CMOS, fully static
microcontroller
• Only 35 single word instructions
• Interrupt capability
• Eight level deep hardware stack
• Direct and Indirect addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
PIC 16C6x Architecture
• Watchdog Timer (WDT)
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM/ROM
technology
• Fully static design
• Wide operating voltage range: 2.5V to 6.0V
• Commercial, Industrial, and Extended
temperature ranges
• Low-power consumption
PIC 16C6x Peripheral Features
• Three timers: Timer0, Timer1, Timer2
– Timer0 : 8-bit timer/counter with 8-bit prescaler
– Timer1 : 16-bit timer/counter with prescaler, can
be incremented during sleep via external
crystal/clock
– Timer2 : 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture/Compare/PWM (CCP) module(s)
– Capture is 16-bit, max resolution is 12.5 ns
– Compare is 16-bit, max resolution is 200 ns
– PWM max resolution is 10-bit
PIC 16C6x Peripheral Features
• Synchronous Serial Port (SSP) with SPI and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
• Brown-out detection circuitry for Brown-out
Reset (BOR)
Harvard Architecture and Pipelining
PIC 16C6x/7x family of microcontrollers use
Hardware architecture to achieve an fast
execution speed for a given clock.
BLOCK Diagram of PIC16C67
Block diagram of PIC 16C77 Microcontroller
PIC Registers
• W - Reg
• Status Register
• FSR – File Select Register
• INDF
• Program Counter
• PCL
• PCLATCH
• Eight Level Stack
PIC Registers
• Working Register:(W - Register)
– Working Register is a 8-bit register used by many
instructions as the source of an operand.
– It also serves as the destination for the result of
instruction execution and it is similar to
accumulator in other Microcontrollers and
Microprocessors.
– It is a 8-bit regarding.
ADDWF f, d
PIC Registers
• Status Register:
– It contains the arithmetic status of the ALU, the
RESET status and the bank select bits for the data
memory.
PIC Registers
• Status Register:
– C: Carry/borrow bit
– DC: Digit carry/borrow bit
– Z: Zero bit
– NOT_PD: Reset Status bit (Power-down mode bit)
– NOT_TO: Reset Status bit (tme- out bit)
– RPO: Register bank Select
– The bits 7 and 6 of Status Register are unused by
16c6x/7x.
PIC Registers
• The ‘C’ bit is set when two 8-bit operands are added
together and a 9-bit result occurs. This 9-bit is placed in
the carry bit.
• The DC or Digit carry bit indicates that a carry from the
lower 4 bits occurred during an 8-bit addition.
Example:
0011 1000
0011 1000
----------------
0111 0000
---------------
Here DC=1 as a result of the carry from the bit 3 to the
bit 4 position.
PIC Registers
• The Z or zero bits is affected by the execution
of arithmetic or logic instructions.
• The reset status bits NOT_TO and NOT_PD are
used in conjunction with PIC’s sleep mode.
The micro controller can put itself to sleep
mode to save power during intervals when it
has nothing to do. Upon reset the CPU can
check these two reset status bits to determine
which kind of event resettled it and then
respond accordingly.
PIC Registers
• The Register bank select bit RPO is used to
select either bank .
When RPO=0, select Bank 0,
RPO=1, select Bank 1.
• Example:
bcf STATUS, RPO //Select bank 0
bsf STATUS, RPO //Select bank 1.
PIC Registers
• FSR – (File Select Register):
– It is the pointer used for indirect addressing.
– In the indirect addressing mode the 8-bit register
file address is first written into FSR.
– It is a special purpose register that serves as an
address pointer to any address through out the
entire register file.
• INDF – (Indirect File):
– It is not a physical register addressing, this INDF
will cause indirect addressing.
– Any instruction using the INDF register actually
access the register pointed to by the FSR.
PIC Registers
• PCL:
– PCL is actually the lower 8-bits of the 13-bit program
counter.
– It can be read like any other register.
• PCLATH (Program Counter Latch):
– Upper bits of are not readable but are indirectly
writable .
– The upper 3-bits of PCLATH remains zero and serves no
purpose.
Progarm Counter :
Watch Dog Timer (WDT):
A Watch dog timer is a simple timer circuit
that performs a specific operation after a certain
period of time if something goes wrong.
Pipelining
• Overlapped movement of instruction to the processor is
called pipelining.
Pipelining
Program Memory Considerations
Program memory access for PIC parts having 2K of
program memory.
• PIC family uses 13-bit program counter allowing the
controllers to an 8k- program memory without changing the
CPU structure.
Program Memory Considerations
Program memory access for PIC parts having 4K of
program memory.
Program memory and Stack memory
Two addresses in the program memory address space are treated
in a special way by the CPU.
• When the CPU starts up from its reset state, its program
counter is automatically cleared to zero. with the content of
address H'000’being a go to Mainline instruction.
• The second special address H'004', is automatically loaded
into the program counter when an interrupt occurs.
Program Memory
Addressing Used by Subroutine calls :
Data Memory
The data memory of PIC 16F8XX is partitioned into multiple
banks which contain
• General purpose registers
• Special function Registers.(SFRs).
The bits RP1 and RP0 bits of the status register are used
to select these banks
Data Memory Considerations
PIC 16C63
PIC 16C65 A
PIC 16C73 A
PIC 16 C74 A
General Purpose
Register
BANK 0 BANK 1
Addressing Mode
Direct Addressing Mode
ADDWF FSR,0
Indirect Addressing Mode
ADDWF INDF
INSTRUCTION SET OF PIC
INSTRUCTION SET OF PIC
• Instruction set of PIC are divided into three
basic categories,
• Byte Oriented Instruction
• Bit Oriented Instruction
• Literal and Control Instruction
Byte Oriented Instruction (18 inst)
f: File Register (or RAM)
d: Destination
d=0: Destination  W
d=1: Destination  File
Register
Bit Oriented Instruction (4 Inst)
• f: Register File where the Bit is located
• b: Bit Field
Literal and Control Instruction (13 Inst)
• K: 8-bit constant
Classification of Instruction
• Instruction set of PIC are classified into
• Arithmetic Instruction
• Logical Instruction
• Increment/Decrement Instruction
• Data Transfer Instruction
• Clear Instruction
• Rotate Instruction
• Branch Instruction
• Miscellaneous Instructions
Arithmetic Instruction
 ADDWF
 ADDLW
 SUBWF
 SUBLW
ADDWF
ADDWF
ADDLW
ADDLW
SUBWF
SUBWF
SUBLW
SUBLW
Logical Instruction
 ANDWF
 ANDLW
 IORWF
 IORLW
 XORWF
 XORLW
 COMF
ANDWF
ANDWF
ANDLW
ANDLW
IORWF
IORWF
IORLW
IORLW
XORWF
XORWF
XORLW
XORLW
COMF
COMF
Increment/ Decrement Instruction
 INCF
 DECF
INCF
INCF
DECF
DECF
Data Transfer Instruction
 MOVF
 MOVWF
 MOVLW
MOVF
MOVF
MOVWF
MOVWF
MOVLW
MOVLW
Clear Instruction
 CLRF
 CLR W
 BCF
 BSF
CLRF
CLRF
CLR W
CLR W
BCF
BCF
BSF
BSF
Rotate Instruction
 RLF
 RRF
 SWAPF
RLF
RLF
RRF
RRF
SWAPF
SWAPF
Branch Instruction
 Branch Instructions are classified into
 Conditional Branch
 Unconditional Branch
Conditional Instruction
 BTFSC
 BTFSS
 DECFSZ
 INCFSZ
BTFSC
BTFSC
BTFSS
BTFSS
DECFSZ
DECFSZ
INCFSZ
INCFSZ
Unconditional Instruction
 CALL
 GOTO
 RETURN
 REETLW
 RETFIE
CALL
CALL
GOTO
RETURN
RETLW
REETLW
RETFIE
Miscellaneous Instruction
 SLEEP
 CLRWDT
 NOP
SLEEP
• Stop clock
• Reduce Power
• Wait for watchdog timer or external signal
CLRWDT
• If watchdog timer is enabled, this instruction
will reset it (before it resets the CPU)
NOP
NOP
Reference :
• Peatman,J.B., “Design with PIC Micro
Controllers”PearsonEducation,3rdEdition, 2004.
• Mazidi, M.A.,“PIC Microcontroller” Rollin Mckinlay,
Danny causey Printice Hall of India, 2007.

Introduction to pic microcontroller

  • 1.
    EE6008 MICROCONTROLLER BASED SYSTEMDESIGN MR.G.SIVAKUMAR AP/ECE RAMCO INSTITUTE OF TECHNOLOGY RAJAPALAYAM.
  • 2.
  • 3.
    Introduction to PICMicrocontroller • Introduction to PIC Microcontroller • PIC 16C6x Architecture • PIC16C7x Architecture • PIC16Cxx–Pipelining • Program Memory considerations • Register File Structure • Addressing modes • Instruction Set • Simple Operations
  • 4.
    Why PIC hasbecome popular ??? • Low cost • Wide availability • Large user base • Easy of availability of its supporting hardware and software tools like assemblers, debuggers and simulators • Re-programming with flash memory capability • Easy to interface with other peripherals
  • 5.
    PIC - Introduction PIC-Peripheral Interface Controller • Harvard architecture • RISC Architecture • Low end Architecture and Mid-range Architecture • Speed (20 Mhz) (0.2 microseconds) • Watch dog timer • Brown-out protection
  • 6.
    PIC - Introduction •Power on Reset • ROM/OTP/EPROM/ROM/Flash • 8 level stack • Powerful output pin control • Up to 12 independent interrupt sources • Direct and Indirect addressing modes • Timers • Serial Programming
  • 8.
    PIC 16C6x Architecture •High performance RISC CPU • 8 bit microcontroller • Low cost, High performance, CMOS, fully static microcontroller • Only 35 single word instructions • Interrupt capability • Eight level deep hardware stack • Direct and Indirect addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST)
  • 9.
    PIC 16C6x Architecture •Watchdog Timer (WDT) • Programmable code-protection • Power saving SLEEP mode • Selectable oscillator options • Low-power, high-speed CMOS EPROM/ROM technology • Fully static design • Wide operating voltage range: 2.5V to 6.0V • Commercial, Industrial, and Extended temperature ranges • Low-power consumption
  • 10.
    PIC 16C6x PeripheralFeatures • Three timers: Timer0, Timer1, Timer2 – Timer0 : 8-bit timer/counter with 8-bit prescaler – Timer1 : 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock – Timer2 : 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture/Compare/PWM (CCP) module(s) – Capture is 16-bit, max resolution is 12.5 ns – Compare is 16-bit, max resolution is 200 ns – PWM max resolution is 10-bit
  • 11.
    PIC 16C6x PeripheralFeatures • Synchronous Serial Port (SSP) with SPI and I2C • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls • Brown-out detection circuitry for Brown-out Reset (BOR)
  • 12.
    Harvard Architecture andPipelining PIC 16C6x/7x family of microcontrollers use Hardware architecture to achieve an fast execution speed for a given clock.
  • 13.
  • 14.
    Block diagram ofPIC 16C77 Microcontroller
  • 15.
    PIC Registers • W- Reg • Status Register • FSR – File Select Register • INDF • Program Counter • PCL • PCLATCH • Eight Level Stack
  • 16.
    PIC Registers • WorkingRegister:(W - Register) – Working Register is a 8-bit register used by many instructions as the source of an operand. – It also serves as the destination for the result of instruction execution and it is similar to accumulator in other Microcontrollers and Microprocessors. – It is a 8-bit regarding. ADDWF f, d
  • 17.
    PIC Registers • StatusRegister: – It contains the arithmetic status of the ALU, the RESET status and the bank select bits for the data memory.
  • 18.
    PIC Registers • StatusRegister: – C: Carry/borrow bit – DC: Digit carry/borrow bit – Z: Zero bit – NOT_PD: Reset Status bit (Power-down mode bit) – NOT_TO: Reset Status bit (tme- out bit) – RPO: Register bank Select – The bits 7 and 6 of Status Register are unused by 16c6x/7x.
  • 19.
    PIC Registers • The‘C’ bit is set when two 8-bit operands are added together and a 9-bit result occurs. This 9-bit is placed in the carry bit. • The DC or Digit carry bit indicates that a carry from the lower 4 bits occurred during an 8-bit addition. Example: 0011 1000 0011 1000 ---------------- 0111 0000 --------------- Here DC=1 as a result of the carry from the bit 3 to the bit 4 position.
  • 20.
    PIC Registers • TheZ or zero bits is affected by the execution of arithmetic or logic instructions. • The reset status bits NOT_TO and NOT_PD are used in conjunction with PIC’s sleep mode. The micro controller can put itself to sleep mode to save power during intervals when it has nothing to do. Upon reset the CPU can check these two reset status bits to determine which kind of event resettled it and then respond accordingly.
  • 21.
    PIC Registers • TheRegister bank select bit RPO is used to select either bank . When RPO=0, select Bank 0, RPO=1, select Bank 1. • Example: bcf STATUS, RPO //Select bank 0 bsf STATUS, RPO //Select bank 1.
  • 22.
    PIC Registers • FSR– (File Select Register): – It is the pointer used for indirect addressing. – In the indirect addressing mode the 8-bit register file address is first written into FSR. – It is a special purpose register that serves as an address pointer to any address through out the entire register file. • INDF – (Indirect File): – It is not a physical register addressing, this INDF will cause indirect addressing. – Any instruction using the INDF register actually access the register pointed to by the FSR.
  • 23.
    PIC Registers • PCL: –PCL is actually the lower 8-bits of the 13-bit program counter. – It can be read like any other register. • PCLATH (Program Counter Latch): – Upper bits of are not readable but are indirectly writable . – The upper 3-bits of PCLATH remains zero and serves no purpose. Progarm Counter :
  • 24.
    Watch Dog Timer(WDT): A Watch dog timer is a simple timer circuit that performs a specific operation after a certain period of time if something goes wrong.
  • 25.
    Pipelining • Overlapped movementof instruction to the processor is called pipelining.
  • 26.
  • 28.
    Program Memory Considerations Programmemory access for PIC parts having 2K of program memory. • PIC family uses 13-bit program counter allowing the controllers to an 8k- program memory without changing the CPU structure.
  • 29.
    Program Memory Considerations Programmemory access for PIC parts having 4K of program memory.
  • 30.
    Program memory andStack memory
  • 31.
    Two addresses inthe program memory address space are treated in a special way by the CPU. • When the CPU starts up from its reset state, its program counter is automatically cleared to zero. with the content of address H'000’being a go to Mainline instruction. • The second special address H'004', is automatically loaded into the program counter when an interrupt occurs.
  • 32.
    Program Memory Addressing Usedby Subroutine calls :
  • 33.
    Data Memory The datamemory of PIC 16F8XX is partitioned into multiple banks which contain • General purpose registers • Special function Registers.(SFRs). The bits RP1 and RP0 bits of the status register are used to select these banks
  • 35.
    Data Memory Considerations PIC16C63 PIC 16C65 A PIC 16C73 A PIC 16 C74 A General Purpose Register BANK 0 BANK 1
  • 36.
  • 37.
  • 38.
  • 39.
  • 40.
    INSTRUCTION SET OFPIC • Instruction set of PIC are divided into three basic categories, • Byte Oriented Instruction • Bit Oriented Instruction • Literal and Control Instruction
  • 41.
    Byte Oriented Instruction(18 inst) f: File Register (or RAM) d: Destination d=0: Destination  W d=1: Destination  File Register
  • 42.
    Bit Oriented Instruction(4 Inst) • f: Register File where the Bit is located • b: Bit Field
  • 43.
    Literal and ControlInstruction (13 Inst) • K: 8-bit constant
  • 44.
    Classification of Instruction •Instruction set of PIC are classified into • Arithmetic Instruction • Logical Instruction • Increment/Decrement Instruction • Data Transfer Instruction • Clear Instruction • Rotate Instruction • Branch Instruction • Miscellaneous Instructions
  • 45.
    Arithmetic Instruction  ADDWF ADDLW  SUBWF  SUBLW
  • 46.
  • 47.
  • 48.
  • 49.
  • 50.
  • 51.
  • 52.
  • 53.
  • 54.
    Logical Instruction  ANDWF ANDLW  IORWF  IORLW  XORWF  XORLW  COMF
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  • 74.
    Data Transfer Instruction MOVF  MOVWF  MOVLW
  • 75.
  • 76.
  • 77.
  • 78.
  • 79.
  • 80.
  • 81.
    Clear Instruction  CLRF CLR W  BCF  BSF
  • 82.
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  • 97.
    Branch Instruction  BranchInstructions are classified into  Conditional Branch  Unconditional Branch
  • 98.
    Conditional Instruction  BTFSC BTFSS  DECFSZ  INCFSZ
  • 99.
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  • 101.
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  • 107.
    Unconditional Instruction  CALL GOTO  RETURN  REETLW  RETFIE
  • 108.
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  • 113.
  • 114.
  • 115.
  • 116.
    SLEEP • Stop clock •Reduce Power • Wait for watchdog timer or external signal
  • 117.
    CLRWDT • If watchdogtimer is enabled, this instruction will reset it (before it resets the CPU)
  • 118.
  • 119.
  • 120.
    Reference : • Peatman,J.B.,“Design with PIC Micro Controllers”PearsonEducation,3rdEdition, 2004. • Mazidi, M.A.,“PIC Microcontroller” Rollin Mckinlay, Danny causey Printice Hall of India, 2007.