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1.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 01 | Jan-2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 356 A Review of High Throughput Polar Encoder Rohan B. Pachange1, A. M. Shah2 1Electronics and Telecommunication Department, GCOE, Amravati (MH), India 2Assistant Professor, Electronics and Telecommunication Department, GCOE, Amravati (MH), India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - In recent years the polar codes have become insane popular due to channel achieving capacity specifically in symmetric binary memoryless channels hence also become the most favorable error correcting codes. The polarcodesare constructed using the method of channel polarization, the channel capacity has been achieved asymptotically. In polar code transmission, the channel is divided into thetwosections: complete noisy and noiseless channels. Inspired by the rapid progress of polar codes, we propose a pipelined architecture for the FPGA implementation of polar code encoding. Key Words: Polar codes, channel achieving capacity, error correcting codes, channel polarization, FPGA. 1.INTRODUCTION In digital communication theory, the errors have been observed while retrieving the transmitted data which are introduced due to the noise. To suppress the effect of noise use of error-correcting codesis advisable. From single error in the recovered bit sequence to long length the probability of getting errors in the recovered bit sequence also increases to suppresssuch errorserrorcorrectingcodes like Hamming code, LDPC code, turbo code, Polar code are used. In information theory, the points to take into consideration are compression, errorless transmission, and the channel capacity. The symmetric capacity I(w) of any given Binary discrete memoryless channel can be achieved by the code sequence constructed using the method of channel polarization. The symmetric capacity canbedefined as the highest rate achievable subject to using the input letters of the channel with equal probability. The main motivation is to come across a family of codes that are provably capacity achieving. Polar codes are noticeable due to its recursive structure which leads to low complexity encoding and decoding algorithm. The basic idea behind the polar coding can be explained as think of two channels let they are close to each other with respect to some metric; typically probability of error but many times mutual information. Hence the main requirement is the approximated channel must be a “pessimistic” versionofthe true channel so that the approximated set of good channels will be a subset of the true set. When compared with the complementary codes, polar codes achieve better error correcting performance when code length ranging from 28 to 216, also 16384 bytes is the normal memory requirement when a typical message is protected by the polar error correcting codes or termed polar coding. Consider, W(X, Y) be a generic B-DMC with inputalphabet X, output alphabet Y and transition probabilitiesW(y|x),xϵX,y ϵ Y. Since the channel is binary input would be always {0,1} the output alphabet and the transition probabilities may be arbitrary. To measure the rate and reliability Symmetric capacity and the Bhattacharya parameter are used: Symmetric capacity: Bhattacharya parameter: Where I(W) is the highest rate at which reliable communication is possible across W using the inputs of W with equal frequency. 1.1 Problem Formulation Designing a polar code is almost an analogous task to find out the set of good indices. The output alphabet of WN (i) is YN * {0,1}i. The number of output alphabet for a particular channel at level n is exponential in the block length. Hence the exact computation of the transition probabilities becomes unmanageable and hence there is need of some efficient method to approximate these channels. Quantization is a method that can be helpful in estimating the Bhattacharyya parameter. But in the quantization method, there is the occurrence of the quantization error which can be defined as the difference between the true set of good indices and the approximate set of good indices. Hence a suitable formulation of the quantization problem is to introduce the various methods to replace each channel say with , where is polar degraded with respect to such that the number of output alphabets is limited to number of channels, the set of good indices obtained with this procedure is a subset of the true set of good indices obtained from the channel polarization.
2.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 01 | Jan-2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 357 Algorithms for Quantization: To compute the Bhattacharyya parameter the method of quantization can be implemented by using various algorithms 2. METHODOLOGY Mainly the polar code makes the use of the phenomenon of channel polarization that each channel tends to approach perfectly reliable or completely noisy channel. For the process of encoding of polar code, it's importantto take into consideration that they belong to linear block codes. While implementing the polar code encoder it is prime important to make it less complex. From the available data the size of a message protected by an error-correcting code in storage is 4096 byte and also presumed that it will rise to 8192 bytes in near future, as per the literature reviewed it is true that polar codes are associated with theless complexity butwhile dealing with the considerable size of long polar codes, it is seen that it suffers from severe hardware complexity and long latency. Fig.1 Fully parallel 16-bit polar encoder architecture [1] As mentioned the code length solely increases the hardware complexity. So as to make implementation feasible another approach has been taken into consideration i.e. partially parallel polar code encoder. 3. CONCLUSIONS In this paper, we have taken into consideration the implementation of the polar encoder using the partially parallel architecture, which in turn leads to our main objective of reducing hardware complexity for long length polar codes. From the future perspective, wehavethoughtof providing the pipelined architecture so as to achieve optimum hardware with less number of resources used. REFERENCES [1] Alok Arpure, Somulu Gugulothu, “FPGA Implementation of Polar Code Based Encoder Architecture”, International Conference on Communication and Signal Processing, April 6-8, 2016, India [2] Erdal Arıkan, Senior Member, IEEE, “Channel Polarization: A Method for Constructing Capacity- Achieving Codes for Symmetric Binary-Input Memoryless Channels”, EE TRANSACTIONS ON INFORMATION THEORY, VOL. 55, NO. 7, JULY 2009 [3] Ramtin Pedarsani, S. Hamed Hassani, IdoTal, Emre Telatar School of Computer and Communication Systems, EPFL, “On the Construction of Polar Codes”, 2011 IEEE INTERNATIONAL SYNOPSIUM ON INFORMATION THEORY PROCEEDINGS [4] Alptekin Pamuk Department of Electrical-Electronics Engineering Bilkent University Ankara, TR-06800, Turkey apamuk@bilkent.edu.tr, “An FPGA Implementation Architecture for Decoding of Polar Codes”, 2011 8TH INTERNATIONAL SYMPOSIUM ON WIRELESS COMMUNICATION SYSTEMS, AACHEN. [5] Hoyoung Yoo, Student Member, IEEE, andIn-CheolPark, Senior Member, IEEE, “Partially Parallel Encoder Architecture for Long Polar Codes”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 62, NO. 3, MARCH 2015 [6] Mamatha.Sarah. ,Oommen, S.Ravishankar, “FPGA Implementation of an Advanced EncodingandDecoding Architecture of Polar Codes”, 2015 International Conference on VLSI Systems Architecture, Technology and Applications (VLSI-SATA) Rohan B. Pachange was born in 1995. He received the B.E. (Electronics and Communication) degree from the Government College of Engineering, Aurangabad (MH), in 2016. His research interests include embedded system, VLSI and wireless communication. He is currently pursuing M. Tech. (Electronics System and Communication) at Government College of Engineering, Amravati (MH). hor Photo BIOGRAPHY:
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