This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
Low Power and Area Efficient Multiplier
Layout using Transmission Gate
Sahil Gargi
ME Student (ECE)
National Institute of Technical Teachers’ Training & Research Chandigarh, India-160019
sahil1038@gmail.com
Abstract: This paper proposes the design and implementation
of a 2-bit multiplier using fully automatic design and semi-
custom design. Any digital signal processor has adder and
multiplier in its core unit. Low power and high speed mac
units are in high demand and therefore make a significant
place in today’s vlsi environment. Power consumption of
cmos circuits is a major concern in vlsi design. The proposed
design is made using transmission gate logicwhich helped in
using less number of cmos. The multiplier circuit is first
simulated using avlsi cad tool and thus the layout was
generated. The proposed circuit is simulated by using 90nm
cmos technology with supply voltage of 1.2v. It is found that
semi-custom based design produced better results in terms of
power dissipation and area.
Keywords: Multiplier, VLSI, Transmission Gate, CMOS,
Power, Area.
1. INTRODUCTION
In most of the VLSI applications arithmetic operations like
addition, subtraction, multiplication are commonly used.
The time required for multiplication is one of the most
dominant factor to evaluate the time needed for instruction
cycle of a DSP chip. Performance of a DSP chip is largely
limited by its multiplication performance. Demand and
popularity of various devices depends on the small silicon
area, higher speed, longer battery life and reliability [1].
For VLSI design, emphasis is generally laid on three
constraints that is, power, area and delay. Interest has now
widely grown in optimizing and minimising the chip area
with least power consumption and still maintaining high
performance.Statics shows that more than 70% instructions
in microprocessor and most of DSP algorithms perform
addition and multiplication [2]. Thus a multiplier plays a
pivotal role in modern VLSI design and a high speed
multiplier with low power consumption is the need of the
hour. Minimising the power consumption is still a major
concern for designers. Most techniques for saving power
involve scaling of the power supply, which resulted in
substantial increase in the leakage current. It has been
found that there is fundamental connection between
computation and power dissipation [3]. A method is
proposed to somehow reduce the computation without any
loss of information. Thus, with reduced computation, there
is a reduction in power consumption in the design process.
In this paper a fully automatic design is compared with
semi-custom design in terms of all the design constraints.
Binary multiplication can be performed using number of
techniques. Parallel multiplication uses an array or tree of
adders (half or full) to sum the partial products. A n*n
multiplier requires, n*(n-2) full adders, n half-adders and
n2
AND gates [4]. Shift and add algorithm was the
conventional technique used to implement the design. It
involved the basic multiplication principle. The partial
products are generated by the multiplication of the
multiplicand with one multiplier digit followed by addition
of shifted partial products. Traditionally shift and add
algorithm has been implemented to design however this is
not suitable for VLSI implementation and also from delay
point of view[4]. Main advantage of binary multiplication
is that the generation of intermediate products are easy [2].
Generally this technique of multiplicationisslow and
accumulates a lot of area in hardware. Thus requires more
power.
With the help of Transmission Gate Logic (TGL) there is
reduction in leakage power and leakage current in active
mode [5]. TGL has proved to be an attractive alternative to
static CMOS designs with respect to area, performance and
power consumption [6]. It will improve the overall
performance.It is designed by connecting both source to
source and drain to drain terminals of NMOS and PMOS
transistors [7].This logic style has a great functionality that
can reduce the number of transistor counts [8]. A design
with a high speed is resulted using a TGL with a reduced
transistor count. Thus optimised low power circuit design
is obtained. As the NMOS transistor is passing strong ‘0’
signal and PMOS transistors passes strong ‘1’ signal
towards the output, the both transistors are turn on/off by
an enable signal [7].Inverter followed by Transmission
gate structure appears in many CMOS circuit design
[9].The multiplier is constructed using AND gates and half
adder. The half adder is made using transmission gate
which is made using EX-OR and AND gates. The
multiplier is schematised by DSCH3.1 CAD tool and its
layout is generated using CMOS 90nm technology in
Microwind 3.1 CAD tool [10].
2. MULTIPLIER DESIGN
This paper presents design approach for a 2-bit multiplier.
Two types of multiplier designs are proposed here using
Ex-OR and AND gates. A 2-bit multiplier will have a1, a0,
b1, b0 as inputs and z3, z2, z1, z0 as outputs. The truth
table is shown in Table 1.
Table 1: Truth table of 2-bit multiplier
Inputs Outputs
a1 a0 b1 b0 z3 z2 z1 z0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1 1

2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 86
1 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1 1
1 1 0 0
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
In Fully Automatic (FA) Design approach, the design is
created using DSCH3.1 CAD tool. DSCH is used to
validate the architecture of the logic circuit before the
microelectronics design is started [11]. CMOS circuits is
used to create AND gate and half-adder.Transmission
gatelogic style of 2-bit multiplier shown in Fig. 1is used
which helped in reducing the number of CMOS.
Fig. 1 CMOS design in DSCH
The corresponding simulation or behavior in DSCH to
check the functionality is shown in Fig. 2.
Fig. 2 Simulation results in DSCH
The layout of the multiplier is generated using
Microwind3.1 CAD tool by compiling a Verilog file that
was created in DSCH.Its corresponding simulation results
along with power are shown in Fig. 3. And the
corresponding Auto Generated layout is created as shown
in Fig. 4.
Fig. 3 Simulation results of FA design
Fig. 4Layout of FA design
In Semi-Custom (SC) Design approach, the layout is
directly made in Microwind3.1 using MOS generators.
Similar to fully automatic design, transmission gatelogic
style is also used here. But the only difference is that both
NMOS and PMOS are made using this MOS generator.
That is if somehow computation could be implemented
without any loss of information, then energy required by it
could be potentially reduced by a large amount [3]. The
main advantage of using semi-custom design approach is
the reduction in computations without any loss of
information. With reduced computation, the chip area and
power consumption is optimised to a significant level. The
layout of 2-bit multiplier using semi-custom design is
shown in Fig. 5. It can be clearly seen the semi-custom
design occupies less chip area as compared to fully
automatic.
Fig. 5Layout of SC design

3. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
87 NITTTR, Chandigarh EDIT-2015
The simulation results for the SC design are shown in Fig.
6. The Simulation results of both designs appear to be
similar implying that there is no loss of information in
semi-custom approach. However the power consumed in
semi-custom is quite low as compared to fully automatic
design.
Fig. 6Simulation results of SC design
3. RESULTS AND DISCUSSIONS
The proposed designs of 2-bit multiplier using
transmission gates logic for fully automatic and semi-
custom is simulated using Microwind CAD tool. A
comparison on the basis of Power and Area is shown in
Table 2. Firstly we can state that the semi-custom design
approach (the conventional one or with transmission gate)
produce better results based on power and chip area.
Secondly, the logic design with transmission gate logic
will give optimised results in terms of power and chip area.
A comparison graph between all design constraints is
shown in Fig. 7.
Table 2: Comparison of multiplier design techniques
Fig. 7 Graphical comparison between various designs
4. CONCLUSION
This paper concludes that a 2-bit multiplier is best
implemented using semi-custom approach. A reduction of
25.45% in power is achieved by semi-custom transmission
gateas compared to fully automatic transmission gatelogic.
Also a reduction of 20% in chip area is obtained because of
the property of transmission gate which allows usage of
less number of CMOS. Despite reduction in power
consumption and chip area, still the proposed design
maintains high performance without any loss of
information.
REFERENCES
[1] Rajesh Mehra, Anjali Sharma, “Area and Power Efficient CMOS
Adder Design by Hybridizing PTL and GDI Technique”, International
Journal of Computer Applications, Vol. 66, No. 4, pp. 15-22, 2013.
[2] Soniya, Surech Kumar, “A Review of Different Type of Multipliers
and Multiplier-Accumulator Unit”, International Journal of Emerging
Trends & Technology in Computer Science (IJETTCS), Vol.2, Issue 4, pp
364-368, 2013.
[3] Rajesh Mehra, Richa Singh, “Power Efficient Design of Multiplexer
Using Adiabatic Logic”, International Journal of Advancesin Engineering
& Technology (IJAET), Vol.6, Issue 1, pp. 246-254, 2013.
[4] Sumit Vaidya, Deepak Dandekar, “Delay-Power Performance
Comparison of Multipliers in VLSI Circuit Design”, International Journal
of Computer Networks & Communications (IJCNC), Vol. 2, No. 4, pp.
47-56, 2010.
[5] AbhishekDikshit, SaurabhKhandelwal, ShyamAkashe, “Power
Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with
Power Gating Technique”, International Journal of Computer
Applications, Vol. 99, pp. 37-42, 2014.
[6] Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen,
“An Efficient Pass-Transistor-Logic Synthesizer Using Multiplexers and
Inverters Only”, IEEE International Symposium on Circuits and Systems
(ISCAS), Vol.3, pp 2433-2436, 2005.
[7] AmreenParveen,Subhasis Bose, SachinBandewar “A High Speed
Transmission Gate Logic Base 1/N Frequency Divider Digital Parallel
Counter Design”, International Journal of Engineering and Management
Research, Vol. 4,Issur 3,pp 132-134, 2014.
[8] K. Purnima, S. AdiLakshmi, M. Sahithi, A. Jhansi Rani, J. Poornima,
“Design of Modified Shannon Based Full Adder Cell Using PTL Logic
for Low Power Applications”, International Journal of Computer Science
and Information Technologies, (IJCSIT) ,Vol.3, No.1, pp. 2964-2968,
2012.
[9] V. Sreelakshmi, Dr. K. GnanaSheela, “A Survey on Analytical Delay
Models for CMOS Inverter-Transmission Gate Structure”, International
Journal of Science and Research (IJSR), Vol. 3, Issue 11, pp. 1324-1330,
2014.
[10] Rajesh Mehra, Meena Aggarwal, Aastha Agarwal, “4-Input Decimal
Adder Using 90 nm CMOS Technology”, IOSR Journal of Engineering
(IOSRJEN), Vol. 3, Isseu 5, pp. 48-51, 2013.
[11] User’s Manual of Microwind & DSCH Version 3.1, pp. 5-9, 2006
Paramet
er
Conventio
nal FA
design
Convention
al SC
design
TG
FA
desig
n
TG
SC
desig
n
Power(m
W)
0.265 0.210 0.220 0.164
Area
(um2
)
841.5 623.7 526.5 421.2