This module deals with JFET biasing and its different configurations.

1. FET BIASING

2. INTRODUCTION
• For the field-effect transistor, the relationship between input and output
quantities is nonlinear due to the squared term in Shockley’s equation.
• The nonlinear relationship between ID and VGS can complicate the mathematical
approach to the dc analysis of FET configurations.
• A graphical approach may limit solutions in accuracy, but it is a quicker method
for most FET amplifiers. We use graphical solutions rather than mathematical
solutions, as the formers are easier.

3. • The general relationships that can be applied to the dc analysis of all
FET amplifiers are:
• For JFETs, Shockley’s equation is applied to relate the input and
output quantities:

4. FIXED-BIAS
CONFIGURATION

5. • Fixed bias configuration can be
solved just as directly using either a
mathematical or a graphical
approach.
• The coupling capacitors are “open
circuits” for the dc analysis.
• The resistor RG is present to ensure
that Vi appears at the input, to the
FET amplifier for the ac analysis.

6. • For the dc analysis,
• The zero-volt drop across RG permits
replacing RG by a short-circuit
equivalent, as appearing in the network.
• Applying KVL,

7. • Applying KVL,

8. GRAPHICAL ANALYSIS
• A graphical analysis would require a plot of
Shockley’s equation.
• The fixed level of VGS has been superimposed
as a vertical line at VGSQ = -VGG.
• At any point on the vertical line, the level of
VGS is (–VGG.)
• The point where the two curves intersect is
commonly referred to as the quiescent or
operating point.

9. Ex:1) Determine the following for the network:
a)VGSQ b)IDQ c)VDS d)VD e)VG f)VS

10. Graphical approach

11. SELF-BIAS
CONFIGURATION

12. • The self-bias configuration
eliminates the need for two
dc supplies. An additional
resistor is introduced at
the source terminal, for the
stability of the Q-point.
• The controlling gate-to-
source voltage is now
determined by the voltage
across the resistor RS
introduced in the self-bias
configuration, as shown.

13. • For the dc analysis, the capacitors can again be
replaced by “open circuits” and the resistor RG
replaced by a “short-circuit”, since IG = 0 A.
• The current through RS is the source current IS;
but IS = ID and VRS = ID.RS
• Applying KVL,

14. • In case of self bias, unlike fixed bias, VGS is a function of the
output current ID, and is not fixed in magnitude.
• A mathematical solution could be obtained by substituting VGS
into Shockley’s equation as follows:
This results in a quadratic equation, which can be solved for obtaining ID.

15. • Applying KVL,

16. Graphical Solution
• The graphical approach requires that we first
establish the device transfer characteristics.
• Equation VGS = -ID.RS defines a straight line on the
same graph.
• To Identify the two points to draw the line, apply
ID=0 A, which gives, VGS = -ID.RS = (0)RS = 0 V.
• The second point requires that a level of VGS or ID
be chosen. we choose a level of ID equal to one-half
the saturation level.

17. Ex:2) Determine the following for the network, using the graphical method:
a)VGSQ b)IDQ c)VDS d)VS e)VG f)VD
From the given values of IDSS and VP, the characteristic curve can be plotted, as shown.
Further, the gate-to-source voltage is determined by, VGS = -IDRS . For ID = 4 mA, VGS = -4V.
From this value, a straight line can be drawn, as shown:

18. a) The resulting operating point results in a
quiescent value, VGSQ = -2.6 V.
b) At the Q-point, IDQ = 2.6 mA.
c)
d)
e) VG = 0 V.
f)

19. VOLTAGE-DIVIDER
BIASING

20. • The circuit is similar to that of BJT.
As that of self-bias, graphical analysis
is preferred here, as the mathematical
analysis is more complicated.
• For DC Analysis:
• All the capacitors, including the
bypass capacitor CS , have to be
replaced by an “open circuit”
equivalent.
• VDD can be separated into two
equivalent voltage sources, to
permit a further separation of the
input and output regions of the
network.

21. • Since IG = 0 A, Applying KCL, we have IR1 = IR2.
• Using voltage-divider rule, the voltage VG is given by,
• Appling KVL,
• Substituting VRS = IS.RS = ID.RS,
• Equation of VGS is still the equation for a straight line,
but the origin is no longer a point in the plot of the line.
• The quantities VG and RS are fixed by the network
construction. Substituting for VGS in Shockley’s equation,
the expression for ID is obtained as,

22. Graphical Solution
• Since any straight line requires two
points to be defined, anywhere on
horizontal axis ID=0, yielding-
• For the other point, let us substitute
VGS=0, and solve for the value of ID -

23. Increasing the
values of RS
results in lower
quiescent values
of ID and declining
values of VGS.
Applying KVL,

24. Ex:3) Determine the following for the network:
a)VGSQ b)IDQ c)VD d)VS e)VDS f)VGD

25. a) From Graph:
IDQ = 2.4 mA and VGSQ = -1.8 V
b) VD = VDD - IDRD
= 16 V - (2.4 mA)(2.4 k)
= 10.24 V
c) VS = IDRS = (2.4 mA)(1.5 k)
= 3.6 V
d) VDS = VDD - ID(RD + RS)
= 16 V - (2.4 mA)(2.4 k + 1.5 k)
= 6.64 V
e) VGD = VG - VD
= 1.82 V - 10.24 V
= -8.42 V
Biasing type Value for
VGS
Line of
VGS
Fixed bias
(2 supplies)
-VGG
Vertical line
Self bias
(single VDD)
- IDRS
Slant line that
passes through
the origin
Voltage-
divider bias
(single VDD)
VG - IDRS
Slant line does
not pass thru’
the origin

26. COMMON-GATE
CONFIGURATION

27. • In this configuration, the gate terminal is
grounded, and typically, the input signal is
applied to the source terminal, and the output
signal is obtained at the drain terminal.
• Applying KVL,
• Applying the condition, ID = 0 mA,
• Applying the condition, VGS = 0 V,

28. Applying KVL,

29. Ex:4) Determine the following for the common-gate configuration:
a) VGSQ b) IDQ c) VD d) VG e) VS f) VDS
For the transfer characteristics,
For this equation, the origin is one point on the load
line while the other point must be determined at some
other arbitrary point.
Choosing ID = 6 mA,
The resulting solution is:
a) VGSQ = -2.6 V
b) IDQ = 3.8 mA

30. c)
d)
e)
f)
in the next part …
JFET SMALL
SIGNAL MODEL