This module deals with basic JFET construction and its basic characteristics.

2. ELECTRONICS
CIRCUITSDEVICES SYSTEMS
ACTIVE ANALOGPASSIVE DIGITAL
TRANSISTORDIODE
RESISTOR
CAPACITOR
INDUCTOR
TUNNEL
ZENER
LED
VARACTOR
SCHOTTKY
BJT FET
JFET
MOSFET
POWER SUPPLIES
RADIO BROADCAST
TV BROADCAST
TELECOM
WIRELESS COMM.
SATELLITE COMM.
CELLULAR COMM.
COMPUTING
AUTOMOBILE
PROCESS CONTROL
FINFET

3. ANALOG CIRCUITS DIGITAL CIRCUITS
RECTIFIERS
AMPLIFIERS
OSCILLATORS
MODULATORS
DEMODULATORS
MIXERS
FILTERS
LOGIC GATES
FLIP-FLOPS
COUNTERS
REGISTERS
MEMORIES
μP, μC
ADDERS
MULTIPLIERS
ATTENUATORS
HYBRID CIRCUITS
SAMPLERS
ADC, DAC
ENCODERS
DECODERS
QUANTIZERS
COMPARATORS
PLL
TIMERS

4. ANALOG ELECTRONIC CIRCUITS (19ECE34)
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# Electronic
Principles,
Albert Malvino &
David Bates, 7th ed.
Electronic Devices & Circuit
Theory, Robert Boylestad &
Louis Nashelsky, 11th edition
Electronic Devices &
Circuits, Millman J.
& Halkias C., 4th ed.
1 - 4.1 to 4.5, 4.7, 4.8,
4.18 (pages 221-223),
5.4 to 5.6, 5.8, 5.9
8.9, 8.11
2 - 6.1 to 6.3, 7.1 to 7.5,
8.1 to 8.3, 8.5
-
3 16.6, 16.8, 16.9 9.1 to 9.3, 9.6 to 9.12, 5.19, 5.20 -
4 23.1 to 23.6 14.1 to 14.9 15.1 to 15.4
5 12.1 to 12.10 12.1 to 12.8 -

5. MODULE 2
JFET BIASING AND AMPLIFIERS
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ANALOG ELECTRONIC CIRCUITS
(ECE34)

6. • When VGS = 0 and VDS = VDD, electrons
are drawn towards the drain, causing
the flow of IDS.
• The n-channel acts like a uniform
resistance; i.e., when VDS is increased
starting from 0 V, the device obeys
Ohm’s law.
• The depletion region is wider at the
top region, due to the reverse bias.
When VDS is increased gradually, the
depletion regions keep on widening.
• The value of VDS at which the
depletion regions touch each other is
called pinch-off voltage (VP), because
of the pinching off of the channel.
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• Beyond pinch-off, IDS becomes
almost constant, and is denoted as
IDSS. Hence, this region in the curve
is called as “saturation” region, and
the device acts like a current source.
• IDSS is the maximum drain current
for a JFET, and is defined by the
conditions VGS = 0 V and VDS > |VP|.
• With positive values of VGS, the
device becomes a complete
conductor, and causes IGS as well.
• In order to have a control over the
conduction, VGS needs to be applied
as negative, such that saturation is
reached at a lower level of VDS.

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• As VGS becomes more and more negative, VP continues to
drop in a parabolic manner. The device will be turned off
when VGS = -VP resulting in IDS = 0 mA, as both input and
output junctions are reverse biased.
• The pinch-off voltage (VP) is negative for n-channel and
positive for p-channel JFETs.

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• The region in between the cutoff and saturation regions
is called as “ohmic” region or “voltage controlled
resistance” region. In the ohmic region, the current is
due to drift, which is because of the applied voltage.
• In the ohmic region, the JFET can be used as a voltage
controlled resistor, whose resistance is controlled by the
applied VGS. The resistance value increases with more
negative values of VGS, and is given by –
• In the saturation region, pinch-off causes IDS to become
constant. Hence, the saturation region is also called as
“constant current” region. The current in this region is
not due to drift, but due to diffusion, which is because
of the carrier concentration.

11. BJT JFET
Bipolar
(Both electrons and holes)
Unipolar
(Either electrons or holes)
Either NPN or PNP Either N-channel or P-channel
Current controlled device
(Linear transfer curve)
Voltage controlled device
(Non-linear transfer curve)
Emitter, Base and Collector Source, Drain and Gate
Cut-off, active, saturation Cut-off, saturation, ohmic
Emitter and Collector are
physically different.
Source and Drain are physically
identical.
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12. BJT JFET
Finite Base current No Gate current
Finite input impedance Very high input impedance
Better as amplifier (large gain,
due to higher sensitivity)
Better as switch (sharp curve,
due to less temp. dependence)
Larger in size Smaller in size
Difficult to fabricate Easier to fabricate
Larger gain-BW product Smaller gain-BW product
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p-Channel Device
• At high levels of VDS, the current suddenly rises, leading to
breakdown region. Hence, care should be taken during design.
• This phenomenon occurs with n-channel devices also, but at a
larger value than that of p-channel devices.

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Symbols of n-ch and p-ch JFETs
• The maximum current is defined as IDSS, and it occurs when
VGS = 0 V and VDS ≥ |VP|.
• The drain current is zero, when VGS is more negative than VP.
• For the values of VGS in between 0 and VP, the drain current
will respectively range between IDSS and 0.
Summarized points for n-ch JFET

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TRANSFER CHARACTERISTICS
(obtained from output characteristics)
With BJT, the o/p & i/p currents are
related linearly by β. But, with JFET,
as there is no input current (IG), the
trans-relation is non-linear, and can
be defined by Shockley’s equation.

17. Exercise - 1
• Sketch the transfer curve for an n-channel
FET that has IDSS = 12 mA and VP = -6 V.
Solution:
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VGS ID
0 V 12 mA
-1.8 V 6 mA
-3 V 3 mA
-6 V 0 mA

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in the next part …
FET BIASING